VIT

UNIVERSITY

ECE 301 - VLSI System Design

(Fall 2011)

Lexical Conventions of Verilog HDL

Prof.S.Sivanantham School of Electronics Engineering VIT University Vellore, Tamilnadu. India E-mail: ssivanantham@vit.ac.in

Objectives
After completing this lecture, you will be able to:
Explain the rules and regulations for comments, white space and identifiers Appropriately and effectively utilize Verilog operators

ECE301 VLSI System Design

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S.Sivanantham

Lexical Conventions
Lexical conventions Comments Numbers Strings Identifier Operators

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Comments and Spacing

// A one-line comment starts with // and ends with newline character /* A block comment starts anywhere with /* and ends anywhere with */ Do not clutter your source module muxadd (a, b, sel, sum, carry, y); input a, b, sel; // module inputs output /* module outputs */ sum, carry, y; ...
with comments that state the obvious!

// Verilog is a free-format language // White space is needed only to separate some language tokens // Use additional white space p to enhance readability y assign sum = a ^ b; assign carry = a & b; // Also use indentation ( (2 space p is best) ) to enhance readability y always @(a or b or sel) if (sel == 1) y = b; else y = a; ...
ECE301 VLSI System Design FALL 2011 S.Sivanantham 1.4

Lexical Conventions: Identifiers

Identifiers Names g given to objects j Cannot start with a number or dollar sign ($) Can start with alphabetic character or underscore
wire a1; output sum; // wire is a keyword, a1 is an identifier // output is a keyword keyword, sum is an identifier

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Identifier Naming Rules

Identifiers start with a letter or an underscore (_) Subsequent characters may be letter, digit, dollar sign ($) or underscore Verilog does not restrict name length Tool or methodology may restrict name length l h Identifiers are case sensitive ABC, Abc, abc are all different legal names

Not Legal unit-32 16_bit_bus $abc

Legal unit_32 bus_16_bits abc$ Escaped \unit-32 \16_bit_bus \$abc

Keywords are all lowercase

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Lexical Conventions: Numbers (1)

Sized numbers are represented as <size> '<base format> <number> <size> is written only in decimal and specifies the number of bits in the number Legal g base formats are decimal ( ('d or 'D), ) hexadecimal ( ('h or 'H), binary ('b or 'B) and octal ('o or 'O). Examples
5`b10111 // 5-bit 5 bit binary bi number b 16`hcdab // 16-bit hexadecimal number 3`d7 // 3-bit decimal number

Unsized numbers
16549 // 32-bit decimal number by default 'hc3 hc3 // This is a 32-bit 32 bit hexadecimal number `o21 // 32-bit octal number
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Lexical Conventions: Numbers (2)

x or z values : Verilog has two symbols for unknown and high impedance values. x unknown value z high impedance value Examples:
16`h536x 16 h536x // This is a 16-bit 16 bit hexadecimal value with 4 least significant bits unknown 6'hx // This is a 6-bit hex number 32'bz // This is a 32-bit high impedance number

Negative numbers Number with a minus sign before the size of a constant number Examples:
-6'd3 4'd-2
// 8-bit negative number stored as 2's complement of 3 // Illegal specification

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Lexical Conventions: Numbers (3)

Underscore, Question mark _ character anywhere y in a number except p the first character
16`b1010_0110_1101

? ? question mark substitutes z in numbers for better readability

4'b10?? // Equivalent of a 4'b10zz

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Lexical Conventions: Numbers - Examples

Number 4d3 8ha 8o26 8 o26 5b111 8b0101_1101 8bx1101 -8d6 8`b01??_11??

Decimal Equivalent q 3 10 22 7 93 -6

Actual Binary y 0011 00001010 00010110 00111 01011101 xxxx1101 11111010

equivalent to a 8`b01zz_11zz

Numbers with MSB of x or z extended with that value

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Lexical Conventions: Strings

A string is a sequence of characters that are enclosed by double quotes. The restriction on a string is that it must be contained on a single line, that is, without a carriage return. It cannot be on multiple lines. lines Strings are treated as a sequence of one-byte ASCII values. Examples:
Verilog HDL Concepts

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Operators
Topics: Category reduction arithmetic shift relational equality bit-wise logical conditional concatenation replication Symbol(s) & ~& | ~| ^ ~^ ^~ ** * / % + << >> <<< >>> < > <= >= == != === !== ~ & | ^ ~^ ! && || ?: {} {{}}

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Unary Reduction Operators

and or xor nand nor xnor & | ^ ~& ~| ~^ ^~
module reduction; localparam [3:0] CONST_A = 4b0100, CONST_B = 4b1111; reg val; l initial begin val val val val val val val val val end endmodule

Reduction operators perform a bitwise operation on all the bits of a single operand The result is always 1b0, 1b1 or 1bX

= = = = = = = = =

&CONST_A ; |CONST_A ; &CONST_B ; |CONST_B ; ^CONST_A ; ^CONST B ; ^CONST_B ~|CONST_A; ~&CONST_A; ^CONST_A && &CONST_B;

// // // // // // // // //

0 1 1 1 1 0 0 1 1

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Arithmetic Operators
Verilog-1995: add + subtract multiply * divide / modulus % An A i integer t is i signed i d A reg is unsigned Verilog-2001: power operator ** You can declare a reg signed g and You can cast between signed unsigned expressions using $signed and $unsigned
module arithops; localparam integer CONST_INT = -3, CONST_5 = 5; localparam [3:0] rega = 3, regb b = 4b1010, 4b1010 regc = 14; integer val; reg g [3:0] num; initial begin val val val num num num num end endmodule

= = = = = = =

CONST_5 * CONST_INT; (CONST INT + 5)/2; (CONST_INT CONST_5/CONST_INT; rega + regb; rega + 1; CONST_INT; regc % rega;

// // // // // // //

-15 1 -1 1101 0100 1101 0010

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Shift Operators
Verilog-1995: logical shift >> <<
module shift; reg [7:0] rega = 8b10011001; reg signed [7:0] regs = 8b10011001; reg [7:0] regb; initial begin regb regb g regb regb regb end endmodule

Ignores operand signs Fills extra bits with 0 Implements division or multiplication by powers of two

Verilog-2001: arithmetic shift

= = = = =

rega rega g regs regs rega

<< 1; >> 1; <<< 1; >>> 1; << -1;

// // // // //

00110010 01001100 00110010 11001100 00000000

<<< >>>

-1 is 2**32-1

Ignores right operand sign Left shift operates like logical left shift Right shift preserves the left operand sign if the result is a signed expression

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Relational Operators
less than greater than less than or equal q to greater than or equal to < > <= >=
module relationals; reg [3:0] rega, regb, regc; reg val; initial i i i l begin rega = 4b0011; regb = 4b1010; regc g = 4b0x10; val val val val end endmodule = = = = regc regb regb regb > rega ; < rega ; >= rega; > regc ; // // // // val val val val = = = = X 0 1 X

The result is: 1b0 if the relation is false 1b1 if the relation is true 1bx if either operand p contains any y z or x bits

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Logical Equality and Case Equality Operators

logical equality == Result can be unknown
0 1 Z X 0 1 0 X X 1 0 1 X X Z X X X X X X X X X
... a = 2b1x; b = 2b1x; if (a ( == b) // values match & do not contain Z or X else // values do not match or contain Z or X // above values execute this else branch

case equality

===
... a = 2b1x; 2 b = 2b1x;

Result is always known

0 1 Z X

0 1 0 0 0

1 0 1 0 0

Z 0 0 1 0

X 0 0 0 1

if (a === b) // values match exactly y // above values execute this else branch else // values do not match

Called case case equality equality because the case statement matches items this way.

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More about Equality Operators

logical equality == logical inequality case equality q y === case inequality !== !=
module equalities; reg [3:0] rega, regb, regc; reg val; initial i i i l begin rega = 4b0011; regb = 4b1010; regc g = 4b1x10; val val val val val val val val end endmodule = = = = = = = = rega rega regb regc rega rega regb regc == regb; != regb; != regc; == regc; === regb; !== regc; === regc; === regc; // // // // // // // // val val val val val val val val = = = = = = = = 0 1 X X 0 1 0 1

For logical g equalities, q , the result is always 1b0, 1b1 or 1bX For case equalities, the result is always 1b0 or 1b1

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Bit-Wise Operators
not and or xor xnor xnor ~ & | ^ ~^ ^~
module bitwise; reg [3:0] rega, regb, regc; reg [3:0] num; initial i i i l begin rega = 4b1001; regb = 4b1010; regc g = 4b11x0; num num num num num num end endmodule = = = = = = ~rega; rega & rega & rega | regb & regb | // // // // // // num num num num num num = = = = = = 0110 0000 1000 1011 10x0 1110

Bit-wise operators operate on vectors Operations are performed bit by bit on individual bits Unknown bits in an operand do not necessarily lead to unknown bits in the result

0; regb; regb; regc; regc;

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Logical Operators
not and or ! && ||
module logical; localparam integer FIVE = 5; localparam [3:0] CONST_A = 4b0011, CONST_B = 4b10xz, CO S C = 4b0z0x; CONST_C 4b0 0 reg ans; initial begin g ans ans ans ans ans ans end endmodule

Logical operators interpret their operands as either true (1b0) or false (1b1) or unknown (1bX) 0 if all bits 0 1 if any bit 1 X if any bit is Z or X and no bit is 1

= = = = = =

!CONST_A; CONST_A && CONST_A || CONST_A && CONST A && CONST_A CONST_C ||

// 0; // 0; // FIVE; // CONST_B; CONST B; // 0; //

0 0 1 1 1 X

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Conditional Operator
conditional ?:
module tribuf1 (a, en, y); input a, en; output y; assign y = en ? a : 1bZ; endmodule d d l

a en

module tribuf2 (a, en, y); input a, en; output reg y; always @(a or en) y = en ? a : 1bZ; endmodule module tribuf3 (a, en, y); input a, en; output reg y; always @(a or en) if (en) y = a; else y = 1bZ; endmodule d d l

Sometimes the conditional operator is more readable than the if statement. Sometimes not not...

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Concatenation Operator
concatenation {} Can select and join bits from different vectors to form a new vector Can reorganize vector bits to form a new vector
endian di swaps rotate
module concatenation; reg [7:0] rega, regb, regc, regd, new; reg [3:0] nib1, nib2; initial begin rega = regb = regc = regd =

8b00000011; 8b00000100; 8b00011000; 8b11100000;

new = {regd[6:5], regc[4:3], regb[3:0]}; // new = 8b11_11_0100 new = {2b11, regb[7:5], rega[4:3], 1b1}; // new = 8 8b11 b11_000_00_1 000 00 1 new = {regd[4:0], regd[7:5]}; // rotate regd right 3 places // new = 8b00000_111 {nib1, nib2} = rega; // nib1 = 40000, nib2 = 40011 end

Can use on either side of an assignment!

Literals in a concatenation must be explicitly sized so that all the bits go into the correct position.

endmod le endmodule

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Replication Operator
replication {{}} Reproduces a concatenation a set number of times Syntax:
{const_expr {sized_expr}} The constant number of repetitions must not have Z or X values
module replicate; reg rega = 1b1; reg [1:0] regb = 2b11; reg [3:0] regc = 4b1001; reg [7:0] bus; initial begin // single bit rega replicated 8 times b bus = {8{rega}}; {8{ }} // bus = 11111111 // 4x rega concatenated with 2x regc[1:0] bus = { {4{rega}}, {2{regc[1:0]}} }; // bus = 1111_01_01 1111 01 01 // regc concatenated with 2x regb bus = { regc, {2{regb}} }; // bus = 1001_11_11 // regc concatenated with 2x 1b1 // and replicated 2 times bus = { 2{regc[2:1], {2{1b1}}} }; // bus = 00_1_1_00_1_1 end endmodule

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Reference: Operator Precedence

Reliance on operator precedence may make your code unreadable use parentheses! Category U Unary Exponential Arithmetic Shift Relational Equality Bit-wise Symbol(s) + - ! ~ & ~& | ~| | ^ ~^ ^ ^ ^~ ** * / % + - (binary) << >> <<< >>> < <= > >= == != === !== & (binary) ^ ^ ^~ ~^ ^ (binary) (bi ) | (binary) && || ? : { } {{ }}

Logical Conditional C diti l Concatenation / Replication

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Review
How wide is the result of a logical && operation? Explain the difference between the && and & operators. TRUE or FALSE: You must explicitly p y size literals in a concatenation. Given regx = 4b0101; what is the value of { g [ ], { {3{1b0, { , regx[0]}}} g [ ]}}} }; bus = { 2{regx[3:1], Assume you have stored a four bit signed number in the unsigned reg [3:0] regb; write an arithmetic binary division by two that preserves the sign bit.

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