IT6263

Single Chip De-SSC LVDS to HDMI Converter

Preliminary Datasheet

ITE TECH. INC.

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IT6263 General Description

The IT6263 is a high-performance single-chip De-SSC LVDS to HDMI converter. Combined with LVDS receiver and HDMI Transmitter, the IT6263 supports LVDS input and HDMI1.3 output by conversion function. The build-in LVDS receiver can support single-link and dual-link LVDS inputs, and the build-in HDMI transmitter is fully compliant with HDMI 1.3, HDCP 1.2 and backward compatible with DVI 1.0 specification. With high speed LVDS RX, the IT6263 can support resolution up to 1080P and UXGA and 10-bit deep colors. In order to reduce the EMI noise on legacy system application, the traditional LVDS source will transmit differential signals with spread spectrum, but this spread spectrum does not be allowed for HDMI protocol. The IT6263 also build-in unique De-SSC ( De-Spread Spectrum ) function , it can help customers easily to adopt the IT6263 on the EMI-concerned platform, with SSC has been generated from LVDS source processors. The IT6263 also encodes and transmits up to 8 channels of I2S digital audio, with sampling rate up to 192kHz and sample size up to 24 bits. In addition, an S/PDIF input port takes in compressed audio of up to 192kHz frame rate. The newly supported High-Bit Rate (HBR) audio by HDMI Specifications v1.3 is provided by the IT6263 in two interfaces: with the four I2S input ports or the S/PDIF input port. With both interfaces the highest possible HBR frame rate is supported at up to 768kHz. Each IT6263 chip comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.2 standard so as to provide secure transmission of high-definition content. Users of the IT6263 need not purchase any HDCP keys or ROMs. The single chip IT6263 provides high performance, cost effective, LVDS2HDMI conversion function, and it can be applied to IP TV STBs and Scaler Boxs which need small size video outputs.

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IT6263 Features ( LVDS RX )

Support LVDS Input modes: Single Link, Dual Link Support input clock rate up to 150MHz Support input color depth up to 10bit Support De-SSC ( De-Spread Spectrum ) Support Data Mapping: Open LDI, JEIDA, VESA

Features ( HDMI TX)

HDMI 1.3 transmitter Compatible with HDMI 1.3, HDCP1.2 and DVI 1.0 specifications Support deep color depth up to 12bit Support link speeds of up to 2.25Gbps (link clock rate of 225MHz ) Support Gammat Metadata packet Digital audio input interface supporting o up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and smaple sizes of 16~24 bits o S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate o Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz o Compatible with IEC 60958 and IEC 61937 o Audio down-sampling of 2X and 4X Software programmable, auto-calibrated TMDS source terminations provide for optimal source Software programmable HDMI output current level MCLK input is optional for audio operation. Users could opt to implement audio input interface with or without MCLK Integrated pre-programmed HDCP keys Purely hardware HDCP engine increasing the robustness and security of HDCP operation

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IT6263
Monitor detection through Hot Plug Detection and Receiver Termination Detection Embedded full-function pattern generator Intelligent, programmable power management

Features ( Combined )
Support up to Full-HD/1080P and UXGA(1600x1200) display format Support deep color depth up to 10bit 64-pin QFN (9mm x 9mm) package RoHS Compliant ( 100% Green available )

Ordering Information
Model IT6263FN Temperature Range 0~70 Package Type 64-pin QFN Green/Pb free Option Green

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IT6263 Pin Diagram

RXPCLK RXNCLK

ANVDD

RXPD1

RXPE1

32

31

30

29

28

27

26

25

24

23

22

21

RXPB1

20

19

18

17 16 15 14 13

XTALIN XTALOUT IVDD ANVDD RXNA2 RXPA2 RXNB2 RXPB2 AVCC RXNC2 RXPC2 ANVDD RXND2 RXPD2 RXNE2 RXPE2

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

ANVDD PCSDA PCSCL PCADR SCL_MCLK WS_SPDIF OVDD IVDD I2S0 I2S1 I2S2 I2S3 DDCSDA DDCSCL TXHPD SYSRSTN TXEMEM_VPP
12 11 10 9 8 7 6 5 4 3 2 1

APVDD

RXND1

RXNC1

RXNE1

RXPC1

RXNB1

IT6263
LVDS to HDMI QFN-64 9x9
(Top View)

RXNA1 TXAVCC33

RXPA1 PVCC2

AVCC TXAVCC18

IVDD

TXREXT

PVCC1

TXCM

Figure 1. IT6263 pin diagram

TXCP

TXAVCC18

TX0M

TX0P

TX2M

TX2P

TX1M

TX1P

IVDD
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IT6263 Pin Description

LVDS front-end interface pins
Pin Name RXNA1 RXPA1 RXNB1 RXPB1 RXNC1 RXPC1 RXND1 RXPD1 RXNE1 RXPE1 RXNCLK RXPCLK RXNA2 RXPA2 RXNB2 RXPB2 RXNC2 RXPC2 RXND2 RXPD2 RXNE2 RXPE2 XTALIN XTALOUT Direction Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Description LVDS first link negative input LVDS first link positive input LVDS first link negative input LVDS first link positive input LVDS first link negative input LVDS first link positive input LVDS first link negative input LVDS first link positive input LVDS first link negative input LVDS first link positive input LVDS negative clock input LVDS positive clock input LVDS second link negative input LVDS second link positive input LVDS second link negative input LVDS second link positive input LVDS second link negative input LVDS second link positive input LVDS second link negative input LVDS second link positive input LVDS second link negative input LVDS second link positive input Crystal clock input Crystal clock output Type LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS Analog Analog Pin No. 18 19 20 21 23 24 28 29 30 31 25 26 37 38 39 40 42 43 45 46 47 48 33 34

HDMI front-end interface pins

Pin Name TX2P TX2M TX1P TX1M TX0P TX0M Direction Analog Analog Analog Analog Analog Analog Description HDMI Channel 2 positive output HDMI Channel 2 negative output HDMI Channel 1 positive output HDMI Channel 1 negative output HDMI Channel 0 positive output HDMI Channel 0 negative output Type TMDS TMDS TMDS TMDS TMDS TMDS Pin No. 61 60 58 57 56 55

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IT6263
TXCP TXCM TREXT Analog Analog Analog HDMI Clock Channel positive output HDMI Clock Channel negative output External resistor for setting TMDS output level. Default tied to TXAVCC18 via a 698-Ohm SMD resistor. TMDS TMDS Analog 53 52 50

Digital Audio Input Pins

Pin Name SCL_MCLK WS_SPDIF I2S0 I2S1 I2S2 I2S3 Direction Input Input Input Input Input Input Description I2S serial clock input /Audio master clock input I2S word select input /S/PDIF audio input I2S serial data input I2S serial data input I2S serial data input I2S serial data input Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Pin No. 13 12 9 8 7 6

Programming Pins
Pin Name SYSRSTN DDCSCL DDCSDA PCSCL PCSDA PCADR TXHPD
TXEMEM_VPP

Direction Input I/O I/O Input I/O Input Input Input

Description Hardware reset pin. Active LOW (5V-tolerant) I2C Clock for DDC (5V-tolerant) I C Data for DDC (5V-tolerant) Serial Programming Clock for chip programming (5V-tolerant) Serial Programming Data for chip programming (5V-tolerant) Serial programming device address select HDMI TX Hot Plug Detection (5V-tolerant) Must be tied low via a resistor.
2

Type Schmitt Schmitt Schmitt Schmitt Schmitt LVTTL LVTTL LVTTL

Pin No. 2 4 5 15 16 14 3 1

Power/Ground Pins
Pin Name IVDD OVDD TXAVCC18 TXAVCC33 PVCC1 PVCC2 AVCC ANVDD APVDD GND Description Digital logic power (1.8V) I/O Pin power (3.3V) HDMI analog frontend power (1.8V) HDMI analog frontend power (3.3V) HDMI frontend core PLL power (1.8V) HDMI frontend Filter PLL power (1.8V) LVDS frontend power (3.3V) LVDS frontend analog power (1.8V) LVDS frontend PLL power (1.8V) Exposed GND pad Type Power Power Power Power Power Power Power Power Ground Ground Pin No. 10, 35, 49, 64 11 54, 59 63 51 62 22, 41 17, 27, 36, 44 32 65

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IT6263 Block Diagram

Figure 2. The IT6263 block diagram

Configuration and Function Control

The IT6263 includes two serial programming ports by default : one for interfacing with micro-controller, the other for accessing the DDC channels of HDMI link. The serial programming interface for interfacing the micro-controller is a slave interface, comprising PCSCL (Pin 15) and PCSDA (Pin 16). The micro-controller uses this interface to monitor all the statuses and control all the functions. Two device addresses are available, depending on the input logic level of PCADR (Pin 14). If PCADR is pulled high by the user, the device address is 0x9A. If pulled low, 0x98. The I2C interface for accessing the DDC channels of the HDMI link is a master interface, comprising DDCSCL (Pin 4) and DDCSDA (Pin 5). The IT6263 uses this interface to read the EDID data and perform HDCP authentication protocol with the sink device over the HDMI cable.

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IT6263 LVDS Mapping Table

Link 1 Mapping Table
LVDS OUTPUT DATA T0 T1 T2 RXA1 T3 T4 T5 T6 T0 T1 T2 RXB1 T3 T4 T5 T6 T0 T1 T2 RXC1 T3 T4 T5 T6 MAPPING MODE Open LDI/ JEIDA R14 R15 R16 R17 R18 R19 G14 G15 G16 G17 G18 G19 B14 B15 B16 B17 B18 B19 HSYNC VSYNC DE VESA R10 R11 R12 R13 R14 R15 G10 G11 G12 G13 G14 G15 B10 B11 B12 B13 B14 B15 HSYNC VSYNC DE RXE1 RXD1 LVDS OUTPUT DATA T0 T1 T2 T3 T4 T5 T6 T0 T1 T2 T3 T4 T5 T6 MAPPING MODE Open LDI/ JEIDA R12 R13 G12 G13 B12 B13 NA R10 R11 G10 G11 B10 B11 NA VESA R16 R17 G16 G17 B16 B17 NA R18 R19 G18 G19 B18 B19 NA

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IT6263
Link 2 Mapping Table
LVDS OUTPUT DATA T0 T1 T2 RXA2 T3 T4 T5 T6 T0 T1 T2 RXB2 T3 T4 T5 T6 T0 T1 T2 RXC2 T3 T4 T5 T6 MAPPING MODE Open LDI/ JEIDA R24 R25 R26 R27 R28 R29 G24 G25 G26 G27 G28 G29 B24 B25 B26 B27 B28 B29 HSYNC VSYNC DE VESA R20 R21 R22 R23 R24 R25 G20 G21 G22 G23 G24 G25 B20 B21 B22 B23 B24 B25 HSYNC VSYNC DE RXE2 RXD2 LVDS OUTPUT DATA T0 T1 T2 T3 T4 T5 T6 T0 T1 T2 T3 T4 T5 T6 MAPPING MODE Open LDI/ JEIDA R22 R23 G22 G23 B22 B23 NA R20 R21 G20 G21 B20 B21 NA VESA R26 R27 G26 G27 B26 B27 NA R28 R29 G28 G29 B28 B29 NA

RXCLK RXA/B/C/D/E* Previous Cycle

Note:

T6

T5

T4

T3 Current Cycle

T2

T1

T0

*=1 or 2, 1 for Link1, 2 for Link2

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IT6263 De-SSC Advantage and Performance

LVDS Input Conditions: Single Channel LVDS at 1080P ( Input Clk = 148.5MHz ) with +/- 5000ppm SSC LVDS Input. Output Results of HDMI Compliance Test (Measured HDMI Output Eye Diagram ): With ITE De-SSC Technology Pass, Eye Diagram is Open. ( Fig. 2 ) Without De-SSC Technology Fail, Eye Diagram is Closed and Blur. ( Fig. 3 )

Figure 3. HDMI Output Eye Diagram with De-SSC ( Pass )

Figure 4. HDMI Output Eye Diagram without De-SSC ( Fail )

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IT6263 Electrical Specifications

Absolute Maximum Ratings
Symbol IVDD OVDD TXAVCC18 TXAVCC33 PVCC1 PVCC2 AVCC ANVDD APVDD VI VO TJ TSTG ESD_HB Parameter Core logic supply voltage I/O pins supply voltage HDMI analog frontend supply voltage HDMI analog frontend supply voltage HDMI core PLL supply voltage Filter PLL supply voltage LVDS frontend power LVDS frontend analog power LVDS frontend PLL power Input voltage Output voltage Junction Temperature Storage Temperature Human body mode ESD sensitivity -65 2000 Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Typ Max 2.5 4.0 2.5 4.0 2.5 2.5 4.0 2.5 2.5 OVDD+0.3 OVDD+0.3 125 150 Unit V V V V V V V V V V V C C V

ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2. Refer to Functional Operation Conditions for normal operation.

Functional Operation Conditions

Symbol IVDD OVDD TXAVCC18 TXAVCC33 PVCC1 PVCC2 AVCC ANVDD APVDD VCCNOISE TA Parameter Core logic supply voltage I/O pins supply voltage HDMI analog frontend supply voltage HDMI analog frontend supply voltage HDMI core PLL supply voltage Filter PLL supply voltage LVDS frontend power LVDS frontend analog power LVDS frontend PLL power Supply noise Ambient temperature 0 25 Min. 1.62 2.97 1.71 2.97 1.62 1.62 2.97 1.62 1.62 Typ 1.8 3.3 1.8 3.3 1.8 1.8 3.3 1.8 1.8 Max 1.98 3.63 1.89 3.63 1.98 1.98 3.63 1.98 1.98 100 70 Unit V V V V V V V V V mVpp C C/W

Junction to ambient thermal resistance ja Notes: 1. TXAVCC18, TXAVCC33, PVCC1, PVCC2, AVCC, ANVDD and APVDD should be regulated. 2. See System Design Consideration for supply decoupling and regulation.

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IT6263
DC Electrical Specification
Under functional operation conditions Symbol Parameter VIH Input high voltage1 VIL VT VTVT+ VOL VOH IIN IOZ IOL Vswing Input low voltage1 Switching threshold1 Schmitt trigger negative going threshold voltage
1

Pin Type LVTTL LVTTL LVTTL Schmitt

Conditions

Min. 2.0

Typ

Max 0.8

Unit V V V V

1.5 0.8 1.1

Schmitt trigger positive going threshold voltage

1

Schmitt

1.6

2.0

Output low voltage1 Output high voltage

1 1

LVTTL LVTTL all all

2

IOL=2~16mA IOH=-2~-16mA VIN=5.5V or 0 VIN=5.5V or 0 VOUT=0.2V RLOAD=50 VLOAD=3.3V REXT=698 4 400 2.4 5 10

0.4 A A 16 600 mA mV

Input leakage current

Tri-state output leakage current1 Serial programming output sink current TMDS output single-ended swing3

Schmitt TMDS

IOFF VTH VTL IIN

Single-ended standby output current Differential Input high threshold Differential Input low threshold Input current

TMDS LVDS LVDS LVDS

VOUT=0 VCM = +1.2V VCM = +1.2V VCM = +2.4V/0V -100

10 100 6

A mV mV A

Notes: 1. Guaranteed by I/O design. 2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In a real serial programming environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I2C Standard. When set at maximum current, the serial programming output ports of the IT6263 are capable of pulling down an effective pull-up resistance as low as 500 connected to 5V termination voltage to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher than default. 3. Internal source turned off. Limits defined by HDMI Specifications v1.3a

Audio AC Timing Specification

Under functional operation conditions Symbol Parameter FS_I2S I2S sample rate FS_SPDIF S/PDIF sample rate Conditions Up to 8 channels 2 channels Min. 32 32 Typ Max 192 192 Unit kHz kHz

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IT6263
Operation Supply Current Specification
Symbol IIVDD_OP Parameter IVDD current under normal operation PIXELCLK 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) IIOVDD_OP OVDD current under normal operation 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) ITXAVCC18_OP TXAVCC18 current under normal operation 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) ITXAVCC33_OP TXAVCC33 current under normal operation 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) IPVCC1_OP PVCC1 current under normal operation 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) IPVCC2_OP PVCC2 current under normal operation 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) IANVDD_OP ANVDD current under normal operation 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) IAPVDD_OP APVDD current under normal operation 27MHz 74.25MHz 148.5MHz 148.5MHz(DI) IAVCC_OP AVCC current under normal operation 27MHz 74.25MHz 148.5MHz
4 4 4 4 4 4 4 4

Typ 47 96 166 144 623 615 595 672 34 36 39 39 58 57 49 50 2 5 7 7 2 6 13 13 28 36 47 59 4 12 24 13 9 9 9

Max 48 97 161 157 623 615 670 672 38 40 43 44 58 58 59 59 2 5 11 11 2 6 13 13 30 38 51 62 5 13 27 14 10 10 10

Unit mA mA mA mA A A A A mA mA mA mA A A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

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IT6263
148.5MHz(DI)4 WTOTAL_OP Total power consumption under normal operation
3

15 243 376 565

16 286 432 645 656

mA mW mW mW mW

27MHz 74.25MHz 148.5MHz 148.5MHz(DI)

4

547

Notes: 1. Typ: OVDD=TXAVCC33=AVCC=3.3V, IVDD=AVCC18=PVCC1=PVCC2=APVDD=ANVDD=1.8V Max: OVDD=TXAVCC33=AVCC=3.6V, IVDD=AVCC18=PVCC1=PVCC2=APVDD=ANVDD=1.98V 2. PIXELCLK refer to the video clock 3. PIXELCLK=27MHz: 480p with 48kHz/8-channel audio, PIXELCLK=74.25MHz: 1080i with 192kHz/8-channel audio, PIXELCLK=148.5MHz: 1080p with 192kHz/8-channel audio. 4. DI: LVDS Dual Link. 5. PWTOTAL_OP are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items.

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IT6263 Package Dimensions

Figure 5. 64-pin QFN Package Dimensions

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