CECS 201

Digital Logic Design

2008 R. W. Allison

Xilinx ISE Lab #1 Fall 2008

Name ______________________________

General Statement: Implement function F1 = WY(X+Z) + XZ(W+Y) + WX(Y+Z) using two-level NAND logic. Thus, you are to draw the circuit using the Xilinx ISE Schematic Editor, then simulate it using the Xilinx ISE Simulator. You are to get a printout of the Simulation results (i.e. the timing diagram). You must turn in (1) this cover sheet, followed by (2) a printout of the circuit via the Schematic Editor, followed by (3) a printout of the timing diagram via the Xilinx Simulator. You must also implement and download the design into the Spartan FPGA on the Digilent proto-board to verify the correct operation of the circuit. When creating your New Project in the project manager, make sure to select the Spartan 3E family of logic and specify the xc3s500e-fg320 parts (or whatever FPGA part is on your Digilent board) in the New Project dialog box! See pages 4 to 6 on techniques for drawing your schematic with respect to interfacing with the Digilent FPGA development board. After drawing the schematic diagram of your logic, you must click on the Tools Check Schematic option. If there are no errors, you must then save your schematic before going back to the Project Navigator window. Verification of the circuit is done by checking the output(s) (in Xilinx ISE Simulator) for each combination of inputs. For example, what is the output when the inputs (W,X,Y,Z) are 0 0 0 0? Is it correct or not? What is the output when the inputs are 0 0 0 1? Is that correct? You must check all combinations in this manner. It is not uncommon for most of the combinations to be correct, yet a few are incorrect. This means something is wrong with the original design. In that case, you must go back to your K-map(s) and double check your work. If it seems okay, then go back into the Schematic Editor and check your work there, etc. etc. Remember: Design is iterative. Directions for using the Xilinx Simulator are on the CECS 201 Web Site (refer to Xilinx ISE 10.1 Tutorial link on the Learning Links page). To generate the input/output waveform, click on the Simulate Behavioral Model in the ISE Simulator tool box located in the Processes window of Project Navigator. Note that the Xilinx Simulator only runs for 1000 ns (default) but we want to simulate 1700 ns. Thus, you must type in the length of simulation you want (e.g. 1700) and rerun. The output should look similar to what is shown below:

Once your design is verified using the Xilinx simulator, you are to get (1) a printout of the actual circuit from the Schematic Editor and (2) a printout of the simulation waveforms. This is done by selecting the Print option from the File pull-down menu (in both tools). Be sure to print the schematic and the simulation results using landscape mode. You are now ready to "Implement" and "Download" your design into the FPGA. Connect inputs W,X,Y,Z to the far right slide switches SW3, SW2, SW1 and SW0. Connect the output to LED LD0. Due Date: Monday, October 6, 2008
Xilinx ISE Lab # 1 Page 1

{Mon. of week 6}

CECS 201

Digital Logic Design

2008 R. W. Allison

Digilent Nexys 2 Board - Basic I/OPinouts

7-segment displays
L18 J17 H14 G14 D16 D17 G14 D16 F18 J17 H14 D17 G14 D16 L18 F18 J17 H14 D17 G14 L18 F18 J17

50 MHz Clock
B8

L18 F18 H14 D17 D16

F15 (AN3)

C18 (AN2)

H17 (AN1)

F17 (AN0)

Slide Switches

R17 (SW7)

N17 (SW6)

L13 (SW5)

L14 (SW4)

K17 (SW3)

K18 (SW2)

H18 (SW1)

G18 (SW0)

Push Button Switches

H13 (BTN3)

E18 (BTN2)

D18 (BTN1)

B18 (BTN0)

LED's

R4 (LD7)

F4 (LD6)

P15 (LD5)

E17 (LD4)

K14 (LD3)

K15 (LD2)

J15 (LD1)

J14 (LD0)

Xilinx ISE Lab # 1 Page 2

CECS 201

Digital Logic Design

2008 R. W. Allison

Digilab Spartan 3 Board - Basic I/OPinouts

7-segment displays
E14 F13 N16 R16 P15 N15 R16 P15 G13 F13 N16 N15 R16 P15 E14 G13 F13 N16 N15 R16 E14 G13 F13

50MHzClock T9

E14 G13 N16 N15 P15

E13 (A3)

F14 (A2)

G14 (A1)

D14 (A0)

Slide Switches

K13 (SW7)

K14 (SW6)

J13 (SW5)

J14 (SW4)

H13 (SW3)

H14 (SW2)

G12 (SW1)

F12 (SW0)

Push Button Switches

L14 (BTN3)

L13 (BTN2)

M14 (BTN1)

M13 (BTN0)

LED's

P11 (LD7)

P12 (LD6)

N12 (LD5)

P13 (LD4)

N14 (LD3)

L12 (LD2)

P14 (LD1)

K12 (LD0)

Xilinx ISE Lab # 1 Page 3

CECS 201

Digital Logic Design

2008 R. W. Allison

Xilinx ISE Lab # 1 Page 4

CECS 201

Digital Logic Design

2008 R. W. Allison

Xilinx ISE Lab # 1 Page 5

CECS 201

Digital Logic Design

2008 R. W. Allison

Xilinx ISE Lab # 1 Page 6