Leakage Current Monitoring And Comparing In NMOS At Standby Mode

Guided By
Dr.J.Raja Paul Perinbam PhD Professor RMK Engineering College

Submitted By
Tharaneeswaran.T [1054819] II M.E.,[VLSI Design] RMK Engineering College

Overview
2

Introduction

Objective
Literature Survey Implemented System Simulation Results
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Introduction
3

Scaling down the Size of Transistors Improve the

speed of devices, density of chip, lower power dissipation.

To decrease power consumption supply voltage have

to be scaled, which in turn increase sub-threshold leakage current severely affecting power dissipation.
In MOS transistors, current is consumed even in

Off-state or Standby Mode.

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Objective
4

Leakage current is monitored by Setting the

Substrate Bias Voltage to Control the Transistor Threshold Voltage.

Total minimum leakage is found by comparing sub-

threshold current (I ) and band-to-band current (I ).

SUB
BTBT

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Literature Survey
5

Kaushik Roy, et al (2003) reviews various transistor intrinsic leakage

mechanisms. High leakage current in deep-sub micrometer regimes is a significant contributor to power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. The identification of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications.

Cassondra Neau, Kaushik Roy et al (2003) presented a techniques to determine the optimal body bias to minimize leakage current and compensate process variations in scaled CMOS technologies. A circuit trades off subthreshold leakage with band-to-band tunneling leakage at the source/drain junctions to determine the optimal substrate bias for different technology generations and under process variations.

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Literature Survey (cont..)

6

Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park et al (2007)

estimated the total leakage power is critical to designing low-power digital circuits. To improve performance, it is necessary to reduce the threshold voltage (Vth) as well, which results in an exponential increase of sub threshold leakage.

H. Jeon, Y.-B. Kim, and M. Choi et al (2009) proposed a novel approach to minimize leakage current in CMOS circuit during the off-state (or standby mode, sleep mode) by setting the optimal substrate bias voltage to control the transistor threshold voltage. The total minimum leakage current is found by comparing the sub threshold current and band-to-band current .

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Implemented System
7

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Leakage Current Components

8

Total leakage current (IT) is represented as IT = ISUB + IBTBT(DB) + IBTBT(SB) + IGIDL(DB) + IGIDL(SB) + IGB
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Monitoring Circuit
9

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Comparing Circuit
10

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Simulation Results
11

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Simulation Results (cont..)

12

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Conclusion
13

Project work phase I presents a system for leakage

current monitoring and comparing in CMOS Integrated circuits through which the leakage currents are detected and simulated.
The simulated currents are then given to the current

comparator circuit which in turn produces the output voltage in the pulse width manner.
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Future Work
14

The extension of my project is to design the charge pump and the various chip core are analyzed using this implemented system thus to build an optimal body bias system.
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References
15

[1] H. Jeon, Y.-B. Kim, and M. Choi, A novel technique to minimize standby leakage power in nanoscale CMOS VLSI, in Proc. I2MTC, Singapore, May 57, 2009, pp. 13721375. [2] Cassondra Neau and Kaushik Roy, Optimal Body Bias Selection for Leakage Improvement and Process Compensation Over Different Technology Generations, ISLPED03, August 2527, 2003, pp.116-121. [3] Kyung Ki Kim, Yong-Bin Kim, Nohpill Park and Minsu Choi,Leakage Minimization Technique for Nanoscale CMOS VLSI,in IEEE Design & Test of Computers, 2007,pp.322-330. [4] Kaushik Roy, Saibal Mukhopadhyay and Hamid Mahmoodi-meimand, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits,in Proceedings Of The Ieee, Vol. 91, No. 2, February 2003,pp.305-327. [5] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer: Analysis and Design of Analog Integrated Circuits Fourth Edition, Wiley.
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