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Ciclo I-2013 UES-FIA-EIE-AEL115
4) Formar supernodos alrededor de
cada fuente de potencial contenida en
nodos diferentes al de referencia.
Supernodo: Aquel nodo que resulta
al unir los nodos adyacentes donde
estan contenidas las fuentes de
potencial, que tienen terminales
conectadas en nodos diferentes al
nodo de referencia.
Ciclo I-2013 UES-FIA-EIE-AEL115
Expresar cada supernodo en funcin
de las variables de potencial de nodos y
de los parmetros de la respectiva fuente
de potencial.
3 2
La fuente como una ddp:
S
Vs
V v v =
Ciclo I-2013 UES-FIA-EIE-AEL115
5) Aplicar LCK/KCL a cada Supernodo
del circuito.
Se debe tener en cuenta que pudiese existir
mas de un Supernodo simple, doble, etc.
en el ckto
6) Resolver el arreglo matricial para
determinar los potenciales respectivos
asociados a cada nodo.
Continuar con el anlisis de la red, si
es necesario.
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.1 (a) A simple three-
node circuit. (b) Redrawn
circuit to emphasize nodes.
(c) Reference node selected
and voltages assigned. (d)
Shorthand voltage
references. If desired, an
appropriate ground symbol
may be substituted for Ref.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
Copyright 2002 McGraw-Hill. All rights reserved.
Example:
Obtain values for the unknown voltages
across the elements in the circuit below.
1 2
1 2
1 1 2
2 2 1
KCL(LCK) at node (1):
KCL(LCK) at node (2):
7 2 31 (a)
- 6 7 (b)
3.1 0
2 5
( 1.4) 0
1 5
v v v
v v v
v v
v v
=
+ =
+ =
+ + =
( ( (
=
( ( (
=
=
= =
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.5 (a) The circuit of
Example 4.2 with a 22-V
source in place of the 7-O
resistor. (b) Expanded view
of the region defined as a
supernode; KCL requires
that all currents flowing
into the region must sum to
zero, or we would pile up or
run out of electrons.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
Copyright 2002 McGraw-Hill. All rights reserved.
Example (Supernode):
(a) The circuit of Example 4.2 with a 22 V source in place of the 7-O resistor.
(b) Expanded view of the region defined as a supernode; KCL requires that all
currents flowing into the region must sum to zero, or we would pile up or run
out of electrons.
1
3 2
3 2
1 2 1 3
2 2 1 3 3 1
3 2
KCL(LCK) en node ( ):
KCL(LCK) en "Supernode" ( , ) :
De fuente de tensin en "Supernodo" ( , ):
( 8) ( 3) 0
3 4
(
(a)
(b)
(
3) ( 25) 0
1 3 5 4
2 c 2 )
v
v v
v v
v v v v
v v v v v v
v v
+ + =
+ + + + + =
=
Ciclo I-2013 UES-FIA-EIE-AEL115
Reescribiendo (a), (b) y (c) como una matriz, se tiene:
1
2
3
1
2
3
7 4 3 132
35 80 27 1680
0 1 1 22
cuya solucin es:
15
1.071 [V]
14
21
10.5 [V]
2
65
32.5 [V]
2
v
v
v
v
v
v
( ( (
( ( (
=
=
( ( (
( ( (
~
=
=
=
=
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.7
Determine the
node-to-reference
voltages in the circuit
below.
Example: Determine the node-to-reference voltages in
the circuit below.
Ciclo I-2013 UES-FIA-EIE-AEL115
1
2 1
4 1
2 1 2 3
4 1 4 3 2
3 4
Del ckto (ddp):
LCK en nodo 2 :
LCK e
12
n "supernodo" (3 y 4) :
(a)
(b)
(c)
14 0 (d)
0.5 2
0.5 0 (e)
2.5
Del "supernodo" (3
1 2
0.
y 4) :
2 (f)
x
y
x
y
v
v v v
v v v
v v v v
v v v v v
v
v v v
=
=
=
+ =
+ + =
=
Ciclo I-2013 UES-FIA-EIE-AEL115
De ecs. (a) a (f), sustituyendo (b) en (e) y (c) en (f), se tiene:
1
2
3
4
1
2
3
4
Resolviendo la matriz, se obtiene la solucin:
1 0 0 0 12
4 5 1 0 28
1 10 5 14 0
1 0 5 6 0
12 [V]
4 [V]
0 [V]
2 [V]
v
v
v
v
v
v
v
v
( ( (
( ( (
( ( (
=
( ( (
( ( (
=
=
=
=
Ciclo I-2013 UES-FIA-EIE-AEL115
Ejercicio: resolver el arreglo matricial de nodos
Ciclo I-2013 UES-FIA-EIE-AEL115
1.5 d) Mtodo de Anlisis de Mallas:
Objetivo: Determinar las corrientes asociadas
a cada malla, circulando en direcciones y
sentidos pre-establecidos.
Resolviendo un sistema matricial de Orden igual
al nmero de mallas.
Limitante: Mallas solo es vlido para redes
planas.
Con las corrientes de mallas conocidas se continua el
anlisis para determinar otros parmetros de inters
(tensiones, potencias, etc).
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.9 Examples of planar
and nonplanar networks;
crossed wires without a solid
dot are not in physical contact
with each other.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
Copyright 2002 McGraw-Hill. All rights reserved.
Examples of planar (a) and nonplanar networks (b,c);
crossed wires without a solid dot are not in physical
contact with each other.
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.10 (a) The set of branches
identified by the heavy lines is
neither a path nor a loop. (b) The
set of branches here is not a path,
since it can be traversed only by
passing through the central node
twice. (c) This path is a loop but
not a mesh, since it encloses
other loops. (d) This path is also a
loop but not a mesh. (e, f) Each of
these paths is both a loop and a
mesh.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
Copyright 2002 McGraw-Hill. All rights reserved.
(a) The set of branches identified by the heavy lines is neither a path nor a
loop.
(b) The set of branches here is not a path, since it can be traversed only by
passing through the central node twice.
(c) This path is a loop but not a mesh, since it encloses other loops.
(d) This path is also a loop but not a mesh.
(e, f) Each of these paths is both a loop and a mesh.
Ciclo I-2013 UES-FIA-EIE-AEL115
Pasos: Analisis de Mallas:
1) Determinar las mallas formadas en el
circuito y asignar un sentido y direccin
particular a c/u de ellas.
2) Asignar a cada malla sus respectivas
variables de corrientes, por ejo:
I
a
, I
B
, i
x
, i
1
, i
2
,, etc.
(Si las corrientes de mallas no estn previamente
asignadas).
Ciclo I-2013 UES-FIA-EIE-AEL115
3) Aplicar LTK/KVL a cada malla
que no contenga fuentes de
corrientes entre mallas adyacentes.
En los elementos pasivos por
facilidad se suponen cadas de
potencial en el sentido y direccin
del recorrido de la respectiva
corriente de malla en anlisis.
Ciclo I-2013 UES-FIA-EIE-AEL115
The current i
x
-i
y
, defined as flowing
from left to right (i
R
), establishes the
polarity of the voltage across R.
( )
R y R x
i v i R R i = =
Ciclo I-2013 UES-FIA-EIE-AEL115
4) Formar Supermallas que
contengan a fuentes de corrientes entre
mallas adyacentes.
Supermalla:
Aquella trayectoria cerrada resultante
luego de abrir las fuentes de corrientes
respectivas que da origen a la supermalla.
Ciclo I-2013 UES-FIA-EIE-AEL115
Expresar cada Supermalla en funcin
de las corrientes de mallas adyacentes y
de cada fuente de corriente de rama
respectiva.
S
2 1
De la fuente I :
S
I i i =
Ciclo I-2013 UES-FIA-EIE-AEL115
5) Aplicar LTK/KVL a cada Supermalla
del circuito.
Se debe tener en cuenta que pudiese existir
mas de una Supermalla simple, doble, etc.
en el ckto
6) Resolver el arreglo matricial para
determinar las corrientes asociada a
cada malla.
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.12 Determine the
two mesh currents, i
1
and i
2
,
in the circuit below.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
Copyright 2002 McGraw-Hill. All rights reserved.
KVL(LTK) for the left-hand mesh, (i
1
),
-42 + 6 i
1
+ 3 ( i
1
- i
2
) = 0
KVL(LTK) for the right-hand mesh, (i
2
),
3 ( i
2
- i
1
) + 4 i
2
- 10 = 0
Solving, we find that i
1
= 6 A and i
2
= 4 A.
(The current flowing downward through the 3-O resistor is
therefore i
1
- i
2
= 2 A. )
Example: Determine the two mesh currents, i
1
and i
2
, in the
circuit below.
(
=
(
10
42
7 3
3 9
2
1
i
i
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.16
Find the three
mesh currents in the circuit
below.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
Copyright 2002 McGraw-Hill. All rights reserved.
Creating a supermesh from meshes 1 and 3: KVL
-7 + 1 ( i
1
- i
2
) + 3 ( i
3
- i
2
) + 1 i
3
= 0 [a]
KVL(LTK) Around mesh 2:
1 ( i
2
- i
1
) + 2 i
2
+ 3 ( i
2
- i
3
) = 0 [b]
Rearranging [a], [b], [c],
i
1
- 4 i
2
+ 4 i
3
= 7
-i
1
+ 6 i
2
- 3 i
3
= 0
i
1
- i
3
= 7
Solving,
i
1
= 9 A, i
2
= 2.5 A, and i
3
= 2 A.
Finally, we relate the currents in meshes 1 and 3:
i
1
- i
3
= 7 [c]
Example: Find the three mesh currents in the circuit below.
(
(
(
=
(
(
(
(
(
(
7
0
7
1 0 1
3 6 1
4 4 1
3
2
1
i
i
i
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.19
Circuit from
Practice Problem 4.8.
W.H. Hayt, Jr., J.E. Kemmerly, S.M. Durbin, Engineering Circuit Analysis, Sixth Edition.
Copyright 2002 McGraw-Hill. All rights reserved.
Exercise :Find the voltage v
3
in the circuit below.
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.19
Circuit from
Practice Problem 4.8.
Ejo. resuelva los ejercicios anteriores de anlisis de nodos,
aplicando anlisis de mallas y sus variantes.
Ciclo I-2013 UES-FIA-EIE-AEL115
Fig. 4.19
Circuit from
Practice Problem 4.8.
Ejo. resuelva los ejercicios anteriores de anlisis de
mallas, aplicando anlisis de nodos y sus variantes.
Posteriormente para todos los ejercicios, aplique los
mtodos y teoremas alternativos, por ejo. Reducciones,
Transformaciones, Equivalente Thevenin/Norton,
Superposicin, etc. (se debe verificar si el mtodo o
teorema es procedente o aplicable para cada ejercicio)