Institute of of Energy Technology Institute Electronic Systems

Fredrik Bajers Vej 7 A1 9220 Aalborg Denmark http://ies.aau.dk

Faculty of Engineering and Science

Title:

Low cost camera for CubeSats

 a feasibility study

Synopsis:

Theme:

Microcomputer systems

Project period:

E4, spring semester 2006

Project group:
418

Loss Balancing in a Three Level Active Neutral Point Clamped Converter

Group members:

Simon Just Kjeldgaard Pedersen Morten Burchard Tychsen Morten Egelund Jensen Jens Martin Oddershede

Supervisor:

Rasmus Abildgren

Number printed:
7

Number of pages:

Report: 95 Appendicies: 42 Total: 137

Finished:

This project concerns the development of a camera system for taking a picture of Earth from a CubeSat. Based on a market survey, a suitable image sensor complying with the requirements for operation in space is chosen. For testing purposes, a lens is chosen, but a comprehensive market survey should be made to select a lens suitable for operation in space. The functionality of the camera system is analyzed using UML use cases. The use cases obtained are take picture, generate thumbnail, and self test. In order to test the camera system, a test system is constructed, based on the Motorola 68000. The test system runs the TS2MON debugger/monitor and communicates with a PC over a RS232 connection. This forms a platform for designing the interfaces needed for the camera. Hardware and software design of the camera system is modulated by using the use cases and the Rugby metamodel. The hardware and software of the test system works as designed, but it has not been possible to take a picture. It is possible to communicate with the camera, but the resulting data does not resemble a picture. This is possibly due to misconguration of the camera. During software integration, faulty memory reads have occurred, which are believed to be EMC related, due to the long buses. Both of these problems are not investigated further, which should be done before the camera can be used on board a CubeSat.

29th May 2006

- 2010 -

Title: Semester: Semester theme: Project period: ECTS: Supervisor: Project group:

Loss Balancing in a Three Level Active Neutral Point Clamped Converter 8 Control in converter-fed AC drives 15.02.2010 - 26.05.2010 26 Andrzej Adamczyk 840

SYNOPSIS
An unbalanced distribution of the semiconductor power losses amongst the switches of a converter will limit its switching frequency and output power. Hence, for the Neutral Point Clamped (NPC) topology, which is widely used in medium voltage, high power drives, this issue represents a major disadvantage. In order to overcome this drawback, the NPC can be replaced by the Active Neutral Point Clamped (ANPC) topology. This report investigates dierent modulations strategies which can be used for controlling the ANPC converter in order to balance the power losses amongst the semiconductor devices. Several strategies, which use the active neutral point clamping switches are presented and analysed through simulations and experimental tests. The obtained results conrm that by taking advantage of the exibility provided by ANPC topology, a major improvement in the losses distribution can be brought.

Catalin Dincan

Cam Pham

Claudia Georgiana Cojocaru

Marco Guarrera

Copies: Pages: Appendices: Supplements:

2 85 4 1 CD

By signing this document, each member of the group conrms that all participated in the project work and thereby all members are collectively liable for the content of the report.

Title: Semester: Semester theme: Project period: ECTS: Supervisor: Project group:

Jvn fordeling af tab i en three-level ANPC 8 Styring af konverter til at forsyne AC driver 15.02.2010 - 26.05.2010 26 Andrzej Adamczyk 840

SYNOPSIS
En ujvn fordeling af eekt tabene imellem konverterens kontaktorer vil begrnse dens switchs frekvens og udgangseekt. Deraf, for Neutral Point Clamped (NPC) topologi, som er anvendt i stor udstrkning i mellemspnding, hj eekt driver, denne problemstilling er hovedsagelig den vigtigste ulempe. For at kunne lse denne ulempe, NPC kan erstattes med den Aktiv Neutral Point Clamped (ANPC) topologi. Denne rapport undersges hvilken modulation principper som kan bruges til at styre ANPC konverteren med henblik i jvn fordeling af eekt tab imellem halvleder komponenter. Flere principper som bruges af ANPC kontaktorer er fremlagt og analyseret gennem simulering og eksperimenter. De opnet resultater bekrfter, ved at udnytte eksibilitet givet af ANPC topologi, forbedring af tabene fordeling kan hentes.

Catalin Dincan

Cam Pham

Claudia Georgiana Cojocaru

Marco Guarrera

Oplag: Antal sider: Appendiks: Bilag:

2 85 4 1 CD

Ved at underskrive dette dokument bekrfter hvert enkelt gruppemedlem, at alle har deltaget ligeligt i projektarbejdet og at alle er kollektivt ansvarlige for rapportens indhold.

Preface
This report represents the documentation of the project entitled Loss Balancing in a Three Level Active Neutral Point Clamped Converter. The project was prepared between the 15th of February and the 26th of May 2010, at Aalborg University Institute of Energy Technology, by the 8th semester group 840. The aim of the project was to study dierent modulation strategies for a three level Active Neutral Point Clamped (ANPC) inverter, in order to ensure loss equalization amongst the semiconductor switches. The report is structured into ve chapters. The rst chapter gives a brief presentation of the background an motivation for this project, setting the main objectives and limitations. Chapter two provides information about the theoretical concepts which are used throughout the report. In chapter three, Matlab Simulink simulations are performed in order to study how the ANPC inverter behaves for dierent modulation strategies, from the point of view of losses distribution amongst the switches. In chapter four experimental are performed in order verify if loss balancing is achieved. The nal chapter presents the conclusions of the report and future work. The literature references are shown in square brackets by numbers. The list of the references is presented in the chapter Bibliography. Appendices are assigned with letters, and arranged in alphabetical order at the end of the report. Figures and tables are numbered in the following format: Figure Chapter.Number and Table Chapter.Number. The contents of the enclosed CD are listed in Appendix D.

26th of May 2010

Contents
1 Introduction 1.1 1.2 17

Background and motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.2.1 1.2.2 Project objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Project limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19

2 Basics on converter losses and the ANPC topology 2.1

IGBT and diode power losses . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1.1 2.1.2 2.1.3 IGBT conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . 19 IGBT switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Diode losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 . . . . . . . . . . . . . . . . . 21

2.2

The Active Neutral Point Clamped topology 2.2.1 2.2.2 2.2.3

Basics on three level converters . . . . . . . . . . . . . . . . . . . . . 21 ANPC topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Modulation strategies . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.3

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 37

3 Simulations 3.1 3.2

System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Simulation results 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

PWM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PWM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PWM-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PWM-DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PWM-ALD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Results for validation in the laboratory . . . . . . . . . . . . . . . . 44

3.3

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4 Laboratory implementation 4.1

49

Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.1.1 4.1.2 4.1.3 ANPC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DSP board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Interface board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 4.3

Modulation implementation on the DSP . . . . . . . . . . . . . . . . . . . . 52 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3.1 4.3.2 R load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 RL load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.4

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 65

5 Conclusions 5.1 5.2

Review of the main tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 69 71 77 79 81

Bibliography A Heat sink selection B Extension interface board C List of used laboratory instruments D Contents of the enclosed CD

List of Figures
1.1 2.1 2.2 2.3 2.4 Single-phase three-level NPC (a) and ANPC (b) voltage source converters . 17 Single-phase two-level half bridge (HB) (a) and three-level Neutral Point Clamped (NPC) (b) voltage source converters . . . . . . . . . . . . . . . . . 21 Switching states for the single-phase three-level NPC converter: (a) P - S1 and S3 are on; (b) N - S4 and S6 are on; (c) O - S3 and S4 are on . . . . . 22 Single-phase ANPC voltage source converter . . . . . . . . . . . . . . . . . . 23 Switching states for the single-phase three-level ANPC converter: (a) P S1 and S3 are on; (b) N - S4 and S6 are on; (c) OU - S2 and S3 are on; (b) OD - S4 and S5 are on; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PWM generation for the PWM-NPC strategy . . . . . . . . . . . . . . . . . 26 The switching sequences and output voltage for the PWM-NPC strategy. Because the frequency of the carrier waves is much higher than that of the reference signal, during one period of the carrier wave, the reference can be considered to be constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 The switching sequences and output voltage for the 3L-ANPC PWM-1 strategy. Because the frequency of the carrier waves is much higher than that of the reference signal, during one period of the carrier wave, the reference can be considered to be constant. . . . . . . . . . . . . . . . . . . . . 27 The switching sequences and output voltage for the 3L-ANPC PWM-2 strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PWM generation for the PWM-3 strategy . . . . . . . . . . . . . . . . . . . 29

2.5 2.6

2.7

2.8 2.9

2.10 Switching signals for the ANPC inverter switches with PWM-3 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.11 PWM generation for the PWM-DF strategy . . . . . . . . . . . . . . . . . . 31 2.12 The switching sequences and output voltage for the 3L-ANPC PWM-DF strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.13 PWM generation for PWM-ALD modulation strategy for 50%-50% Stress In/Stress Out ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.14 The switching sequences and output voltage for the 3L-ANPC PWM-ALD strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1 3.2 The general block diagram of the simulation models . . . . . . . . . . . . . 37 The PLECS block diagram of the plant . . . . . . . . . . . . . . . . . . . . 38 7

3.3 3.4 3.5 3.6 3.7 3.8

The Simulink block diagram of the losses calculation block . . . . . . . . . . 39 Power losses distribution for PWM-1 modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power losses distribution for PWM-2 modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power losses distribution for PWM-3 modulation strategy with a 50%-50% PWM-1/PWM-2 ratio and a 10 kW load (PF = 1) . . . . . . . . . . . . . . 42 Power losses distribution for PWM-DF modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Power losses distribution for PWM-ALD modulation strategy with a 50%50% Stress In/Stress Out ratio and a 10 kW RL load (PF = 0,85) . . . . . 44 Block diagram of the experimental test setup . . . . . . . . . . . . . . . . . 49 Laboratory test setup: (1)- 300 V, 5 A DC power supply; (2)- 24 V, 3 A DC power supply; (3)- single-phase ANPC converter; (4)- load resistor; (5)load inductor; (6)- thermal camera; (7)- single-phase power analyser; (8)TMS320F28335 eZdsp board; (9)- interface board; (10)- oscilloscope; (11)PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Simulink model used for DSP implementation . . . . . . . . . . . . . . . . . 52 Thermal picture of the ANPC inverter with R load for PWM-1 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Thermal picture of the ANPC inverter with R load for PWM-2 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Thermal picture of the ANPC inverter with R load for PWM-3 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Thermal picture of the ANPC inverter with R load for PWM-DF modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Thermal picture of the ANPC inverter with R load for PWM-ALD modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Thermal picture of the ANPC inverter with RL load for PWM-1 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.1 4.2

4.3 4.4 4.5 4.6 4.7 4.8 4.9

4.10 Thermal picture of the ANPC inverter with RL load for PWM-2 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.11 Thermal picture of the ANPC inverter with RL load for PWM-3 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.12 Thermal picture of the ANPC inverter with RL load for PWM-DF modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.13 Thermal picture of the ANPC inverter with RL load for PWM-ALD modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.14 The waveform of the output voltage (measured on the resistor) for RL load (PF =0,85) with PWM-1 modulation strategy . . . . . . . . . . . . . . . . . 62 4.15 The waveform of the output voltage (measured on the resistor) for RL load (PF =0,85) with PWM-2 modulation strategy . . . . . . . . . . . . . . . . . 62 8

4.16 The waveform of the output voltage (measured on the resistor) for RL load (PF =0,85) with PWM-3 modulation strategy . . . . . . . . . . . . . . . . . 63 A.1 Typical switching losses versus the collector-to-emitter current . . . . . . . 72 A.2 Device and heat sink physical model . . . . . . . . . . . . . . . . . . . . . . 73 A.3 Equivalent electrical model for a semiconductor device, where: Q - heat source which has a current source as an electrical correspondent [W]; Tj junction temperature [o C ]; Tc - temperature of the case [o C ]; Th - temperature of the heat sink [o C ]; Ta - ambient temperature [o C ]; Rjc - junctionto-case resistance [o C/W ]; Rch - case-to-heat sink resistance [o C/W ]; Rha is heat sink-to-ambient resistance [o C/W ] . . . . . . . . . . . . . . . . . . . 73 A.4 Matlab Simulink simulation model for heat sink calculation . . . . . . . . . 75 A.5 Matlab Simulink simulation model for heat sink calculation - subsystem . . 76 B.1 The circuit diagram of the extension interface board . . . . . . . . . . . . . 77 B.2 The PCB layout of the extension interface board . . . . . . . . . . . . . . . 78

List of Tables
2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Possible switching states used for the NPC converter . . . . . . . . . . . . . 22 Possible switching states used for the ANPC converter . . . . . . . . . . . . 23 Switching sequences for the PWM-NPC strategy . . . . . . . . . . . . . . . 25 Switching sequences for the PWM-1 strategy . . . . . . . . . . . . . . . . . 27 Switching sequences for the PWM-2 strategy . . . . . . . . . . . . . . . . . 28 Switching sequences for the PWM-DF strategy . . . . . . . . . . . . . . . . 32 Switching sequences for the 3L-ANPC PWM-ALD strategy . . . . . . . . . 33 Simulation results for PWM-1 modulation strategy with a 10 kW R load . . 39 Simulation results for PWM-2 modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Simulation results for PWM-3 modulation strategy with a 50%-50% PWM1/PWM-2 ratio and a 10 kW load (PF = 1) . . . . . . . . . . . . . . . . . . 42 Simulation results for PWM-DF modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Simulation results for PWM-ALD modulation strategy with a 50%-50% Stress In/Stress Out ratio and a 10 kW load (PF = 1) . . . . . . . . . . . . 44 Simulation results for PWM-1 modulation strategy . . . . . . . . . . . . . . 45 Simulation results for PWM-2 modulation strategy . . . . . . . . . . . . . . 45 Simulation results for PWM-3 modulation strategy . . . . . . . . . . . . . . 45 Simulation results for PWM-DF modulation strategy . . . . . . . . . . . . . 46

3.10 Simulation results for PWM-ALD modulation strategy . . . . . . . . . . . . 46 4.1 4.2 4.3 Simulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 The temperatures [o C ] of the switching devices obtained for the RL load . . 61 The temperatures [o C ] of the switching devices obtained for the R load . . 64

A.1 Total power losses of the semiconductor devices . . . . . . . . . . . . . . . . 72 C.1 Laboratory instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11

12

List of Acronyms

2L - two-level 3L - three-level ALD - adjustable losses distribution ANPC - active neutral point clamped APOD - alternative phase opposition disposition DF - double frequency DSP - digital signal processor FC - ying capacitor HB - half bridge IGBT - insulated gate bipolar transistor MV - medium voltage NPC - neutral point clamped PD - phase disposition PF - power factor POD - phase opposition disposition PWM - pulse width modulation R - resistive RL - resistive inductive S - switch SC - stacked cells VSC - voltage source converter VSI - voltage source inverter

13

Nomenclature list
dv dt

- voltage variation in time

fsw - frequency of the carrier waves Ts - switching time period for the reference wave vCE - IGBT collector-emitter voltage vCE 0 - IGBT collector-emitter voltage at zero current vD0 - diode forward voltage at zero current vD - diode forward voltage gf e - IGBT transconductance iph - phase current iC - IGBT collector current ICav - average value of the IGBT collector current ICrms - rms value of the IGBT collector current iD - diode forward current IDav - average forward current of the diode IDrms - diode rms forward current is - instantaneous current M - modulation index O - zero switching state OD - zero down switching state OU - zero up switching state P - positive switching state P N - negative switching state Pcond - conduction losses Ploss - total losses Psw - switching losses Pb - blocking (leakage) losses rC - IGBT collector-emitter on resistance 15

rD - diode forward resistance Sc1 , Sc2 - carrier waves Sr , Sr - reference signals Tsw - switching time period for the carrier wave vs - instantaneous voltage VAO - phase voltage Vdc - DC link voltage

16

Chapter 1

Introduction
In this chapter, a short introduction on the background and motivation of this project is given. The problem of the project is formulated. The goals and limitations are also stated.

1.1

Background and motivation

The three-level (3L) Active Neutral Point Clamped (ANPC) topology was proposed in 2001 [1], as an improved version of the Neutral Point Clamped (NPC) topology, which dates back in the early 1980s. The NPC oered a simple solution for extending the the voltage and power ranges of the existing two-level voltage source converter (VSC) technology and a superior output voltage quality [2]. Today, the NPC converter is widely used in medium voltage (MV) drives for industry, marine, mining and traction applications [3]. A very important drawback of the NPC topology is that the semiconductor losses are distributed unequally among the devices of the converter, which will also lead to an unequal junction temperature distribution [3]. Hence, some of the devices will become hotter, while others will stay cooler. As in every converter, the losses in the most stressed device will limit the switching frequency and the output power.

S1 ___ V dc 2 D2

D1 ___ V dc 2 S3 D3 iph

S1

D1 D2 S3 D5 S4 D3 iph

S2

D5 ___ dc V 2 S6

S4

D4 ___ dc V 2

S5

D4

D6

S6

D6

(a) 3L NPC-VSC

(b) 3L ANPC-VSC

Figure 1.1: Single-phase three-level NPC (a) and ANPC (b) voltage source converters In order to overcome the uneven loss distribution issue, the clamping diodes of the NPCVSC (see Figure 1.1(a)) have been replaced by active switches with anti-parallel diodes, 17

in the ANPC converter (see Figure 1.1(b)). This way, the additional switches will enable more switching states and commutations compared to the NPC topology. Due to the increased number of possible switching states and commutations which can be achieved with the ANPC topology compared to the NPC structure, numerous modulation strategies can be implemented for controlling the ANPC inverter. Hence, by using the proper modulation technique, loss balancing amongst the semiconductor devices could be achieved. Due to the fact that the most stressed device will limit the current capability of the converter, power loss balancing amongst the switches of the converter is desired. This way, the transferred power and switching frequency of the converter can be increased, without having to increase the costs by replacing the switches with higher rated ones or bringing improvements to the cooling system.

1.2

Problem formulation

The aim of this report is to investigate the modulation strategies for the three level Active Neutral Point Clamped (ANPC) voltage source inverter in order to achieve an even distribution of the power losses amongst the inverters semiconductor switches.

1.2.1

Project objectives

The main goals of this project are: to achieve knowledge about the the existing modulation strategies used for the ANPC converter; to investigate the distribution of the power losses amongst the ANPC switches for dierent modulation strategies through simulations; experimental validation of the simulation results.

1.2.2

Project limitations

Due to time constraint, not all the aspects of the considered problem have been covered. The main limitations of this project are: a low voltage ANPC converter will be used in the laboratory implementation; only the inverter mode of operation of the converter will be studied; only single phase operation is considered; the inverter used in the experiments was not built for the purpose of studying loss balancing; the modulation strategies are going to be tested only on an R and RL load.

18

Chapter 2

Basics on converter losses and the ANPC topology

This chapter introduces the main theoretical concepts which are used throughout the report. At the beginning, basic notions about Insulated Gate Bipolar Transistors (IGBT) and diode power losses are briey presented. Afterwards, the three-level converter concept is introduced. The Active Neutral Point Clamped (ANPC) topology is then described, as an improvement to the basic Neutral Point Clamped (NPC) structure. Several modulation strategies used for controlling the ANPC converter are presented, with focus on how the power losses are distributed amongst the switches.

2.1

IGBT and diode power losses

IGBT and diode power losses, as well as power losses in any semiconductor component operating in switch-mode can de divided in three main groups [4]: conduction losses (Pcond ); switching losses (Psw ); blocking (leakage) losses (Pb ), which are generally neglected. Therefore, the total losses in a semiconductor device (Ploss ) are given by Equation 2.1 [4]. Ploss = Pcond + Psw + Pb Pcond + Psw [W ] (2.1)

2.1.1

IGBT conduction losses

If the energy associated with the small amount of leakage current during the o-state of the switch is neglected, the conduction losses are represented by the energy lost in the switch during the on-state. This type of losses depend on the voltage across the switch and the current through it. IGBT conduction losses can be calculated by approximating the semiconductor device with a DC voltage source, representing the IGBT on-state zero-current collector-emitter voltage (vCE 0 ) connected in series with a resistance representing the the collector-emitter on-state resistance (rc ) [4]: vCE (iC ) = vCE 0 + rC iC 19 [V ] (2.2)

where vCE is the collector-emitter voltage and iC is the current through the IGBT, during on-state. The average conduction losses of the IGBT can be computed as [4]: Pcond = Pcond = 1 Tsw
Tsw 0

1 Tsw

Tsw

(vCE iC (t))dt
0

[W ]

(2.3)

2 (vCE 0 iC (t) + rC iC (t)2 )dt = vCE 0 ICav + rC IC rms

[W ]

1 is the switching period, ICav is the average where fsw is the switching frequency, Tsw = fsw current and ICrms is the rms value of the current through the IGBT.

2.1.2

IGBT switching losses

The IGBT switching losses represent the energy losses which occur during the switching transient, as the operating state of the switch is changed from on (o) to o (on). The switching losses depend on the voltage across the switch, the current through it and the switching time, and based on the instantaneous waveforms of the voltage and current, can be expressed as [4]:
t1 +tswon

Psw = fsw
t1

is vs dt +

t2 +tswo t2

is vs dt

[W ]

(2.4)

where fsw is the switching frequency, t1 represents the moment when the IGBT starts to turn on, t2 represents the time moment when the switch starts to turn o, tswon and represents the time needed for the switch to turn on, tswo represents the time needed for the switch to turn o, is is the instantaneous current through the IGBT and vs is the instantaneous voltage across the switch.

2.1.3

Diode losses

Similar to the IGBT, the diode has both conduction and switching losses. Diode switching losses are generally small, and can therefore be neglected. The conduction losses can be calculated by approximating the semiconductor device with a DC voltage source, representing the forward voltage drop at zero current (vD0 ) connected in series with a resistance representing the forward resistance of the diode (rD ) [4]: vD (iD ) = vD0 + rD iD [V ] (2.5)

where vD is the voltage across the diode and iD is the current through the diode, during on-state. The average conduction losses of the diode can be computed as [4]: Pcond = Pcond = 1 Tsw
Tsw 0

1 Tsw

Tsw

(vD iD (t))dt
0

[W ]

(2.6)

2 (vD0 iD (t) + rD iD (t)2 )dt = vD0 IDav + rD ID rms

[W ]

1 is the switching period, IDav is the average where fsw is the switching frequency, Tsw = fsw current and IDrms is the rms value of the current through the diode.

20

2.2
2.2.1

The Active Neutral Point Clamped topology

Basics on three level converters

Three-level (3L) converters are relatively new, and they have been developed as an improvement to the existing two-level (2L) topologies. Nowadays, due to the advance in technology, this type of converters are successfully used in high power, medium voltage, fast switching applications [1]. A standard single-phase two-level inverter is composed of two complementary switches, and can be seen in Figure 2.1(a). The output voltage obtained with this topology is a d square wave whose amplitude swings between + V2d and V 2 , hence the name of two-level. With this topology, each of the switching device has to withstand full DC link voltage. Other disadvantages of the two-level converters are high harmonic distortion and high dv dt [5].

S1
S1 Vdc D1 iph

D1 D2 S3

___ V dc 2 D3 iph D5 S4 D4

S2

D2

___ dc V 2 S6 D6

(a) 2L HB converter

(b) 3L NPC converter

Figure 2.1: Single-phase two-level half bridge (HB) (a) and three-level Neutral Point Clamped (NPC) (b) voltage source converters In order reduce the problems of the classical two-level inverters, multilevel topologies can be used instead. The three main multilevel inverter topologies are Stacked Cells (SC), Flying Capacitor (FC) and Neutral Point Clamped (NPC), where NPC has found wide application in high power medium voltage drives [5]. With an appropriate switching strategy, the multilevel topologies can reduce the dv dt and if the number of levels is suciently high, harmonic distortion will be small enough that output lter can be omitted [6]. A single-phase three-level NPC converter is presented in Figure 2.1(b). Compared with the two-level topology, shown in Figure 2.1(a), two extra switches with anti-parallel diode are added and so, an additional zero level is introduced in the waveform of the output voltage, hence the name of three-level converter. The NPC inverter, as well as all any three-level topology, can take one of the following three switching states [5]: Positive (P) - when the two upper switches S1 and S3 are turned on, + V2d is applied to the output (see Figure 2.2(a)); Negative (N) - when the two lower switches S4 and S6 are turned on, V2d is applied to the output (see Figure 2.2(b)); 21

 Zero (O) - when the two inner switches S3 and S4 are turned on, the output is connected to the neutral point of the converter through one of the clamping diodes ( D2 or D5 ), depending on the direction of the load current: if iph is positive, the current will ow through D2 , and if iph is negative, the current will ow through D5 (see Figure 2.2(c)).

S1 ___ V dc 2 D2

D1 ___ V dc 2 S3 D3 iph

S1

D1 D2 S3

D3 iph

D5 ___ dc V 2 S6

S4

D4 ___ dc V 2

D5

S4

D4

D6

S6

D6

(a) Positive switching state (P)

(b) Negative switching state (N)

S1 ___ V dc 2 D2

D1 S3

D3 iph

D5 ___ dc V 2 S6

S4

D4

D6

(c) Zero switching state (O)

Figure 2.2: Switching states for the single-phase three-level NPC converter: (a) P - S1 and S3 are on; (b) N - S4 and S6 are on; (c) O - S3 and S4 are on The switching states which can be used for the NPC topology are summarized in Table 2.1. Switching state P 0 N Device state S1 S3 S4 S6 On O O On On O O On On O O On Inverter terminal voltage
dc + V2 0 dc V2

Table 2.1: Possible switching states used for the NPC converter An advantage of the 3L NPC converter is that each of the switches will have to withstand only half of the DC link voltage, and so they can be used for applications which require high power transfer. The drawback of this topology is represented by the unequal distribution of the power losses among the semiconductor devices, which will yield an unequal junction 22

temperature distribution. The most thermally stressed device will limit the switching frequency and the output power transfer of the converter [3].

2.2.2

ANPC topology

The Active Neutral point Clamped (ANPC) topology was developed in order to overcome the uneven loss distribution issue of the NPC converter [1]. In order to achieve this, the clamping diodes of the NPC-VSC (see Figure 2.1(b)) have been replaced by active switches with anti-parallel diodes, in the ANPC converter (see Figure 2.3). This way, the additional switches will enable more switching states and commutations compared to the NPC topology.

S1 ___ V dc 2 S2

D1 D2 S3 D5 S4 D3 iph

S5 ___ dc V 2

D4

S6

D6

Figure 2.3: Single-phase ANPC voltage source converter With the ANPC converter, the same switching states can be achieved as with the NPC topology. The additional active switches in the ANPC converter will introduce more possible switching states (see Table 2.2), meaning that with this topology, the same output state can be obtained with more than one switching state. For the positive and negative switching states, the paths of the current through the switches remain the same as for the NPC topology. In the case of the zero switching state, the active clamping devices allow the selection of dierent current paths, independent from the direction of the load current [7]. Switching state P1 P2 OU 1 OU 2 OD1 OD2 N1 N2 S1 On On O O On O On O S2 O O On On O On O On Device S3 On On On On O O O O state S4 O O O O On On On On Inverter terminal voltage S5 O On O On On On O O S6 On O On O O O On On
dc + V2 V dc + 2 0 0 0 0 V dc 2 dc V2

Table 2.2: Possible switching states used for the ANPC converter

23

The switching states which can be used for the ANPC topology are presented in Figure 2.4.

S1 ___ V dc 2 S2

D1 D2 S3 D3 iph
___ V dc 2

S1

D1 D2 S3 D5 S4 D3 iph

S2

S5 ___ dc V 2

D5 S4

D4
___ dc V 2

S5

D4

S6

D6

S6

D6

(a) Positive switching state (P)

(b) Negative switching state (N)

S1 ___ V dc 2 S2

D1 ___ V dc 2 D2 S3 D3 iph

S1

D1

S2

D2 S3

D3 iph

S5 ___ dc V 2

D5 S4

D4 ___ dc V 2

S5

D5 S4

D4

S6

D6

S6

D6

(c) Zero (up) switching state (OU )

(d) Zero (down) switching state (OD )

Figure 2.4: Switching states for the single-phase three-level ANPC converter: (a) P - S1 and S3 are on; (b) N - S4 and S6 are on; (c) OU - S2 and S3 are on; (b) OD - S4 and S5 are on; The additional switching states of the ANPC topology will allow an improvement in what concerns the uneven distribution of the losses amongst the semiconductor devices, compared to the NPC converter. This can be achieved by using an appropriate switching sequence which can redistribute the power loses of the switches in a way that loss balancing is achieved. Hence, the lifetime of the inverter can be extended, its current capability, or the switching frequency can be increased, without changing the switching devices for higher rated ones, neither improve the cooling system [7].

2.2.3

Modulation strategies

The main function of a voltage source inverter (VSI) is to convert a xed DC voltage to an AC voltage with variable magnitude and frequency. This can be achieved by applying a specic modulation strategy, and hence control the switching sequence of the inverters switches [5]. There are various control techniques that have been proposed for the multilevel inverters. In general, they can be classied into two main categories [8]: carrier-based methods; 24

 space vector modulation methods. In this report, only carries based modulation strategies are going to be presented. In the case of carrier-based strategies, the switching states for the switches of a n-level inverter are obtained by comparing n-1 triangular carrier waves having the same frequency and amplitude, with a sinusoidal reference, centred in the middle of the carrier set [9]. Depending on the phase relationship between the carriers, there are three common carrierbased strategies [9]: alternative phase opposition disposition (APOD), where each carrier is phase shifted by 180o from its adjacent carriers; phase opposition disposition (POD), where the carriers above the reference zero point are out of phase with those below the zero point by 180o ; phase disposition (PD), where all carriers are in phase. For three-level inverters, the APOD and POD strategies are equivalent [9]. The three-level ANPC inverter is derived from the NPC topology, where the clamping diodes are replaced by two active switches with anti-parallel diodes (see Figure 1.1). This way, in contrast to the conventional NPC topology, the ANPC converter oers more than one possibility of clamping the midpoint [10]. Compared to the classical NPC structure, the ANPC topology has more degrees of freedom, i.e. more zero conduction paths can be achieved. By using dierent zero states and conduction paths, various PWM modulation strategies can be obtained for the ANPC topology. Due to the fact that the commutations to or from the zero states determine the distribution of the switching losses and that the distribution of conduction losses during the zero states can be controlled by the selection of dierent current paths, a more even distribution of the losses in the semiconductor devices can be achieved with the ANPC topology [10]. NPC modulation strategy The control strategy of the NPC converter can also be used on the ANPC topology. In this case, the two additional active switches of the ANPC converter are not used. Figures 2.5 and 2.6 (on the next page) present how the switching signals are obtained for the PWM-NPC strategy, by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ). Through the comparison process, three switching states are obtained: P (Vdc /2), N (Vdc /2) and O (see table 2.3).

Output Voltage
dc + V2 0 dc V2

Switching State P O N

Switching Sequence S1 S3 S4 S6 1 1 0 0 0 1 1 0 0 0 1 1

Table 2.3: Switching sequences for the PWM-NPC strategy

25

1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 Sc1 Sc2 Sr

0.002 0.004 0.006 0.008

0.01

0.012 0.014 0.016 0.018

0.02

Time[s]

Figure 2.5: PWM generation for the PWM-NPC strategy

Vdc/2 Sr

Sc1

0 O N Sc2 0 Ts O

O 0 0

O Ts

Sr -Vdc/2

S1 S3 S4 S6

S1 S3 S4 S6

VAO

Vdc/2 (a)

VAO

Vdc/2 (b)

Figure 2.6: The switching sequences and output voltage for the PWM-NPC strategy. Because the frequency of the carrier waves is much higher than that of the reference signal, during one period of the carrier wave, the reference can be considered to be constant. In order to obtain the P state, the switches S1 and S3 must be turned on. The N state is obtained by turning on the switches S4 and S6 . The zero voltage level is obtained when the switches S3 and S4 are turned on [11].

26

Classical PWM strategies For the ANPC topology there are two well known classical carrier-based PWM modulation strategies, called PWM-1 and PWM-2. In the case of PWM-1 strategy, the switches S1 , S2 and S5 , S6 switch alternatively at a high frequency (fsw /2), while S3 and S4 switch at a low frequency, equal to the frequency of the reference voltage [12]. Figures 2.5 (on the previous page) and 2.7 present how the switching signals are obtained for the PWM-1 strategy, by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ). Through the comparison process, four switching states are obtained: P (Vdc /2), N (Vdc /2), O1+ and O1 (see Table 2.4).
Vdc/2 Sr Sr Ts -Vdc/2 S1 S2 S3 S4 S5 S6 Vdc/2 (a) VAO Vdc/2 (b) 0 0 O1O1+ 0 S1 S2 S3 S4 S5 S6 VAO 0 P O1+ N Sc2 Ts O1-

Sc1

Figure 2.7: The switching sequences and output voltage for the 3L-ANPC PWM-1 strategy. Because the frequency of the carrier waves is much higher than that of the reference signal, during one period of the carrier wave, the reference can be considered to be constant.

Output Voltage
dc + V2

Switching State P O1 + O1 N S1 1 0 0 0

0
dc V2

Switching S2 S3 0 1 1 1 0 0 0 0

Sequence S4 S5 0 0 0 0 1 1 1 0

S6 0 0 0 1

Table 2.4: Switching sequences for the PWM-1 strategy In order to obtain the P state, the switches S1 and S3 must be turned on. The N state is obtained by turning on the switches S4 and S6 . For these two commutation sequences, the paths of the load current through the switches are the same as for the NPC topology. The zero voltage level is obtained with two switching states: O1 and O1+ . The state O1 is obtained when the reference voltage is negative. In this case, S4 and S5 must be 27

turned on, while S1 , S2 , S3 and S6 must be turned o. The state O1+ is obtained when the reference voltage is positive. In this case, S2 and S3 must be turned on, while S1 , S4 , S5 and S6 must be turned o [12]. With the PWM-1 strategy, the inner switches of the inverter (S3 and S4 ) have only conduction losses, while the switching losses mainly stress the outer IGBTs (S1 and S6 ) [10].

In the case of PWM-2 strategy, the switches S3 and S4 switch at a high frequency, while the rest of the switches switch at a low frequency(the frequency of the reference voltage) [12]. Figures 2.5 (on page 25) and 2.8 present how the switching signals are obtained for the PWM-2 strategy, by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ). Through the comparison process, four switching states are obtained: P (Vdc /2), N (Vdc /2), O2+ and O2 (see table 2.5).
Vdc/2 Sr O2O2+ 0 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (a) 0 P O2+ Ts Sr -Vdc/2 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (b) 0 N Sc2 O2Sc1 0

Ts

Figure 2.8: The switching sequences and output voltage for the 3L-ANPC PWM-2 strategy

Output Voltage
dc + V2

Switching State P O2 + O2 N S1 1 1 0 0

0
dc V2

Switching S2 S3 0 1 0 0 1 1 1 0

Sequence S4 S5 0 1 1 1 0 0 1 0

S6 0 0 1 1

Table 2.5: Switching sequences for the PWM-2 strategy In order to obtain the P state, the switches S1 , S3 and S5 must be turned on. The state N is obtained by turning on the switches S2 , S4 and S6 . In the case of these two commutation sequences, the paths of the load current through the switches are the same as for the ANPC PWM-1 strategy. The zero voltage level is obtained with two switching states: O2 and O2+ . The state O2 is obtained when the reference voltage is negative. In this case, S2 , S3 and S6 must be turned on, while S1 , S4 and S5 must be turned o. 28

The state O2+ is obtained when the reference voltage is positive. S1 , S4 and S5 must be turned on and S2 ,S3 and S6 must be turned o. For O2 and O2+ states, the load current can pass in both directions through S2 and S3 or through S5 and S4 [12]. With the PWM-2 modulation strategy, the transistors S3 and S4 switch during the entire cycle, and so they are the most stressed semiconductor devices in the inverter.

The disadvantage of the PWM-1 and PWM-2 methods is given by an unequal distribution of the losses in the semiconductor devices, which leads to an unequal distribution of junction temperatures and so, to a limitation in the output power of the ANPC inverter. Hence, by using the two classical PWM modulation strategies, the main drawback of the conventional NPC topology is not overcome by the ANPC structure. Classical strategies combined By combining the two classical modulation strategies, a new strategy was obtained, and named PWM-3. Figure 2.9 shows the reference and carrier signals which are used for obtaining the switching sequences for the switches with PWM-3 modulation strategy.
PWM-1
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 Sc1 Sc2 Sr

PWM-2

PWM-1

Time[s]

Figure 2.9: PWM generation for the PWM-3 strategy The switching states for the PWM-3 modulation strategy are obtained by applying for 50% of the period of the reference signal Sr , the switching sequences of PWM-1 strategy (see Figure 2.7 on page 27), and for the rest of the period, the switching sequences of PWM-2 strategy (see Figure 2.8 on page 28). For the rst 25% of the positive cycle of the reference signal, the switches are controlled with PWM-1. For a resistive load, this means that the inner switches have only conduction losses and the switching losses mainly stress the outer IGBTs. For the rest of the positive cycle and the rst 25% of the negative cycle PWM-2 strategy is applied. Therefore, the switching losses stress the inner switches, while the outer have only conduction losses. For the remaining 25% of the negative cycle, PWM-1 strategy is applied again. 29

By using this PWM modulation strategy, the switching losses can be equally distributed amongst the inner and outer switches, in order to balance the overall power losses. The switching signals for the six switches with the PWM-3 strategy can be seen in Figure 2.10.
15 10

S1
5 0 0

0.002 0.004 0.006 0.008

0.01 0.012 0.014 0.016 0.018 Time [s]

0.02

15 10

S2
5 0 0
15 10

0.002 0.004 0.006 0.008

0.01 Time [s]

0.012 0.014 0.016 0.018

0.02

S3
5 0 0

0.002 0.004 0.006 0.008

0.01 0.012 0.014 0.016 0.018 Time [s]

0.02

15 10

S4
5 0 0 15 10 5 0 0

0.002 0.004 0.006 0.008

0.01 0.012 0.014 0.016 0.018 Time [s]

0.02

S5

0.002 0.004 0.006 0.008

0.01 0.012 0.014 0.016 0.018 Time [s]

0.02

15 10

S6
5 0 0

0.002 0.004 0.006 0.008

0.01 0.012 0.014 0.016 0.018 Time [s]

0.02

Figure 2.10: Switching signals for the ANPC inverter switches with PWM-3 modulation strategy

30

Double frequency PWM strategy Figures 2.11 and 2.12 present how the switching signals are obtained for the PWM-DF strategy [12], by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ). Through the comparison process, six switching states are obtained: P (Vdc /2), N (Vdc /2), O1+ , O2+ , O2 , O1 (see table 2.6 on the next page).
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 Sr Sc1 Sc2

Time[s]

Figure 2.11: PWM generation for the PWM-DF strategy

Vdc/2 Sr 0 O1+ P O2+ Sc1 -Vdc/2 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (a) 0 Ts P O1+

Vdc/2 Sc2 0 Sr -Vdc/2 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (b) O1N 0 O2N Ts O1-

Figure 2.12: The switching sequences and output voltage for the 3L-ANPC PWM-DF strategy

31

Output Voltage
dc + V2

Switching State P O1+ O2+ O2 O1 N S1 1 0 1 0 0 0

dc V2

Switching S2 S3 0 1 1 1 0 0 1 1 0 0 1 0

Sequence S4 S5 0 1 0 0 1 1 0 0 1 1 1 0

S6 0 0 0 1 0 1

Table 2.6: Switching sequences for the PWM-DF strategy In order to obtain the switching state P , the switches S1 , S3 and S5 must be turned on, while the state N is obtained by turning on the switches S2 , S4 and S6 . For both these sequences, the paths of the load current are the same as for the PWM-1 and PWM2 strategies. For the zero voltage level, four dierent control sequences are used: O1+ , O2+ when the reference voltage is positive, and O1 , O2 when the reference voltage is negative. The state O1 is obtained when the switches S4 and S5 are turned, while the state O2 is obtained when S2 , S3 and S6 are on. The state O1+ is obtained when the switches S2 and S3 are turned on. In this case, the paths of the load current are similar to those of the state O2 . The state O2+ is obtained when S1 , S4 and S5 are turned on, and the paths of the load current are similar to the state O1 [12]. The commutation sequences of the PWM-DF modulation strategy lead to a doubling of the apparent switching frequency, meaning that each IGBT works at a switching frequency fs , while the output voltage has a switching frequency equal to 2fs [12]. In comparison with the modulation strategies PWM-1 and PWM-2, PWM-DF determines a more uniform distribution of the switching losses between the inner (S3 and S4 ) and the outer (S1 and S6 ) switches . Adjustable losses distribution strategy The adjustable losses distribution modulation (PWM-ALD) [10] is a combination of the classical and PWM-DF strategies. Figures 2.13 and 2.14 (on the next pages) present how the switching signals are obtained for the PWM-ALD strategy, by using two reference signals (Sr and Sr ) which have the same phase angle and frequency, but dierent amplitudes and two carrier waves (Sc1 and Sc2 ). Through the comparison process, eight switching states are obtained: P (Vdc /2), N (Vdc /2), OIn+ , O+ , OOut+ , OOut , O and OIn (see Table 2.7 on the next page). Due to the fact that during the switching sequences O+ , OIn+ , P , OIn+ , O+ and O , OIn , N , OIn , O the outer switches (S1 and S6 ) make zero current switching, whereas the inner switches (S3 and S4 ) make hard switching, causing them to be more stressed, these two switching sequences are named Stress In mode. Due to the fact that during the switching sequences O+ , OOut+ , P , OOut+ , O+ and O , OOut , N , OOut , O the inner switches (S3 and S4 ) make zero current switching, whereas the outer switches (S1 and S6 ) make hard switching, causing them to be more stressed, these two switching sequences are named Stress Out mode [10].

32

1 0.5 S1/S2 0 -0.5 -1 0 1 0.5 S3/S4 0 -0.5 -1 0

1 0.5

Sr Sr' Sc1 Sc2

0.005

0.01

0.015

0.02

0.005

0.01

0.015 Stress Out

0.02

S5/S6 0
-0.5 -1 0

Stress Out

Stress In
0.01 0.012 0.014 0.016 0.018 0.02

0.002 0.004 0.006 0.008

Figure 2.13: PWM generation for PWM-ALD modulation strategy for 50%-50% Stress In/Stress Out ratio

Output Voltage
dc + V2

Switching State P OIn+ OOut+ O+ O OOut OIn N S1 1 1 0 0 0 0 0 0

dc V2

Switching S2 S3 0 1 0 0 0 1 0 0 1 1 1 1 1 1 1 0

Sequence S4 S5 0 1 1 1 1 1 1 1 0 0 1 0 0 0 1 0

S6 0 0 0 0 0 0 1 1

Table 2.7: Switching sequences for the 3L-ANPC PWM-ALD strategy

33

Vdc/2 Sr Sr O+ 0 S1 S2 S3 S4 S5 S6 VAO

Sc1

Vdc/2 Sr Sr P O+ OIn+ Ts 0 S1 S2 S3 S4 S5 S6 Vdc/2 (a) VAO Vdc/2 (b) 0 O+ OOut+ P OOut+ Ts O+

OIn+ 0

Sc2

Sr Sr OOIn-Vdc/2 S1 S2 S3 S4 S5 S6 VAO 0

OOInTs

Sr Sr -Vdc/2 S1 S2 S3 S4 S5 S6

O0

N OOut- OOut-

OTs

Vdc/2 (c)

VAO

Vdc/2 (d)

Figure 2.14: The switching sequences and output voltage for the 3L-ANPC PWM-ALD strategy With this strategy, during a given cycle, dierent working time rates of Stress In mode and Stress Out mode can be chosen, in order to modify the distribution of the switching losses (see Figure 2.13). When Stress In mode is used, during the positive half cycle, S1 uses signal Sr instead Sr, whereas during the negative half cycle, S4 uses Sr instead of Sr. When Stress Out mode is used, during the positive half cycle, S2 uses Sr, whereas during the negative half cycle, S3 uses Sr instead of Sr. If the conduction losses mainly stress the inner IGBTs (the conduction losses distribution depends on the modulation index M and power factor PF), then the PWM-ALD control could give more switching losses to the outer IGBTs, by increasing the rate of Stress Out mode. Otherwise, if the conduction 34

losses mainly stress the outer IGBTs, then, by increasing the rate of Stress In mode, more switching losses could be put on the inner IGBTs. Thereby, the total losses of inner and outer switches can be balanced [10].

2.3

Summary

In this chapter, the main theoretical concepts which are used throughout the entire report have been presented. The chapter starts with a brief presentation of the types of power losses which can occur in semiconductor devices. Formulas for calculating the total power losses (Ploss ) of the IGBT and diode, as the sum of the conduction (Pcond ) and switching losses (Psw ), are given. Afterwards, the three-level converter concept is introduced, as an improvement brought to the two-level structure. The additional zero level of the output voltage (voltage levels of dc dc the output voltage for the three level case are: + V2 , 0 and V2 ) will determine a lower dv harmonic distortion and a lower dt , hence making this topology well suited for high power medium voltage applications. The Active Neutral Point Clamped (ANPC) topology is then described. Compared to the basic Neutral Point Clamped (NPC) converter, this structure allows, by the use of an adequate modulation strategy, to achieve a more balanced distribution of the power losses between the semiconductor devices on the converter, and therefore overcome the main drawback of the NPC. This advantage of the ANPC is due to the two additional active switches, which replace the clamping diodes in the NPC topology. These extra switching devices will enable the ANPC to achieve the same switching states as the NPC, but with dierent switching sequences and so, the losses amongst the devices can be distributed in a more even way. Several modulation strategies used for controlling the ANPC converter are presented, with focus on how the power losses are distributed amongst the switches. The two classical modulation strategies (PWM-1 and PWM-2) do not take advantage of the multiple possibilities of the ANPC topology to obtain the zero state. By using these two modulations, there will always be an uneven distribution of losses between the inner and outer switches of the converter. A new modulation strategy, called PWM-3 has been investigated. This strategy represents a combination of the two classical methods. The switching sequences of PWM-3 are obtained by using for 50% of the reference signals period, the switching sequences of PWM-1 strategy and for the other 50%, the switching sequences of PWM-2 strategy. This way, the switching losses are redistributed amongst the inner and outer switches, hence bringing an improvement to the loss balancing issue. Other two modulation strategies are presented, namely PWM-DF [12] and PWM-ALD [10]. These two strategies also bring improvements to the loss unbalancing issue, by using more and dierent switching sequences in order to achieve the zero state. Due to the fact that the most stressed device will limit the current capability of the converter, power loss balancing amongst the switches of the converter is desired. This way, the transferred power and switching frequency of the converter can be increased, without having to increase the costs by replacing the switches with higher rated ones or bringing improvements to the cooling system.

35

Chapter 3

Simulations
The dierent modulation strategies which have been presented in Chapter 2 are going to be simulated using Matlab Simulink. The aim of this chapter is to study the distribution of the power losses amongst the six switches in the ANPC inverter.

3.1

System description

The modulation techniques presented in Chapter 2 have been tested on a single-phase ANPC converter working in inverter mode of operation, powered from two DC voltage sources. The simulations have been performed in Matlab Simulink environment. For modelling the plant (DC sources, ANPC converter, load), PLECS Toolbox was used. The general block diagram of the simulation models is presented in Figure 3.1

Sr Vload

Sr
Sc1 Gate signals Gate signals

Sc1
Iload Sc2

Sc2 Modulator

Plant

Losses calculation

(a) General block diagram

S1 S1 Sr
Sr S1 S1

Sr

S2 S3

S2
S2 S3 S4 S5 S6

Iload
S2 S3 PLECS Circuit S4 S5 S6

Iload

Sr
Sc1

3 Iload

S3

3 Iload

PWM_1
Sc1

PWM_1 S4
S5

Sc1

Sc1
Sc2
Sc2

1 1 Gate signals2 Gate signals

1 1 Gate signals Gate signals9

S4 S5 S6

PLECS Circuit
Vload

S6

Vload

2 Vload

2 Vload

Sc2

Sc2

(b) Modulator block

(c) Plant block

Figure 3.1: The general block diagram of the simulation models

37

The modulator block implements each of the ve modulation strategies which have been previously discussed. The inputs of the block are the reference signal (Sr ) and the two carriers (Sc1 and Sc2 ), based on whose comparison, the switching states of the inverters switches are obtained. The outputs of the modulator block represent the gate signals of the IGBTs. The plant block was modelled using PLECS Toolbox, which in combination with Simulink, is a very well suited tool for modelling power electronics systems that contain both electrical circuits and controllers. The structure of the plant block can be seen in Figure 3.2, and it consists of: two DC supplies; single-phase ANPC converter; RL load.

Figure 3.2: The PLECS block diagram of the plant By using PLECS Thermal Modelling Toolbox, the conduction and switching losses of the semiconductor devices can be determined. This is achieved by adding a heat sink to the simulation model. The selection of the heat sink is presented in Appendix A. Also, a thermal description needs to be added to the semiconductor components. The semiconductor devices which have been implemented in the simulation models are IGBTs with incorporated anti-parallel diode. This decision was taken in order for the behaviour of the semiconductor switches in the simulations to be similar to the behaviour of the semiconductor switches which have been used in the laboratory tests (IGBT with incorporated ultra fast soft recovery diode - IRG4PC40FD [14]. By using PLECS Thermal Toolbox, the conduction losses have been introduced in the thermal model of the device separately, for the diode and the IGBT, using the information provided in the datasheet of the IRG4PC40FD device [14]. In what concerns the switching losses, these have been introduced in the thermal model merged, because this is how this information is provided in the datasheet [14].

38

Cond_Loss

Conduction Switching

Pcond Si

PLECS Probe Si

Sw_Loss

Ploss Si Psw Si

Losses calculation Si

Figure 3.3: The Simulink block diagram of the losses calculation block
mean is presented Out1 signal In1PLECS probe 1 in Figure 2 2 The losses1 calculation block 3.3. The outputs the Conduction Switching Cond_Loss Sw_Loss thermal conduction losses and thermal switching losses of the selected IGBT with antiAverage Discrete parallel device (Si , where i = 1, 6), together. The conduction (Pcond ), switching (Psw ) and Mean Value total (Ploss ) power losses are calculated for one cycle of the reference signal (20 ms) and then displayed. The values which are displayed represent the power losses of the IGBT and diode together. In this way, the behaviour of the switches from the simulations can be compared with the results obtained in the laboratory, where the IGBT and diode are mounted in the same case.

The distribution of the losses amongst the converter switches has been tested on both an R (PF = 1) and an RL (PF = 0,85) load for a modulation index M = 1. The obtained results are presented and discussed in the following subsections.

3.2

Simulation results

In order for the results to be more clear, the power of the load was considered to be 10 kW in the simulations. This is because at this level, large currents will pass through the switches and loss balancing can be seen more easily. The DC link voltage was considered 600 V and the frequency of the carrier waves 15 kHz, except for the PWM-DF strategy, where the frequency is 7,5 kHz. In the last part of this section, the results of the simulations that had the same load like in the laboratory experiments are shown.

3.2.1

PWM-1

The simulation results obtained with a load of 10 kW (PF = 1) using PWM-1 modulation strategy are presented in Table 3.1.

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 50,36 0 50,33 50,41 0 50,44

Psw [W] 45,1 0 0 0 0 45,1

Ploss [W] 95,46 0 50,33 50,41 0 95,54

Table 3.1: Simulation results for PWM-1 modulation strategy with a 10 kW R load

39

The results presented in Table 3.1 represent the power losses of the IGBT and anti-parallel diode summed. For the resistive case the recovery diodes are not used, and so, the values which are presented represent only the losses of the IGBTs.

100 90 80 Power losses [W] 70 60 50 40 30 50,36 20 10 0 S1 S3 S4 S6 50,33 50,41 50,44 Psw Pcond 45,1 45,1

Figure 3.4: Power losses distribution for PWM-1 modulation strategy with a 10 kW load (PF = 1) As it can be seen from Table 3.1 and Figure 3.4, with PWM-1 modulation strategy the total power losses are unevenly distributed amongst the inverters switches, the outer switches (S1 and S6 ) having higher losses than the inner switches (S3 and S4 ). The dierence in losses between the two groups of IGBTs is due to the fact that S1 and S6 switch at a higher frequency (15 kHz) compared to S3 and S4 , which switch at 50 Hz, and therefore have more switching losses. The switches S2 and S5 do not have any power losses due to the fact that with a resistive load, there is no current passing through them. The disadvantage of the PWM-1 modulation strategy can be easily seen from Figure 3.4, where the outer switches have almost two times more power losses than the inner pair of switches. It can be concluded then, that with this strategy, the main drawback of the NPC topology is not overcome by the ANPC, the distribution of the losses amongst the semiconductor switches remaining unbalanced.

3.2.2

PWM-2

The simulation results obtained with a load of 10 kW (PF = 1) using PWM-2 modulation strategy are presented in Table 3.2 (on the next page). Similar to the PWM-1 case, the results represent the power losses of the IGBT and anti-parallel diode summed. For the resistive case the recovery diodes are not used, and so, the values which are presented represent only the losses of the IGBTs. As it can be seen from Table 3.2 and Figure 3.5 (on the next page), with PWM-2 modulation strategy the total power losses are unevenly distributed amongst the inverters switches, the inner switches (S3 and S4 ) having higher losses than the outer switches (S1 and S6 ). The dierence in losses between the two groups of IGBTs is due to the fact that 40

S3 and S4 switch at a higher frequency (15 kHz) compared to S1 and S6 , which switch at 50 Hz, and therefore have more switching losses.

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 50,8 0 50,8 50,75 0 50,7

Psw [W] 0 0 43,5 42,9 0 0

Ploss [W] 50,8 0 94,3 93,65 0 50,7

Table 3.2: Simulation results for PWM-2 modulation strategy with a 10 kW load (PF = 1) Similar to the PWM-1 case, the switches S2 and S5 do not have any power losses due to the fact that with a resistive load, there is no current passing through them.

100 90 80 Power losses [W] 70 60 50 40 30 50,8 20 10 0 S1 S3 S4 S6 50,8 50,75 50,7 Psw Pcond 43,5 42,9

Figure 3.5: Power losses distribution for PWM-2 modulation strategy with a 10 kW load (PF = 1) The disadvantage of the PWM-2 modulation strategy can be easily seen from Figure 3.5, where the inner switches have almost two times more power losses than the outer pair of switches. It can be concluded then, that with this strategy, the main drawback of the NPC topology is not overcome by the ANPC, the distribution of the losses amongst the semiconductor switches remaining unbalanced.

3.2.3

PWM-3

The simulation results obtained with a load of 10 kW (PF = 1) using PWM-3 modulation strategy are presented in Table 3.3. Similar to the previous cases, the results represent the power losses of the IGBT and anti-parallel diode summed. For the resistive case the recovery diodes are not used, and so, the values which are presented represent only the losses of the IGBTs. 41

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 50,83 0 50,81 50,75 0 50,73

Psw [W] 21,7 0 21,8 20,7 0 21,53

Ploss [W] 72,53 0 72,65 71,45 0 72,26

Table 3.3: Simulation results for PWM-3 modulation strategy with a 50%-50% PWM1/PWM-2 ratio and a 10 kW load (PF = 1) Similar to the previous cases, the switches S2 and S5 do not have any power losses due to the fact that with a resistive load, there is no current passing through them.
100 90 80 Power losses [W] 70 60 50 40 30 50,83 20 10 0 S1 S3 S4 S6 50,81 50,75 50,73 21,7 21,8 20,7 21,53 Psw Pcond

Figure 3.6: Power losses distribution for PWM-3 modulation strategy with a 50%-50% PWM-1/PWM-2 ratio and a 10 kW load (PF = 1) As it can be seen from Table 3.3 and Figure 3.6, with PWM-3 modulation strategy the total power losses are uniformly distributed amongst the inverters switches.

3.2.4

PWM-DF

The simulation results obtained with a load of 10 kW (PF = 1) using PWM-DF modulation strategy are presented in Table 3.4 (on the next page). Similar to the previous cases, the results represent the power losses of the IGBT and anti-parallel diode summed. For the resistive case the recovery diodes are not used, and so, the values which are presented represent only the losses of the IGBTs. As it can be seen from Table 3.4 and Figure 3.7 (on the next page), with PWM-DF modulation strategy the total power losses are uniformly distributed amongst the inverters switches. With this PWM modulation technique the switching losses are redistributed amongst the switches and so, loss balancing is obtained.

42

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 50,59 0 50,59 50,68 0 50,58

Psw [W] 20,79 0 21,51 21,3 0 21,61

Ploss [W] 71,38 0 72,1 71,98 0 72,29

Table 3.4: Simulation results for PWM-DF modulation strategy with a 10 kW load (PF = 1) Similar to the previous cases, the switches S2 and S5 do not have any power losses due to the fact that with a resistive load, there is no current passing through them.
100 90 80 Power losses [W] 70 60 50 40 30 50,59 20 10 0 S1 S3 S4 S6 50,59 50,68 50,68 20,79 21,51 21,3 21,61 Psw Pcond

Figure 3.7: Power losses distribution for PWM-DF modulation strategy with a 10 kW load (PF = 1)

3.2.5

PWM-ALD

The simulation results obtained with a load of 10 kW (PF = 1) using PWM-ALD modulation strategy are presented in Table 3.5 (on the next page). Similar to the previous cases, the results represent the power losses of the IGBT and anti-parallel diode summed. For the resistive case the recovery diodes are not used, and so, the values which are presented represent only the losses of the IGBTs. As it can be seen from Table 3.5 and Figure 3.8 (on the next page), with PWM-ALD modulation strategy the total power losses are uniformly distributed amongst the inverters switches.

43

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 45,42 0 45,4 45,5 0 45,48

Psw [W] 22,56 0 23,45 22,07 0 23,93

Ploss [W] 67,98 0 68,85 67,57 0 69,41

Table 3.5: Simulation results for PWM-ALD modulation strategy with a 50%-50% Stress In/Stress Out ratio and a 10 kW load (PF = 1) Similar to the previous cases, the switches S2 and S5 do not have any power losses due to the fact that with a resistive load, there is no current passing through them.
100 90 80 Power losses [W] 70 60 50 40 30 20 10 0 S1 S3 S4 S6 45,42 45,4 45,5 45,48 22,56 23,45 22,07 23,93 Psw Pcond

Figure 3.8: Power losses distribution for PWM-ALD modulation strategy with a 50%-50% Stress In/Stress Out ratio and a 10 kW RL load (PF = 0,85) From Figure 3.8 it can be seen that the total power losses of the semiconductor devices are smaller when compared to the previous strategies, even though the same load has been used. This apparent reduction is due to the fact that the modulation index used for obtaining the switching states for the PWM-ALD strategy is smaller1 then the value used for the other strategies, where M = 1, and hence the losses obtained in this case are smaller.

3.2.6

Results for validation in the laboratory

Due to the fact that not all the simulation conditions could be reproduced in the laboratory, another set of simulations have been done. The only parameter which changes is the load power, from 10 kW to approximately 650 W. This downscaling is due to the current limitation (5 A) of the available DC sources. This set of simulations have been performed in order to verify if even with such a small load power there are still loss balancing issues.
For the PWM-ALD strategy, two carrier waves with dierent amplitudes are used: Sr , with an amplitude of 0,9 and Sr , with an amplitude of 1.
1

44

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,59 0 0,59 0,50 0 0,59

Psw [W] 1,66 0 0 0 0 1,66

Ploss [W] 2,25 0 0,59 0,59 0 2,25

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,29 0,4 0,39 0,46 0,41 0,28

Psw [W] 0,9 0,6 0 0 0,6 0,9

Ploss [W] 1,18 1 0,39 0,46 1,01 1,17

a) PF =1

b) PF = 0,85

Table 3.6: Simulation results for PWM-1 modulation strategy

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,59 0 0,59 0,59 0 0,59

Psw [W] 0 0 1,66 1,66 0 0

Ploss [W] 0,59 0 2,25 2,25 0 0,59

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,29 0,18 0,72 0,73 0 0,28

Psw [W] 0 0 1,6 1,55 0 0

Ploss [W] 0,29 0,18 2,32 2,28 0 0,28

a) PF =1

b) PF = 0,85

Table 3.7: Simulation results for PWM-2 modulation strategy

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,59 0 0,59 0,59 0 0,59

Psw [W] 0,83 0 0,82 0,82 0 0,83

Ploss [W] 1,42 0 1,41 1,41 0 1,42

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,29 0,15 0,34 0,75 0,46 0,28

Psw [W] 0,26 0,17 0,82 0,66 0,41 0,61

Ploss [W] 0,55 0,33 1,16 1,39 0,87 0,89

a) PF =1

b) PF = 0,85

Table 3.8: Simulation results for PWM-3 modulation strategy

45

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,59 0 0,59 0,6 0 0,6

Psw [W] 0,76 0 0,79 0,78 0 0,79

Ploss [W] 1,35 0 1,38 1,38 0 1,39

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,29 0,31 0,55 0,59 0,25 0,29

Psw [W] 0,42 0,28 0,74 0,71 0,3 0,43

Ploss [W] 0,71 0,59 1,29 1,3 0,55 0,71

a) PF =1

b) PF = 0,85

Table 3.9: Simulation results for PWM-DF modulation strategy

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,53 0 0,53 0,53 0 0,53

Psw [W] 0,83 0 0,86 0,81 0 0,88

Ploss [W] 1,36 0 1,39 1,34 0 1,41

Switch S1 S2 S3 S4 S5 S6

Pcond [W] 0,21 0,17 0,68 0,71 0 0,2

Psw [W] 0,27 0 1,21 0,83 0 0,6

Ploss [W] 0,48 0,17 1,89 1,54 0 0,8

a) PF =1

b) PF = 0,85

Table 3.10: Simulation results for PWM-ALD modulation strategy

3.3

Summary

This chapter treats the simulation part of this report. In the beginning of the chapter, the structure of the simulation models is described. The general system is divided into three main blocks: the plant, composed of the DC sources, the single-phase ANPC converter and the load, the modulator block and the losses calculation block. In order to be able to calculate the power losses of the inverters switches, their thermal model was implemented using PLECS Thermal Toolbox. Because in the inverter from the laboratory setup, the IGBTs and the anti-parallel diode are mounted in the same case, the same conguration of the semiconductor devices was used in the simulations. The losses of the converter are presented as the power losses of the IGBT and anti-parallel diode summed for each of the devices. In this way, the behaviour of the semiconductor switches in the simulations is similar to the behaviour of the semiconductor switches which have been used in the laboratory tests (IRG4PC40FD). All the modulation strategies which have been presented in the previous chapter have been simulated for a 10 kW resistive load, with a frequency of the carrier waves equal to 15 kHz (except the PWM-DF strategy, where the frequency of the carriers was set to 7,5 kHz), and a unity modulation index (except from PWM-ALD strategy, where two reference signals are used, one having M = 1, while the other has M = 0,9). 46

From the simulation results it can be seen that as expected, with PWM-1 and PWM2, the main drawback of the NPC topology is not overcome by the ANPC, hence loss balancing amongst the switches of the inverter is not achieved. With PWM-3, PWM-DF and PWM-ALD it can be seen that the total power losses are evenly distributed between the switches. Due to the fact that in the laboratory tests, the maximum load which could be used with the available equipment was of 650 W, the simulations have been repeated for this new situation, for both R and and RL load (PF = 0,85), in order to check if for this low power level, the issue of loss balancing is still valid.

47

Chapter 4

Laboratory implementation
The dierent modulation strategies which have been described in Chapter 2 are going to be experimentally tested, in order to validate the simulation results presented in Chapter 3. A description of the laboratory setup which has been used for the experimental tests is given. The obtained results are presented and discussed.

4.1

Test setup

The block diagram of the experimental test setup is presented in Figure 4.1.

T1

D1 Power Analyzer Load D2 Differential probe

T5

D5 T2 D6 T3

A
T6 D3

T4

D4

PC

DSP + Interface Board

Dc Power Supply

Figure 4.1: Block diagram of the experimental test setup The laboratory setup can be seen in Figure 4.2, and is composed of: 2 x 300 V, 5 A DC power supply; 2 x 24 V, 3 A DC power supply; single-phase ANPC converter; load resistor; 49

 load inductor; power analyser; dierential probe; oscilloscope; single-phase power analyser; TMS320F28335 eZdsp board; interface board; PC. The detailed list of laboratory instruments which have been used is given in Appendix C.
(10) (7) (2) (5)

(4)

(1)

(3)

(6)

(9)

(8)

(11)

Figure 4.2: Laboratory test setup: (1)- 300 V, 5 A DC power supply; (2)- 24 V, 3 A DC power supply; (3)- single-phase ANPC converter; (4)- load resistor; (5)- load inductor; (6)- thermal camera; (7)- single-phase power analyser; (8)- TMS320F28335 eZdsp board; (9)- interface board; (10)- oscilloscope; (11)- PC

4.1.1

ANPC converter

The inverter used in the experiments was a single-phase 3L-ANPC VSI platform, developed by Andrzej Adamczyk and Maciej Swierczynski [7]. The inverter board is divided into a high-power part mainly containing the power switches, and a low-power part which transfers the command signals form the control unit. For safety and noise reasons, both parts are electrically insulated from each other [7]. Initially, the ANPC inverters six switches were driven as three complementary pairs, using only three signals. To avoid short circuits caused by an incorrect modulation, a hardware dead time was used, in order to insure a constant delay between the two switches in each of the three pairs [7]. In order to implement PWM-DF and PWM-ALD modulation strategies, the inverter switches needed to be driven using six independent gate signals. In order to achieve this, the dead time generator was removed, and replaced by an extension interface board. Details about the extension board are given in Appendix B. 50

The communication with the control unit is achieved through a ber optic bus. The inverter board also provides protection for a safe operation of the power switches, like [7]: gate protection; over voltage limiting circuitry; under voltage lock-out; short circuit protection ; over temperature protection.

4.1.2

DSP board

The control of the inverter was implemented on a DSP board from Texas Instruments, which has the following main features [13]: TMS320F28335 Digital Signal Controller; 150 Mhz operating speed; 32-bit oating point unit; 68K bytes on-chip RAM; 512K bytes on-chip Flash memory; 12 bit analog to digital (A/D) converter with 16 input channels; 12 ePWM modules (6 modules with 2 ePWM outputs each).

4.1.3

Interface board

The communication between the DSP and the inverter is assured through an interface compatible with the TI TMS320F28335 eZdsp board. The features of this interface board are listed below: 24 V DC supply voltage; 10 PWM outputs available for optic ber transmission; 2 general purpose digital inputs are provided as optic ber receivers; 2 voltage sensors scaled for measuring 700 V; 3 voltage sensors scaled for measuring 400 V; 6 current hall-sensors scaled for measuring 35 A.

51

4.2

Modulation implementation on the DSP

The software implementation of the control structure was developed using Matlab 2009b Simulink environment. The code was automatically generated from the simulation model, and then loaded into the TMS320F28335 eZdsp board using Code Composer Studio v3.3. In order to generate the code by using Matlab, the model of the control structure was implemented in discrete time domain. Also, some dedicated blocks were used, like Digital Output and ePWM blocks. These were added to the model from the Target Support Package TC2 Toolbox, for the F28335 eZdsp target board.

S1

WA WB
S2

C280x/C28x3x F28335 eZdsp ePWM ePWM1

S3

WA
Sr

C280x/C28x3x 1 GPIOx

C28x3x

WB Sr
S4

ePWM ePWM2

Enable

GPIO DO Digital Output

S5

WA WB
S6

C280x/C28x3x

C280x/C28x3x

ePWM ePWM3

ePWM ePWM4

Modulator

Figure 4.3: Simulink model used for DSP implementation The Simulink model of the control structure used to generate the code for the DSP board is presented in Figure 4.3. The Target Preferences block that was added to the model, provides access to the processors hardware settings, in order to do the necessary congurations before generating the code. The ePWM blocks congure the corresponding ePWM modules of the DSP board, in order to obtain the switching signals for the inverter. The ePWM1, ePWM2 and ePWM3 blocks are used for generating the switching signals for the switches S1 and S2 , S3 and S4 , and S5 and S6 , respectively (see Figure 4.1). The ePWM4 block is used for disabling the corresponding channels, in order to prevent the heating of the ber optic transmitters from the interface board. The dead time that was used for generating the switching signals for the IGBTs belonging to the same leg, was implemented software using the ePWM blocks, and set to 3,4 s. The choice of dead time depends on the turn-on and turn-o characteristics of the IGBTs, and it was selected in order to safely switch these on and o, without short circuiting the DC sources. The Digital Output block congures the GPIO11 pin to operate as a digital output pin. This pin is set to 1, in order to enable the PWM outputs on the interface board.

52

4.3

Experimental results

All ve modulation strategies which have been simulated in Chapter 3, have also been tested experimentally, using the experimental setup from Figure 4.1. In order to study the distribution of the losses amongst the inverter switches, thermal pictures have been taken for each case. With the help of the thermal camera, also temperature measurements have been performed. Because in the semiconductor devices of the inverter which has been used in the laboratory tests, both the IGBT and the diode are incorporated in the same case, the temperatures measured with the thermal camera will represent the the sum of the power losses for both devices, manifested as heat. All the tests have been performed only for the inverter mode of operation of the ANPC converter, for both R and an RL load (PF = 0,85). The parameters used in the experimental tests are given in Table 4.1.

Parameter DC-link voltage Switching frequency Load resistance Load inductance Modulation index Vdc fsw Rload Lload M

Value 600 V 15 kHz 65 128 mH 1

Table 4.1: Simulation parameters For all the modulation strategies, the frequency of the carriers have been set to 15 kHz, except from the double frequency modulation strategy, where the carrier wave frequency was set to 7,5 kHz. The obtained experimental results are presented and discussed in the following sections.

4.3.1

R load

PWM-1 The experimental results which have been obtained for a resistive load using the PWM-1 modulation strategy are presented in Figure 4.4 (on the next page). With the PWM-1 strategy, only the outer IGBTs (S1 and S6 ) switch, while the inner pair (S3 and S4 ) suers only conduction losses. The thermal picture presented in Figure 4.4 conrms this uneven distribution in the power losses amongst the outer and inner switches. It can be seen that due to higher power losses, the temperatures of S1 and S6 are the highest, while for S3 and S4 , which have only conduction losses, the temperature is lower, with approximately 10o C. Because the inverter supplies a resistive load, the switches S2 and S5 should not have any power losses, and therefore should remain at room temperature. But, due to the parasitic inductance of the load (the power factor read from the power analyser was PF = 0,99), the two switches will suer small losses, caused by the current which passes through them during zero state. Another reason for their increased temperature compared to the ambient temperature is due to the presence of the nearby hotter switches (the switches are mounted on the inverter leg close one next to the other). 53

Figure 4.4: Thermal picture of the ANPC inverter with R load for PWM-1 modulation strategy

PWM-2 The experimental results which have been obtained for a resistive load using the PWM-2 modulation strategy are presented in Figure 4.5 (on the next page). With the PWM-2 strategy, only the inner IGBTs (S3 and S4 ) switch, while the outer pair (S1 and S6 ) suers only conduction losses. The thermal picture presented in Figure 4.5 conrms this uneven distribution in the power losses of the outer and inner switches. It can be seen that due to higher power losses, the temperatures of S3 and S4 are the highest, while for S1 and S6 , which have only conduction losses, the temperature is approximately 25o C lower. The increased temperature of S2 and S5 compared to the ambient temperature is due to the same reasons which are stated in the comments of the experimental results obtained for the PWM-1 modulation strategy.

pwm-1-r.jpg

54

Figure 4.5: Thermal picture of the ANPC inverter with R load for PWM-2 modulation strategy

PWM-3 The experimental results which have been obtained for a resistive load using the PWM-3 modulation strategy are presented in Figure 4.6 (on the next page). A ratio of 50%-50% for the PWM-1 and PWM-2 working times determines a more balanced distribution of the power losses between the inner and outer switches, compared to the classical strategies. The thermal picture of the inverter leg controlled with the PWM-3 strategy presented in Figure 4.6 conrms this improvement, as the dierences between the temperatures of the outer and inner switches are not as big as with the PWM-1 or PWM-2 modulations. The increased temperature of S2 and S5 compared to the ambient temperature is due to the same reasons which are stated in the comments of the experimental results obtained for the PWM-1 modulation strategy. It can be seen from Figure 4.6, that the values obtained for the temperatures of the switches are lower than those obtained with the classical modulations, even if the load, the switching frequency and the modulation index were the same. This dierence is due to the fact that the measurement of the temperature was performed for a shorter working time of the inverter (half, when compared to the measurements for the other strategies). pwm-2-r.jpg This measurement is still valid, because the distribution of the power losses between the semiconductor devices was of interest, and not the exact value of the losses, especially since the tests have been performed for the same conditions.

55

Figure 4.6: Thermal picture of the ANPC inverter with R load for PWM-3 modulation strategy

Double frequency PWM strategy The experimental results which have been obtained for a resistive load using the PWM-DF modulation strategy are presented in Figure 4.7 (on the next page). With PWM-DF modulation strategy, the distribution of the power losses between switches S1 , S3 , S4 and S6 should be more balanced when compared to the classical strategies. The thermal picture of the inverter leg controlled with the PWM-DF strategy presented in Figure 4.7 conrms that this modulation brings an improvement to the loss balancing issue, the dierence between the temperatures of the inner and outer switches being reduced, when compared to PWM-1 or PWM-2 strategies. The increased temperature of S2 and S5 compared to the ambient temperature is due to the same reasons which are stated in the comments of the experimental results obtained for the PWM-1 modulation strategy. If the frequency of the carrier waves in the PWM-DF modulation strategy would be double (equal to 15 kHz, as for the cases of PWM-1 and PWM-2 strategies), the power losses of the switches would increase.

pwm-3-r.jpg

56

Figure 4.7: Thermal picture of the ANPC inverter with R load for PWM-DF modulation strategy

Adjustable loss distribution PWM strategy The experimental results which have been obtained for a resistive load using the PWMALD modulation strategy are presented in Figure 4.8 (on the next page). With the PWM-ALD modulation strategy, it would be expected that the power losses of the inner and outer switches should be similar. The thermal picture of the inverter leg which is presented in Figure 4.8, shows that the dierence between the temperatures of switches S1 and S3 is very small. So, it can be concluded that this method brings an improvement to the loss balancing issue, but only for the positive cycle of the reference signal. The issue arises for the negative cycle of the reference signal, where there is a bigger dierence between the temperatures of switches S4 and S6 . Still, in comparison with PWM-1 or PWM-2 modulation strategies, where this dierence is almost double, the PWM-ALD strategy determines a more even distribution of the power losses amongst the switches. A detailed reinvestigation of the code implemented on the DSP shows that S6 uses only the reference signal from Stress In, which has an amplitude of 0,9 instead of using both reference signals and applying a 50%-50% Stress In/Stress Out ratio. This unsymmetry of the reference signals (unsymmetry of the modulation index) explains why the temperature of S6 lower than the temperature of Spwm-df-r.jpg 1 , instead of being similar, if the Stress In/Stress Out ratio would have been correctly implemented.

57

Figure 4.8: Thermal picture of the ANPC inverter with R load for PWM-ALD modulation strategy

4.3.2

RL load

The experimental results which have been obtained with an RL load (PF = 0,85) for all the ve strategies which have been presented in Chapter 2, are presented in Figures 4.9 - for PWM-1, 4.10 - for PWM-2, 4.11 - for PWM-3, 4.12 - for PWM-DF and 4.13 - for PWM ALD (on the next pages).

pwm-ald-r.jpg

58

Figure 4.9: Thermal picture of the ANPC inverter with RL load for PWM-1 modulation strategy

pwm-1-rl.jpg

Figure 4.10: Thermal picture of the ANPC inverter with RL load for PWM-2 modulation strategy

59

Figure 4.11: Thermal picture of the ANPC inverter with RL load for PWM-3 modulation strategy

pwm-3-rl.jpg

Figure 4.12: Thermal picture of the ANPC inverter with RL load for PWM-DF modulation strategy

60

Figure 4.13: Thermal picture of the ANPC inverter with RL load for PWM-ALD modulation strategy The measured temperatures of the switches which have been obtained for all the discussed modulation strategies are summarized in Table 4.2. Switch S1 S2 S3 S4 S5 S6 PWM-1 46 34,5 43,1 53,6 45,8 47,2 Modulation strategy PWM-2 PWM-3 PEM-DF 34,3 42,1 57,3 40,1 40,8 38,7 58,8 49,6 65,5 59,5 55,6 66,4 41,2 40,4 38,7 39,4 42,1 59

PWM-ALD 44,5 37,8 51,3 50,8 37,9 38,9

Table 4.2: The temperatures [o C ] of the switching devices obtained for the RL load Unlike the R load case, with RL load also the diodes will conduct. Because the diode is incorporated in the same case with the IGBT, the temperature measured with the thermal camera represents the the sum of both the IGBT and diode power losses, manifested as pwm-ald-rl.jpg heat. With an RL load, the zero switches (S2 and S5 ) are expected to have more losses then compared to the R load case, because they carry a higher current during zero state, due to the stored energy in the inductance. The thermal pictures of the inverter for all the modulation strategies conrm this. In order to explain the uneven temperature distribution amongst the complementary switches, a more thorough investigation in the laboratory would be needed. Based on the the waveforms of the output voltages for PWM-1, PWM-2 and PWM-3 modulation

61

strategies1 , which are presented in Figures 4.14, 4.15 and 4.16, it can be seen that the amplitude of the voltage during the negative cycle of the reference signal is higher than the amplitude during positive cycle of the reference signal. This unbalancing of the output voltage is also reected in the temperature distribution amongst the switches. The switches which conduct during the negative cycle are hotter than the switches which conduct on the positive cycle, so the switch S5 is hotter than S2 and the switch S4 is hotter than S3 .
250 200 150 100

Amplitude [V]

50 0 -50 -100 -150 -200 -250 0

0.01

0.02

0.03

0.04

0.05

0.06

Time [s]

Figure 4.14: The waveform of the output voltage (measured on the resistor) for RL load (PF =0,85) with PWM-1 modulation strategy
200 150 100 50

Amplitude [V]

0 -50 -100 -150 -200 -250 0

0.01

0.02

0.03

0.04

0.05

0.06

Time [s]

Figure 4.15: The waveform of the output voltage (measured on the resistor) for RL load (PF =0,85) with PWM-2 modulation strategy
The waveforms for the PWM-DF and PWM-ALD strategies are missing due to the limited amount of time for access in the laboratory
1

62

250 200 150 100

Amplitude [V]

50 0 -50 -100 -150 -200 -250 0

0.01

0.02

0.03

0.04

0.05

0.06

Time [s]

Figure 4.16: The waveform of the output voltage (measured on the resistor) for RL load (PF =0,85) with PWM-3 modulation strategy

4.4

Summary

This chapter treats the laboratory implementation part of this report. In the beginning of the chapter, the laboratory setup is described. The inverter used in the experimental tests was a low voltage single-phase ANPC inverter developed by [7]. The control of the inverter has been implemented on a TMS320F28335 eZdsp. The communication between the DSP and the semiconductor switches is achieved through an interface which is compatible with this DSP board. In order be able to drive the switches with six independent signals, an extension board for the control part of the inverter leg was developed. The code for the control strategies which have been implemented on the DSP was generated using Matlab Simulink. All ve modulation strategies which have been simulated in Chapter 3, have also been tested experimentally. With the help of a thermal camera, temperature measurements have been performed on the inverter. Because in the semiconductor devices of the inverter, both the IGBT and the diode are incorporated in the same case, the temperatures measured with the thermal camera represent the the sum of the power losses for both devices, manifested as heat. All the tests have been performed only for the inverter mode of operation of the ANPC converter, for both R and an RL load (PF = 0,85). In the case of the resistive load, the experimental results conrm the simulation results obtained in the previous chapter in what concerns the distribution of the power losses (expressed as temperatures) amongst the switches of the inverter. The temperatures [o C ] of the switching devices obtained for the resistive load are summarized in Table 4.3 (on the next page). In the case of the RL load (PF = 0,85), the loss balancing is not as evident as for the resistive load, due to the fact that in this case also the anti-parallel diodes will conduct, and therefore their losses will add to the losses of the IGBTs. 63

Switch S1 S2 S3 S4 S5 S6 PWM-1 70,9 34,2 55,1 57,9 37,3 68,3

Modulation strategy PWM-2 PWM-3 PWM-DF 53,9 42,5 61,1 36,5 31,9 33,3 78,2 46,5 65,2 77,5 50,6 66,4 36,3 33,4 33,4 53,1 45 62,9

PWM-ALD 68,8 35,7 65,2 64,4 35,7 57,5

Table 4.3: The temperatures [o C ] of the switching devices obtained for the R load

An uneven distribution of the temperatures amongst the complementary switches is obtained. The waveforms of the output voltages have been measured, and it can be seen that the amplitude during the negative cycle of the reference signal is higher than the amplitude during positive cycle of the reference signal. This unbalancing of the output voltage is also reected in the temperature distribution amongst the switches. So, the switches which conduct during the negative cycle are hotter than the switches which conduct on the positive cycle.

64

Chapter 5

Conclusions
5.1 Review of the main tasks

The goal of this project was to investigate dierent modulation strategies for the Active Neutral Point Clamped (ANPC) topology, in order to achieve an even distribution of the power losses amongst the switches of the converter. Due to the fact that the most stressed device will limit the current capability of the converter, power loss balancing is desired. This way, the transferred power and switching frequency of the converter can be increased, without having to increase the costs by replacing the switches with higher rated ones or bringing improvements to the cooling system. After the background an motivation of this project have been briey presented, the main goals and limitations were established. The main theoretical concepts which have been used throughout the entire report have been presented in the beginning of chapter 2. After a brief presentation of the types of power losses which can occur in semiconductor devices, the three-level converter concept was introduced, as an improvement brought to the two-level structure. The Active Neutral Point Clamped (ANPC) topology was then described. Compared to the basic Neutral Point Clamped (NPC) converter, this strategy allow by the use of an adequate modulation strategy, to achieve a more balanced distribution of the power losses between the semiconductor devices on the converter, and therefore overcome the main drawback of the NPC. Several modulation strategies used for controlling the ANPC converter were presented, with focus on how the power losses are distributed amongst the switches. The two classical modulation strategies (PWM-1 and PWM-2) do not take advantage of the multiple possibilities of the ANPC topology to obtain the zero state. By using these two modulations, there will always be an uneven distribution of losses between the inner and outer switches of the converter. A new modulation strategy, called PWM-3 has been investigated. This strategy represents a combination of the two classical methods. The switching sequences of PWM-3 are obtained by using for 50% of the reference signals period, the switching sequences of PWM-1 strategy and for the other 50%, the switching sequences of PWM-2 strategy. This way, the switching losses are redistributed amongst the inner and outer switches, hence bringing an improvement to the loss balancing issue. Other two modulation strategies were presented, namely PWM-DF [12] and PWM-ALD [10]. These two strategies also bring improvements to the loss unbalancing issue, by using more and dierent switching sequences in order to achieve the zero state. The third chapter contains the simulation part of the report. In the beginning of the chapter, the structure of the simulation models was described. The general system was divided into three main blocks: the plant, composed of the DC sources, the single-phase 65

ANPC converter and the load, the modulator block and the losses calculation block. In order to be able to calculate the power losses of the inverters switches, their thermal model was implemented using PLECS Thermal Toolbox. Because in the inverter from the laboratory setup, the IGBTs and the anti-parallel diodes are mounted in the same case, the same conguration of the semiconductor devices was used in the simulations. The losses of the converter are presented as the power losses of the IGBT and anti-parallel diode summed for each of the devices. In this way, the behaviour of the semiconductor switches in the simulations is similar to the behaviour of the semiconductor switches which have been used in the laboratory tests (IRG4PC40FD). All the modulation strategies which have been presented in the previous chapter have been simulated for a 10 kW resistive load, with a frequency of the carrier waves equal to 15 kHz (except the PWM-DF strategy, where the frequency of the carriers was set to 7,5 kHz), and a unity modulation index (except from PWM-ALD strategy, where two reference signals are used, one having M = 1, while the other has M = 0,9). From the simulation results it can be seen that as expected, with PWM-1 and PWM-2, the main drawback of the NPC topology is not overcome by the ANPC, hence loss balancing amongst the switches of the inverter was not achieved. With PWM-3, PWM-DF and PWM-ALD it can be seen that the total power losses are evenly distributed between the switches. Due to the fact that in the laboratory tests, the maximum load which could be used with the available equipment was of 650 W, the simulations have been repeated for this new situation, for both R and and RL load (PF = 0,85), in order to check if for this low power level, the issue of loss balancing is still valid. The fourth chapter presents the laboratory part of this report. In the beginning of the chapter, the laboratory setup was described. The code for the control strategies which have been implemented on the DSP was generated using Matlab Simulink. All ve modulation strategies which have been simulated in Chapter 3, have also been tested experimentally. With the help of a thermal camera, temperature measurements have been performed on the inverter. Because in the semiconductor devices of the inverter, both the IGBT and the diode are incorporated in the same case, the temperatures measured with the thermal camera represent the the sum of the power losses for both devices, manifested as heat. All the tests have been performed only for the inverter mode of operation of the ANPC converter, for both R and an RL load (PF = 0,85). In the case of the resistive load, the experimental results conrm the simulation results obtained in the previous chapter in what concerns the distribution of the power losses (expressed as temperatures) amongst the switches of the inverter. In the case of the RL load (PF = 0,85), the loss balancing is not as evident as for the resistive load, due to the fact that in this case also the anti-parallel diodes will conduct, and therefore their losses will add to the losses of the IGBTs. In this case, an unbalancing of the output voltages has been observed on the oscilloscope. This unsymmetry was also reected in the temperature distribution amongst the switches. The nal chapter of the report contains the conclusions and ideas for future work.

5.2

Future work

Because the experimental results which have been obtained for the RL load are not so clear, it could be of interest to perform more tests for this type of load, in order to study how the power losses are distributed amongst the semiconductor device of the converter and to discover the source of the unbalanced output voltage. Only power losses (total for the IGBT and anti-parallel diode) are provided by the implemented simulations. This information is enough if the purpose of the analysis is to

66

study the way that the losses are distributed amongst the switches of the inverter for a resistive load. In order to perform a more thorough investigation, especially for RL loads, some improvements could be brought to the simulations, like: semiconductor switch modelled by separate IGBT and diode; evaluation of the temperature in the simulation. In order to study better the advantages of PWM-ALD strategy, simulations and experiments could be performed for dierent Stress In/Stress Out ratios, and for loads with dierent power factors. Due to the fact that the converter which has been used for the laboratory test was not build for loss balancing analysis purposes, the switches which have been used have the IGBT and the anti-parallel diode mounted in the same case. In this case it is impossible to analyse only the IGBT power losses, for example. By building a new converter leg, which has the IGBT and diode mounted separately could allow a more detailed analysis of the power distribution. The ANPC converter is used for high power medium voltage drives for industry, and so it would be of interest to study the loss balancing modulation strategies on a machine load.

67

Bibliography
[1] T. Bruckner, S. Bernet, Loss Balancing in Three-Level Voltage Source Inverters Applying Active NPC Switches, IEEE 32nd Annual Power Electronics Specialists Conference, 2001, Volume 2, Pages 1135-1140; [2] A. Nabel, I. Takahashi, H. Akagi, A New Neutral-Point-Clamped PWM Inverter, IEEE Transactions on Industry Applications, September 1981, Volume IA-17, Issue 5, Pages 518-523; [3] T. Bruckner, S. Bernet, H. Guldner, The Active NPC Converter and Its Loss-Balancing Control, IEEE Transactions on Industrial Electronics, June 2005, Volume 52 , Issue 3, Pages 855-868; [4] Graovac Dusan, Marco Purschel, IGBT Power losses Calculation Using the Data-Sheet Parameters, Inneon Automotive Power, Application Note v 1.1, January 2009; [5] Bin Wu, High-Power Converters and AC Drives, John Wiley & Sons Inc., First Edition, 2006, ISBN 13-978-0-471-73171-9; [6] Muhammad H. Rashid, Power Electronics Handbook, Acadamic Press, First Edition, 2001 [7] Maciej Swierczynski, Andrzej Adamczyk, Modulation of Three Level Inverter with Common Mode Voltage Elimination and DC Link Balancing, Aalborg University, 2009; [8] Hongyang Wu, Xiangning He, Inhrent Correlation Between Multilevel Carrier-Based PWM and Space Space Vector PWM:Principle and Application, 4th IEEE International Conference on Power Electronics and Drive Systems, Proceedings, 22-25 October 2001, volume 1, pages 276 - 281, ISBN 0-7803-7233-6; [9] B.P. McGrath, D.G. Holmes, A Comparison of Multicarrier PWM Strategies for Cascaded and Neutral Point Clamped Multilevel Inverters, IEEE 31st Annual Power Electronics Specialists Conference, 18-23 June 2000, Volume 2, Pages 674 - 679, ISBN 0-7803-5692-6; [10] Lin Ma, Tamas Kerekes, Remus Teodorescu, Xinmin Jin, Marco Liserre, Pedro Rodriguez, The PWM Strategies of Grid-connected Distributed Generation Active NPC Inverters, IEEE Energy Conversion Congress and Exposition, 20-24 September 2009, pages 920 - 927, ISBN 978-1-4244-2893-9; [11] Ionut Trintis, Active Neutral Point Clamped Converter, Aalborg University, 2008; [12] D. Floricau, E. Floricau, M. Dumitrescu, Natural Doubling of the Apparent Switching Frequency using Three-Level ANPC Converter, International School on Nonsinusoidal Currents and Compensation, 10-13 June 2008, pages 1-6, ISBN 978-1-4244-2129-9; [13] eZdspT M F38335 Technical Reference; 69

[14] International Rectier, Insulated Gate Bipolar Transistor with ultra fast soft recovery diode IRG4PC40FD - Datasheet; [15] HS Marston Aerospace,Heat Sinks for Electronics Cooling - Technical Info, Available from http://www.hsmarston.co.uk/technical technical 01.htm [cited on 16 April 2010]; [16] PLECS User manual, Version 2.2, 2009;

70

Appendix A

Heat sink selection

A very important aspect in converter design is the selection of the cooling system for the semiconductor devices. The most handy solution is to passively cool the switches by mounting them on a heat sink. The purpose of the heat sink is to dissipate the heat generated by Joule eect due to the current which passes through the devices, preventing them from becoming too hot, which would lead to their destruction. In order to better observe the temperature of each switch, individual heat sinks are going to be mounted. For choosing the heat sink, the total power losses of the semiconductor device need to be calculated. For this calculation, the inverter is considered to be controlled with the PWM2 modulation strategy, which stresses the most the semiconductor devices, especially the inner switches. The switching frequency is 15 kHz and the load is a 3 kW R load (PF = 1). The losses in the semiconductor device are represented by conduction and switching losses for both the transistor and the antiparallel diode, as presented in Equation A.1. Ploss = Pcond + Psw [W ] (A.1)

The conduction losses can be calculated from Equation A.2 [4].

2 Pcond = VCE 0 ICav + rC IC rms

[W ]

(A.2)

where Vf is the forward voltage drop at zero current [V], Iavg is the average current through the device [A], rf is the forward resistance [] and Irms is the rms value of the current through the device [A]. The forward voltage drop Vf and the forward transconductance are provided in the datasheet of the selected semiconductor device (IRG4PC40FD) [14]: VCE 0 = 0, 9 V gC = 9, 2 S The forward resistance can be calculated from the transconductance as: rC = 1 = 0, 11 gC

The switching losses can be calculated from Equation A.3 [4]: Psw = 1 fsw T
Tsw

e(i)dt
0

[W]

(A.3)

71

where fsw is the switching frequency [Hz], T is fundamental voltage period [s], Tsw is the switching period [s], e(i) is the total switching energy losses for the IGBT together with the reverse recovery diode [J]. In the IRG4PC40FD datasheet [14] it is provided a chart for the total switching losses versus the collector-to-emitter current, for currents above 13 A. Due to the fact that in the considered operating conditions, the current through the device is approximately 4 A, the given graph has been extended, as presented in Figure A.1.

5 4,5 4 3,5 3 2,5 2 1,5 1 0,5 0 0 5 10 15

Totalswitchingenergylosses[mJ]

y=0,181x+0,11 R=0,9997

20

25

30

Collectortoemittercurrent[A]

Figure A.1: Typical switching losses versus the collector-to-emitter current In order to analytically calculate the power losses, a Matlab Simulink simulation model has been developed (see Figure A.4 and Figure A.5). This way, the calculation can also be performed also for other operating conditions of the inverter (dierent load, modulation technique, switching frequency, etc.) The values of the total inverter losses for each semiconductor device are given in Table A.1. Switch Total power losses [W ] S1 6,1 S2 0 S3 25 S4 25 S5 0 S6 6,1

Table A.1: Total power losses of the semiconductor devices As it can be seen from Table A.1, with PWM-2 modulation strategy the inner switches (S3 and S4 ) are the most stressed. The losses in these devices will be considered for sizing the heat sink. In order to size the heat sink the equivalent electrical model of thermal behaviour for the selected switch is considered (see Figures A.2 and A.3 on the next page) [15]. The other heat sinks are going to be selected to be identical.

72

Figure A.2: Device and heat sink physical model

Tj Rjc P

Tc Rch

Th Rha

Ta

Figure A.3: Equivalent electrical model for a semiconductor device, where: Q - heat source which has a current source as an electrical correspondent [W]; Tj - junction temperature [o C ]; Tc - temperature of the case [o C ]; Th - temperature of the heat sink [o C ]; Ta ambient temperature [o C ]; Rjc - junction-to-case resistance [o C/W ]; Rch - case-to-heat sink resistance [o C/W ]; Rha is heat sink-to-ambient resistance [o C/W ] In the equivalent electrical model, the temperatures are seen as node potentials. The temperature dierence between the nodes is treated as a voltage drop on the equivalent thermal impedance, due to the carried losses [15]. The aim of the calculations is to assess the maximum junction temperature of the semiconductor. The model and the resulting equations are approximate, mainly because [15]: the heat transfer process is static or slowly varying over time (order of magnitude of seconds); the calculations do not take into account that there are other paths of heat (between the device and the ambient), which should be represented in the scheme by additional resistances, but can be neglected in a rst approximation; the event of heat transfer (especially between the heat sink and the ambient) is nonlinear because it involves simultaneously heat transfer by conduction, convection and radiation; the presence of any other heat source nearby (like other sinks, power resistors, etc.) reduces the cooling eciency; it is a model that has been simplied to one-dimension.

73

The junction-to-case resistance Rjc and the case-to-heat sink resistance Rch are given in the datasheet of the semiconductor device IRG4PC40FD [14]: Rjc = 0, 77 o C/W Rch = 0, 24 o C/W The maximum working temperature of the junction is Tj = 150 o C and the ambient temperature is considered Ta = 25 o C . The heat sink-to-ambient resistance, Rha can be evaluated using Equation A.4 [15]. Tjmax Ta = P (Rjc + Rch + Rha ) [o C ] (A.4)

The required minimum thermal resistance for the heat sink can be determined from Equation A.5 [15]. Rha = Tjmax Ta (Rjc + Rch ) P [o C/W ] (A.5)

The value which is obtained for the thermal resistance of the heat sink is Rha = 5 o C/W

74

6.094 Cond_Losses S1 PcS1 PcS1 6.157 PsS1 Total_Losses S1 6.094 Cond_Losses S3 PcS3 25.02 PsS1 Cond_Losses S2 PsS3 0.0055 PsS2 PsS5 0.0055 Swit_Losses S2 Total_Losses S2 PcS2 18.93 Swit_Losses S3 0 PsS3 Total_Losses S3 0.0631 PcS5 Swit_Losses S1 PcS3

PcS1

Is1

Is1

PcS2

PcS2

PcS3

Is2

Is2

PcS4

PcS4

PcS5

Is3

Is3

PcS6

PcS6

PsS1

Is4

Is4

PsS2

PsS2

PsS3

Is5

Is5

PsS4

PsS4

PsS5

Is6

Is6

PsS6

PsS6

0 Cond_Losses S6 PcS6 0.0055 PsS6 Total_Losses S6 6.095 4.995 Rth [C/W] 6.095 Cond_Losses S5 PcS5 6.158 PsS5 Total_Losses S5 0.06312 Swit_Losses S5 18.94 Swit_Losses S4 0.0055 Swit_Losses S6 PcS4 25.03 PsS4 Total_Losses S4 Cond_Losses S4

Rthjc

Tj

Rthcs

Ta

PcS3

Figure A.4: Matlab Simulink simulation model for heat sink calculation

PsS3

1 Is1 2 Is2 3 Is3 4 Is4 5 Is5 6 Is6 0

In Mean signal rms

1 PcS1

1/gfe

2 PcS2

sqrt 3 PcS3

4 PcS4 Uce0 5 PcS5

6 PcS6

0.001

f_switching

7 PsS1
Imean fcn e

8 PsS2

9 PsS3

10 PsS4

11 PsS5

12 PsS6

fref

Figure A.5: Matlab Simulink simulation model for heat sink calculation - subsystem

76

Appendix B

Extension interface board

The ANPC converter [7] was build to be driven with three optical signals, while the remaining three complementary signals were generated hardware by using a dead time generator. This feature became a limitation in some situations, like in the case of PWM-DF and PWM-ALD modulation strategies, where the switches needed to be controlled individually, therefore requiring six independent switching signals. To overcome this limitation, another three opto receivers have been added. In order not to perform any hardware modications on the inverter leg, an extension board containing the extra opto receivers has been built, and all the drive signals are routed to it, and then re-routed to the inverter leg through the pins where the dead time generator was. The diagram and the PCB layout o the extension board can be seen in Figure B.1.
5 4 3 2 1

VCC C4 100u 18 U5
D

C5 100n

U4 R ENAR 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

con18 VCC UU UL NU NL BU BL OSC RC IN 18 17 16 15 14 13 12 11 10 18 17 16 15 14 13 12 11 10

D

R S T RC IN ENAR ENAS ENAT RESET OUTPUT ENA

1 3 5 10 2 4 6 8 7

VCC

R S T

RU RL SU SL TU TL GND OSCOUT

17 16 15 14 13 12 11

UU NU

S ENAS T

RCIN ENAR ENAS ENAT RST OUTEN IXDP630

BU OSC

ENAT OUTPUT ENA RESET GND

VCC U1 5 8 NC NC RL VCC GND Vo 4 3 2 1 VCC VCC C8 100n U9 1 3 5 6 9 8 4 3 2 1 1A 2A 3A 3Y 4A 4Y 14 2 13 12 4 11 10 18 U6 1 3 5 10 ENAR ENAS ENAT RESET OUTPUT ENA 2 4 6 8 7 R S T C6 100u C7 100n

C1 100n

HFBR 2521z VCC U2

B

VCC

1Y 6A 6Y 2Y 5A 5Y

VCC

GND

RU RL SU SL TU TL GND OSCOUT

17 16 15 14 13 12 11 1 3 5

UL NL
B

NC NC

RL VCC GND Vo

74HC04 C2 100n

RCIN ENAR ENAS ENAT RST OUTEN IXDP630

J1 BL 2 4 6 R2 4.12k 2 4 6 CON6A R3 7.32k R4 15k

HFBR 2521z VCC U3 5 8

A

R1 CON6A 4.12k J2 1 3 5

NC NC

RL VCC GND Vo

4 3 2 1

C3 100n

C10 100p PED2-840, Spring 2010 Title Extension interface for A/NPC Size A Date: Document Number Friday, May 21, 2010
2

HFBR 2521z

Rev 1.1 Sheet 1

1

of

Figure B.1: The circuit diagram of the extension interface board

77

Figure B.2: The PCB layout of the extension interface board

78

Appendix C

List of used laboratory instruments

The instruments which have been used for the laboratory test setup are given in Table C.1.

Instrument 300 V, 5 A DC Power Supply 24 V, 3 A DC Power Supply Load Resistor Load Inductor Single-Phase Power Analyser

Type Delta Elektronika GW-INSTEK GPS-4303 4 ASEA Education AB-5514 152-B ASEA Education Voltech PM 100

AAU inventory code GPL - PERES 79059 56061 29511 29512 35596

Table C.1: Laboratory instruments

79

Appendix D

Contents of the enclosed CD

The enclosed CD contains: Report - this folder contains the the report in PDF format References - this folder contains the articles used as reference in the report, when available in electronic format Simulations - this folder contains the simulation les Laboratory implementation - this folder contains the Simulink models used for generating the code for DSP implementation, the Code Composer projects and the thermal pictures of the inverter

81