NAND Flash Technology

kvkasin@kmitl.ac.th

Adapted from:
[1] Nonvolatile Memory Technologies with Emphasis on Flash edited by Joe E. Brewer, Wiley 2008 [2] M.Sanvido and et al., NAND Flash Memory and Its Role on Storage Arcthitectures, Arcthitectures , Proceeding of IEEE Vol. Vol.96 96, , No.11 No.11, , Nov 2008

NAND Flash
Topic
Overview Examples Multi Multi-level level Cell NAND Application with HDD and SSD

NAND Flash
Overview
NAND structure cell was invented by Fujio Masuoka of Tohoku University in 1987 Uses uniform FN tunneling g for both erasing g and programming Block-oriented memory
Easily programmed in a long page (order of 16kb) so the programming time per byte can be short Slow random access (read) due to serial connected resistance of cells and select transistor Suitable for applications that requires reading and programming blocks of data

NAND Flash-Recap
NAND Structured Cell
16 stacked cells serially connected between two select transistor Cell pitch defined by the polysilicon wiring lithography thus easier for scaling

NAND Flash
Architecture

Source: Peter Desnoyers Northeastern University

NAND Flash
Ex: 64 Mbit

NAND Flash-Recap
Erase

allow

inhibit

Block operation ( 8kbytes) results in negative VT Over-erasure is of no concern

NAND Flash
Program

0-program change to positive VT

0V

0V

1-program keep negative VT

Page operation All cells in the same page connected to the same WL are programmed simultaneously
Apply pp y 20 V to a selected cell and 10 V to non-selected cells (which share the same BL and must operate as a pass gate) Apply 0 V to BL for 0-programing ( change to positive VT) Apply A l 8 V to t BL for f 1-programing 1 i (k keep negative ti VT)

NAND Flash
Ex: Program Scheme

NAND Flash
Read

All other th cells ll except t th the selected l t d cell ll serve as pass devices If 0 0 is written the selected cell will not turn on

NAND Flash
Array Structure and Operations

Use staggered-row decoder instead of sub row decoder to ease the layout from narrow control gate pitch

NAND Flash
Conventional Structure

Each row decoder occupies length of a NAND strings

NAND Flash
Staggered Row Decoder

Each row decoder occupies length of two NAND g strings

NAND Flash
Self Self-booted Erase Inhibit Scheme
By floating CG and bi i P biasing P-well, ll th the capacitive coupling can raise CG to the same amount as Pwell.

NAND Flash
Block Erase

NAND Flash
Self Self-boosted Program Inhibit Scheme

NAND Flash
Capacitive Model for SelfSelf-boosted

NAND Flash
Program Page Operation

NAND Flash
Read Operation

NAND Flash
Program Disturb

VM should be set between 6 and 11 V.

NAND Flash
Read/Write and Verify Circuits

(Write CG4 and operate at Supply = 3V)

NAND Flash
Read/Write and Verify Circuits

(Read CG4 and operate at Supply = 3V)

NAND Flash
Verify Verify-read
1 1 1 1 0 1 0 0 1 0 1 0

NAND Flash
Page Programming Algorithm

Flash-MLC
Multi Multi-Level Cell
Pro Improve memory density without increasing the number of physical cells Lower cost per bit Solution for many mass storage applications Con Complex C l program algorithms l ith and d circuits i it Increase access time

Flash-MLC
Key Requirements
Placement:
Accurate control of the amount of charge stored, or placed, on the floating gate Precise control and timing of the voltages applied to the cells

Sensing:
Accurate measurement of the transistor characteristics to determine which charge level, or data bit, is stored Advanced analog to digital conversion

Retention:
Accurate charge storage, such that the charge level, or data bit, remains intact over time Leakage rate of less than one electron per day

NOR Flash MLC

Ex: Intels StrataFlash (ETOX NOR)

Threshold voltage of 1b/c and 2b/c Charge difference between states in 1 b/c is roughly 30,000 , electrons Distribution of 0.3 V corresponds to 3,000 electrons

NOR Flash MLC

Placement

Program timing control voltage and placement algorithm of StrataFlash

NOR Flash MLC

Sensing
Parallel sensing for fast decoding Use flash cell to generate reference for better tracking of process variation and operating condition

NAND Flash MLC

4-Level NAND

T Target t threshold th h ld voltage lt distribution di t ib ti

NAND Flash MLC

4-Level NAND : Page Read

The WSR scheme identifies one of f four f different diff t cell ll states t t by sequentially changing the WL voltage

NAND Flash MLC

4-Level NAND : Page Program

NAND Flash MLC

3-Level NAND

NAND Flash MLC

4-bit per Cell 2007
Spansion (AMD) announced MirrorBit Quad Technology Technology
Using silicon nitride instead of conductive floating gate Claimed as first industry 4-bit per cell Flash. Actually it is not a FG Flash, it is a NROM

2009
SanDisk initiated shipments of X4
Made by Toshiba 43 nm process technology Density 64Gb 7 MB/s write throughput

NAND Flash
Architecture and Performance

Source: Peter Desnoyers Northeastern University

NAND Flash
Typical Raw Throughputs
Type SLC 2LC Page 2KB (64B) 4KB (218B) Block 128KB 512KB Page/blc 64 128 Erase (mS/blc) 1 5-2 1.5-2 3 Program (S/p) 200-300 600-900 Write (MB/S) 5 1-6 9 5.1-6.9 3.8-5.4 Read (S/p) 25 50

Improvement :
Higher parallelism Longer page size (512B to 4KB) Setup standard interfaces :ONFI (Open Nand Flash Interface) NVMHCI ( NV Host Controller Interface) Interface),NVMHCI Interface),

[2]

Applications with HDD

Disk Caching Architecture

Hybrid HDD:
Add NAND flash as a disk cache to HDD Looks as if there is firmware on HDD Data are not split into two separate physical units Driver is needed on host side to manage NAND

Applications with HDD

Disk Caching Architecture
How Hybrid HDD work
Use part of flash to permanently store some data such as portion of boot data, initial portion of the hibernation file, f frequency used d random d d data t or applications li ti Use part of flash to temporary store incoming write data during g the time that HDD does not spin p to save p power

Advantages
provide a faster boot up and improve resume time from standby or hibernation reduce power consumption by rotating media, thus increasing battery life for mobile users improve launch time for frequently used applications improve the hard disk drive reliability, since the media can be spun down most of the time

Applications with HDD

Disk Caching Architecture
External caching (Turbo Mem)
Place NAND flash outside of HDD (on MTB or as a card) Split data into two physical l locations ti Require software and driver to manage NAND and HDD

Advantages
Fast boot, , fast resume Lower overall power consumption Improve HDD reliability

HDD System Diagram

Source: Debasis Baral Samsung USA

Solid-State Drive
Inside SSD

Source: Debasis Baral Samsung g USA

Solid-State Drive
SSD
Emerge as a replacement of HDD Currently use SLC NAND Flash Random read 10 10-50 50 times faster than traditional HDD Sequential read slower than HDD which achieves 100MB/s Four to ten times slower than HDD on write access Hardware is more robust than mechanical HDD Still some issues on endurance, data retention Power consumption depends on workload and design (average for 32/64 GB ~ 1-2 W)

NAND Flash
NAND vs HDD
Dollar per gigabyte

Ref. J.Unsworth, Gartnet, Dataquest Insight: Solid-State Drive Emerge i Select in S l Consumer C and d Enterprise E i Markets M k , Jan J 7, 2008

Limitations of Flash
Programming Voltage
Oxide thickness

Programming Speed
Slow in 10 s to 2ms

Endurance
Little improvement, so far ~106

Scaling

Limitation of Flash
Fundamental Scaling Limit
Must maintain oxide thickness to meet specification on retention time Attempt p to reduce p programming g g voltage g has not y yet successful Good news: it can be scaled for more technology generations before anticipated fundamental scaling issues become critical.

Limitation of Flash
Ideal Memory