UNIT 5 PERIPHERAL INTERFACING 5.

1 Introduction The microprocessor achieves its aim or applies its potential only when it is used for data processing or problem solving. The microprocessor has to accept the data through input devices process them using the Arithmetic and Logic Unit and displays the result in a human readable form. In other words we can say the microprocessor is to be interfaced with input and output devices to provide a computing environment. Frequently used input devices are Analog to Digital (A/D) converters and keyboard and the output devices are Light Emitting Diodes (LEDs), printers and monitors. These input and output devices are called peripherals. Since the speed at which the processor and the peripherals operate is different, suitable logic circuits (hardware) and writing instructions (software) should be used to enable the microprocessor to communicate with these peripherals. This is called interfacing. The logic circuits are called I/O ports or interfacing devices. In this unit you will study about the various programmable interfacing devices. This unit also discusses about the coprocessors that are used to enhance the performance of the microprocessors. 5.2 Learning Objectives To understand the various issues involved in interfacing peripherals to the microprocessor To study about the various modes and formats of I/O communication To learn the basics of programmable interfacing devices To study about the principles of matrix keyboard operation To study about the architecture and programming of Intel 8279 To learn the fundamentals and principles of Cathode Ray Tube To understand the architecture and programming of 8275 CRT controller To know the basics of coprocessors To study about the architecture of 8087 coprocessor

5.3 Basics of I/O Operation The microprocessor communicates with the peripherals in either of the two formats: asynchronous or synchronous. In synchronous mode the sender and the receiver are synchronized with the same clock. In asynchronous mode, the communication takes place at irregular intervals. The communication between the microprocessor and the peripherals is by and large asynchronous. The microprocessor receives or sends the data in either of the two modes: parallel and serial. In parallel mode entire word is transferred at a time.

Keyboards, data converters, LEDs etc are interfaced with the microprocessor in parallel mode. In serial mode, one bit is transferred at a time over a single line between the microprocessor and the peripheral. Teletypes (TTY), Cathode Ray Tube (CRT) terminals etc operate in serial mode. The microprocessor uses two types of mappings to identify the I/O devices. The microprocessor uses a common bus to transfer information between the processor and the memory as well as the I/O devices. The distinction between a memory transfer and an I/O transfer is made through the control signals. In such cases, the processor uses specialized instructions like IN and OUT for I/O transfers. Moreover the I/O devices and the memory use separate address spaces. Such a mapping is called I/O mapped I/O. The other type of mapping used by the microprocessors is Memory-Mapped I/O in which the I/O devices are treated alike memory. Same address space is shared between the memory and I/O devices and a common set of control signals are used. In this arrangement an address will refer to memory, if a memory device is connected there; it will refer to an I/O location, if an I/O device is connected there. In memory-mapped I/O no separate instructions are needed to differentiate between the memory and I/O devices. Data transfer between the microprocessor and the peripherals can be controlled either by the microprocessor or by the peripherals. Most peripherals are slower than the microprocessor and hence the conditions for the data transfer are to be set up. In this case, conditions are set up by the microprocessor and this type of transfer is called microprocessor controlled data transfer. If the peripheral is faster than the microprocessor then the conditions are set up by the peripheral and this type of data transfer is called peripheral controlled data transfer. Direct Memory Access Controller (DMAC) is a typical example for the second case. Have you understood? 1. What are the two formats for I/O operation? 2. What are the two modes of I/O operation? 3. What is the difference between parallel transfer and serial transfer? 4. What are the two types of mappings to identify the I/O devices? 5. When does the transfer between the microprocessor and the I/O devices are controlled by the I/O devices? 5.4 Programmable Interfacing Devices I/O functions can be done with the help of either simple integrated circuits or programmable devices. Latches and tri-state buffers are simple integrated circuits whose capabilities are limited. The major limitation of these devices is they are hard-wired and hence each device can perform only one function. On the other hand, a programmable interfacing device is capable of performing 2

various input/output functions according to the way in which we program the device. This type of device can be set up to perform specific functions by writing an instruction (or instructions) in its internal register. The internal register is called control register. The particular function the device will perform depends on the instruction we write into the control register. Hence it is possible to change the function at any time. In general, programmable interfacing devices are flexible, versatile and economical. They are widely used in microprocessor based products. A programmable device should include input and output registers, tri-state buffers, capability for bidirectional data flow, handshake and interrupt signals, control logic, chip select logic and interrupt control logic. Very often, the programmable devices include another register by name status register that monitors the data lines of the data register. A hypothetical programmable device is shown in figure 5.1.

Figure 5.1 Hypothetical programmable Interfacing Device Have you understood? 1. What are the advantages of programmable interfacing devices over buffers and latches? 2. Mention the major internal components of a programmable interfacing device. 5.5 Matrix Keyboard and Multiplexed Display Interface A matrix keyboard is a commonly used input device when more than eight keys are necessary. A matrix keyboard reduces the number of connections and hence 3

reduces the number of interfacing devices. The rows and columns do not have any connection and the connection occurs when a key is pressed. In other words, we can say that pressing a key shorts one row and column. The interfacing of a matrix keyboard requires one input port and one output port. Rows are connected to the output port and columns are connected to the input port. The schematic of the interface is as shown in figure 5.2.

Figure 5.2 Schematic of the Keyboard Interface In a matrix keyboard, the major task is to identify a key that is pressed and decode the key in terms of its binary value. This task can be accomplished through either software or hardware. The keyboard has 4 rows and 4 columns and hence the number of keys is 20. The 6 keys in a sequence represent data 0 to F in Hex. The rows are connected to port C and columns are connected to port B of the programmable peripheral interface 8255. Columns and rows make contact only when a key is pressed, otherwise they remain high. The major function required here is to identify the row and column of the pressed key. In terms of the hardware the intersection of the row and column of the pressed key should change from high state (default state) to low state. This is achieved by grounding all the rows by sending logic 0 through the output port. The interfacing arrangement checks the columns by reading the input port. If any key is pressed then a change is identified and the key press is decoded. The steps involved in this process are 1. Check whether all keys are open 2. Check a key closure

3. Identify the key 4. Find the binary key code for the key Various steps like detection, debouncing and encoding is shown in figure 5.3.

Figure 5.3 Reading of a keypress in a matrix keyboard The matrix keyboard routine is shown as follows with appropriate comments. KEYBOARD: PUSH B PUSH D XRA A MOV E,A OUT PORT C IN PORT B ANI 00001111B CPI 0FH JNZ KEYRELS CALL DEBOUNCE KEYCHECK: IN PORTB ANI 00001111B CPI 0FH JZ KEYCHECK CALL DBOUNCE RLC ; Save registers ; Clear accumulator ; Set up register E as binary code ; counter starting with code for key 0 ; Ground all rows ; Read columns ; Mask data lines D7-D4 ; Check for key release ; If previous key is not released, in a loop ; Wait for 10 ms when key is Released ; Read columns ; Mask data lines D7-D4 ; Is any key closed? ; If not, wait in a loop ; Wait for a key debounce ; Move zero in one of the rows

KEYRELS:

wait

NEXTROW:

MOV D,A row OUT PORTC IN PORTB ANI 00001111B MVI C,04H RAR JNC CODE INR E key DCR C JNZ NEXTCOLUMN next MOV A,D row DCR B columns, JNZ NEXTROW JMP KEYCHECK MOV A,E code

; Save data byte to ground next ; Ground one of the rows ; Read columns ; Mask D7-D4 ; Set column counter ; Move D0 in CY ; Key closure is found if zero is in CY ; Increment binary code for next ; No key closure found yet, ; decrement column counter ; Check for key closure in Column ; Load data byte to ground next ; No key closure found in ; get ready to ground next row ; No key closure yet, go back to ; ground the next row ; No key closure found, it was an ; error ; Load accumulator with binary

NEXTCOLUMN:

DBOUNCE:

LOOP:

from code counter POP D ; Retrieve registers POP B ; RET ; Return to main program ; This is a 10 ms delay routine, does not destroy any register ; content ; Input : None ; Output : None PUSH B ; Save registers PUSH PSW LXI B, COUNT ; Load 10ms delay count DCX B ; Repeat loop for delay MOV A,C ORA B ; Set zero flag if BC = 0 JNZ LOOP POP PSW POP B RET

A display and a keyboard are the two popular peripheral devices used in microprocessor based systems. A display and a keyboard are often combined to form a single peripheral device. If we use the scanned-display with the softwaredriven matrix keyboard, the keyboard subroutine must be coupled with the scanned display. In this case, the program must alternate between refreshing the display and checking a keyboard to find a key pressed. The time needed for the keyboard subroutine to check a key is relatively short and hence it does not affect the display. Another approach is to interface the keyboard using the interrupt technique. In the interrupt approach, the program continues to scan the display until the interrupt signal is received. Once the interrupt signal is received, the program checks the keyboard, processes the key and goes back to the scanning display. Have you understood? 1. What are the advantages of a matrix keyboard? 2. What are the steps required in identifying a key press in a matrix keyboard. 3. What is the necessity to debounce a key press? 4. Why a keyboard and a display are combined together to form a single I/O device? 5.6 Intel 8279 Keyboard/Display Controller Intel 8279 is the keyboard/display controller that is used to interface the keyboard and the display of a system to the microprocessor. The advantage of 8279 is that it is able to drive the signals for both the keyboard and display and hence it is possible for the microprocessor to concentrate in its routine tasks. The 8279 has two sections: keyboard and display. The 8279 chip provides a set of four scan lines and eight return lines for interfacing keyboards and a set of eight output lines for interfacing display. The keyboard section can interface to regular typewriter style keyboards or random toggle or thumb switches. The display section drives alphanumeric displays or a bank of indicator lights. Thus the CPU is relieved from scanning the keyboard or refreshing the display. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The keyboard portion interfaces an array of sensors or a strobed interface keyboard. Keyboard depressions can be 2-key lockout or N-key rollover. Keyboard entries are debounced and strobed in an 8-charcter FIFO. If more than 8 characters are entered, overrun status is set. Key entries set the interrupt output line to the CPU. The display portion provides a scanned display interface for LED, incandescent and other popular display technologies. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279 has 16*8 display RAM which can be organized into dual 16*4. The RAM can be loaded or interrogated by the CPU. Both right entry, calculator and left entry typewriter display formats are possible. Both read and write of the display RAM can be done with auto-increment of the display RAM address.

Since the 8279 is directly connected to the microprocessor, the microprocessor can program all operating modes of 8279. The various input modes of the 8279 are scanned keyboard, scanned sensor matrix and strobed input. In scanned keyboard mode, a key depression generates a 6-bit encoding of the key position. Position and shift control status are stored in the FIFO. Keys are automatically debounced with 2-key lockout or N-key rollover. In the scanned sensor matrix, key status is stored in RAM addressable by the microprocessor. Data on return lines during control line strobe is transferred to FIFO in strobed input. In one output mode, 8 or 16 character multiplexed displays are organized as dual 4-bit or single 8-bit and another output mode deals with right entry or left entry display formats. The keyboard interface part of 8279 continuously scans the keyboard to check if any key has been pressed. If it finds that a particular key has been pressed it sends the code of the corresponding key to the microprocessor. The microprocessor uses 8279 to send the result to the display device. In other words, we can say that 8279 controller transmits the data received from the CPU to the display device. The major advantage of using 8279 is that both of these activities are done without the intervention of the microprocessor. The keyboard can be interfaced to the microprocessor either in the polled mode or in the interrupt mode. In the polled mode the microprocessor reads an internal flag of 8279 to check if any key has been pressed. In the interrupt mode, the processor is requested service only if a key is pressed otherwise the microprocessor can proceed with its routine activities. 8279 permits a maximum of 64 keys to be present in the keyboard. This keyboard/display controller maintains an 8-byte First in First out Random Access Memory (FIFO RAM). If the FIFO contains a valid key entry, the CPU is interrupted (in interrupt mode) or the CPU checks the status (in polling mode) to read the entry. Once the CPU reads the key, the corresponding entry is deleted from the queue to generate space for the future keys that may be pressed. The 8279 normally provides a maximum of sixteen 7 segment display interface with CPU. It contains a 16-byte display RAM that can be used either as an integrated block of 16*8 bits or two 16*4 bit blocks of RAM. The data entry to RAM block is controlled by CPU using the command words of the 8279. Figure 5.4 shows the functional block diagram of 8279.

Figure 5.4 Block diagram of Intel 8279 The I/O control section controls the flow of data to/from the 8279. The data buffers interface the external bus of the system with internal bus of 8279. The I/O section is enabled only if D (Active Low) is low. The pins A0, Rd (Active Low), WR (Active Low) select the command, status or data read/write operations carried out by the microprocessor with 8279. Timing control registers store the keyboard and display modes and other operating conditions programmed by the processor. The registers are written with A0=1 and WR (Active Low) = 0. The timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies. The scan counter has two modes to scan the key matrix and refresh the display. In the encoded mode, the counter provides a binary count that is to be externally decoded to provide the scan lines for keyboard and display. In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3. The keyboard and the display both are in the same mode at a time. Another set of functional components is return buffers and keyboard debounce and control. These components scan for a key closure row wise. If it is detected, 9

the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce period, if the key continues to be detected the code of the key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status. One more block present in 8279 is the FIFO sensor RAM and Status Logic. FIFO is used to handle the quick pressings of the key. Each key code of the pressed key is entered in the order of the key, and in the meantime, read by the CPU, till the RAM becomes empty. The status logic generates an interrupt request after each FIFO read operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as the sensor RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a sensor changes its state, the IRQ line goes high to interrupt the CPU. The display address registers hold the address of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU. The 16-byte display RAM contains the 16-bytes of data to be displayed on the sixteen 7-segment displays in the encoded scan mode. 5.6.1 Signal description 8279 pins The pin diagram and signal description of 8279 is depicted in figure 5.5. The signal descriptions of each of the pins of 8279 are presented below in brief: DB0-DB7 These are bidirectional data bus lines. The data and command words to and from the CPU are transferred on these lines. CLK This is a clock input used to generate internal timings required by 8279.

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Figure 5.5 Pin diagram and Signal description of 8279 RESET This pin is used to reset 8279. A high on this line resets 8279. After resetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2 key lock out mode. The clock prescalar is set to 31. 11

CS (Active Low) Chip select. A low on this line enables 8279 for normal read or write operations. Otherwise this pin should remain high. A0 A high on the A0 line indicates the transfer of a command or status information. Alow on this line indicates the transfer of data. This is used to select one of the internal registers of 8279. RD (Active Low) WR (Active Low) READ/WRITE input pins enable the data buffers to receive or send data over the data bus IRQ The interrupt output line goes high when there is data in the FIFO sensor RAM. The interrupt line goes low with each FIFO RAM read operation. However, if the FIFO RAM further contains any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU Vss and Vcc these are the ground and power supply lines for the circuit SL0-SL3 Scan Lines These lines are used to scan the keyboard matrix and display digits. These lines can be programmed as encoded or decoded, using the mode control register RL0-RL7 Return Lines These are the input lines which are connected to one terminal of keys, while the other terminal of the keys are connected to the decoded scan lines. These are normally high, but pulled low when a key is pressed. SHIFT The status of the shift input line is stored along with each key code in FIFO in the scanned keyboard board. Till it is pulled low, with the key closure it is pulled up internally to keep it high. CNTL/STB-CONTROL/STROBED I/P mode In the keyboard mode, this line is used as a control input and stored in FIFO on a key closure. The line is a strobed line that enters the data into FIFO RAM in the strobed input mode. It has an internal pull up. The line is pulled down with the key closure. BD Blank Display This output pin is used to blank the display during digit switching or by a blanking comment. OUTA0 OUTA3 and OUTB0 OUTB3 These are the output ports for two 16*4 (or one 16*8) internal display refresh registers. The data from these lines is synchronized with the scan lines to scan the display and keyboard. The two four bit ports may also be used as one eight bit port. 5.6.2 Modes of Operation

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In scanned keyboard mode with 2 key lockout, when a key is pressed, a debounce logic comes into operation. During the next two scans, the other keys are checked for closure and if no other is pressed the first pressed key is identified. The key code of the identified key is entered into the FIFO with SHIFT and CNTL status, provided that FIFO is not full, that is it has at least one byte free. If the FIFO does not have any free byte, naturally the key data will not be entered and the error flag is set. If the FIFO has at least one byte free, the above code is entered into it and the 8279 generates an interrupt (on IRQ line) to the CPU to inform about the previous key closures. If another key is found closed during the subsequent two sacns, no entry to FIFO is made. If all the other keys are released before the first key, the key code is entered into FIFO. If the first pressed key is released before the others, the first will be ignored. A key code is entered to FIFO only once for each valid depression, independent of other keys pressed along with it, or released before it. If two keys are pressed within a debounce cycle (simultaneously) no key is recognized till one of them remains closed, and the other is released. The last key that remains depressed is considered as single valid key depression. In scanned keyboard with N-key rollover each key depression is treated independently. When a key is pressed the debounce circuit waits for two keyboard scans and then checks whether the key is still depressed. If it is still depressed, the code is entered in FIFO RAM. Any number of keys can be pressed simultaneously and recognized in the order, the keyboard scan recorded them. All the codes of such keys are entered into FIFO. Note that, in this mode, the first pressed key need not be released before the second is pressed. All the keys are sensed in the order of their depression, rather in the order the keyboard scan senses them, and independent of the order of their release. The scanned keyboard special error mode is valid only under the N-key rollover mode. This mode is programmed using end interrupt/error mode set command. If during a single debounce period (two keyboard scans) two keys are found pressed, this is considered a simultaneous depression and an error flag is set. This flag, if set, prevents for the writing in FIFO, but allows generation of further interrupts to the CPU for FIFO read. The error flag can be read by reading the FIFO status word. The error flag is set by sending normal clear command with CF = 1. In the sensor matrix mode, the debounce logic is inherited. The 8-byte FIFO RAM now acts as 8*8 bit memory matrix. The status of the sensor switch matrix is fed directly to sensor RAM matrix. Thus the sensor RAM bits contain the row wise and column wise status of the sensors in the sensor matrix. The IRQ line goes high, if any change in sensor value is detected at the end of a sensor matrix scan or the sensor RAM has a preivous entry to be read by the CPU. The IRQ line is reset by the first data read option, if AI = 0, otherwise, by issuing the end interrupt command. AI is a bit in read sensor RAM word.

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There are various options of data display. For example, the command number of characters can be 8 or 16, with each character organized as single 8-bit or dual 4-bit codes. Similarly, there are two display formats. The first one is known as left entry mode or type writer mode, since in a type writer the first character typed appears at the left most position, while the subsequent characters appear successively to the right of the first one. The other display format is known as the right entry mode, or calculator mode, since in a calculator the first character entered appears at the rightmost position and this character is shifted one position left when the next character is entered. Thus all the previously entered characters are shifted left by one position when a new character is entered. In the left entry mode, the data is entered from the left side of the display unit. Address 0 of the display RAM contains the leftmost display character and address 15 of the RAM contains the right most display character. It is just like writing in our note books, i.e., from left to right. If the 8279 is in auto increment mode, the display on the leftmost display and the sixteenth entry on the rightmost display. The seventeenth entry is again displayed at the leftmost display position. In the right entry mode, the first entry to be displayed is entered on the rightmost display. The next entry is also placed in the right most display but after the previous display is shifted left by one display position. The leftmost character is shifted out of that display at the seventeenth entry and is lost; it is pushed out of the display RAM. 5.6.3 Software Operation The following commands program the 8279 operating modes. The commands are sent on the data bus with CS (Active Low) and A0 high and are loaded to the 8279 on the rising edge of WR (Active Write). Keyboard/Display Mode Set

Where DD is the display mode and KKK is the keyboard mode. For display mode the various combinations are

For keyboard mode the various combinations are

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Programmable Clock The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescalar.

PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 3 to 31, decided by the bits of an internal prescalar PPPPP.

Read FIFO/Sensor RAM

X Dont Care AI Auto Increment flag AAA Address pointer to 8-bit FIFO RAM This command is used to set the 8279 for a read of the FIFO/Sensor RAM by first writing this command. In the scan keyboard mode, the Auto Increment flag and the RAM address bits (AAA) are irrelevant. The 8279 will automatically drive the data bus for each subsequent read in the same sequence in which the data first entered the FIFO. All subsequent reads will be from FIFO until another command is issued. In the sensor matrix mode, the bits AAA select one of the 8 rows of the RAM. If AI flag is set, each successive read will be from the subsequent row of the sensor RAM. Read Display RAM

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This command enables a programmer to read the display RAM data. The CPU writes this command word to 8279 to prepare it for display RAM read operation. AI is auto increment flag and AAAA, the 4-bit address, points to the 16-byte display RAM that is to be read. If AI=1, the address will be automatically, incremented after each read or write to the display RAM. The same address counter is used for reading and writing. Write Display RAM

The microprocessor uses this command to set up the 8279 for a write to the display RAM. The addressing and auto-increment functions are identical to those for the Read Display RAM. However, this command does not affect the source of subsequent data read. The CPU will read from whichever RAM (Display or FIFO/Sensor) which was last specified. Display Write inhibit/Blanking The Inhibit Write (IW) bits are used to mask the individual nibble in applications requiring separate 4-bit display ports. Once a nibble is masked by setting the corresponding IW bit to 1, the entry to display RAM does not affect the nibble even though it may change the unmasked nibble. The Blank display (BL) flags are used for blanking A and B nibbles. If the user wishes to blank the display, the BL flags are available for each nibble. Clear Display RAM

The CD2, CD1 and CD0 is a selectable blanking code to clear all the rows of the display RAM as given below. The characters A and B represent the output nibbles. 1 1 1 0 1 1 X 0 1 All zeros (X dont care) AB = 00 A1-A2 = 2 (0010) and B3-B0 = 00 (0000) All ones (AB=FF), i.e. clear RAM

End Interrupt/Error Mode Set

For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM. Otherwise, if a change in sensor value is detected, 16

IRQ goes high that inhibits writing in the sensor RAM. For N-key rollover mode, if the E bit is programmed to be 1, the 8279 operates in special error mode. Status Word, data Read and Data Write The status word contains the FIFO status, error and display unavailable signals. This word is read by the CPU when A0 is high and CS (Active Low) and RD (Active Low) are low. Data is read when A0, CS (Active Low) and RD(Active Low) are all low. The source of the data is specified by the READ FIFO or READ Display commands. The trailing edge of RD (Active Low) will cause the address of the RAM being read to be incremented if the Auto-Increment flag is set. FIFO reads always increment independent of AI. Data that is written with A0, CS (Active Low) and WR (Active Low) low is always written to the Display RAM. The address is specified by the latest Read Display or Write Display command. AutoIncrementing on the rising edge of WR (Active Low) occurs if AI is set by the latest display command. Typical configuration of an 8-bit processor, 8279 keyboard/display controller and the peripherals is shown in figure 5.6.

Figure 5.6 Interfacing Keyboard/Display to the Microprocessor Using Intel 8279 Have you understood? 17

1. What are the functional components of 8279 keyboard display controller? 2. Differentiate between 2-key lockout and N-key rollovers of the key depression. 3. How do the items in the queue are processed in polling and interrupt mode? 4. What is the information available in the status word of Intel 8279? 5. What is the difference between the typewriter mode and the calculator mode in display? 5.7 CRT Fundamentals Early computers communicated with the user with either indicator lamps or hard copy printers, but today, the primary output device is the electronic display. This is usually the CRT display, although other technologies are available. The CRT display uses the same technology as the television. It is the oldest and most popular display technology. Advantages of CRT are as follows. Low cost because of volume of production. Speed of updating and the retention of image is good. Colour display is available. Text and graphics display modes. Disadvantages of CRT are as follows. Large size and weight: Typical CRT displays are at least as deep as they are wide High voltage and power consumption. Also generate a lot of heat. CRT displays are glass vacuum tubes, and are therefore relatively fragile. The microprocessor interface is relatively complex.

Figure 5.7 shows the basic components of the CRT. The vacuum glass tube has at the end of its neck a heated filament. The electrons emitted are attracted towards the face of the screen by the electric field created by the high tension (HT) voltage applied between the cathode and the anode. For a 12-inch monitor, this voltage is about 1200V. The beam of electrons passes through the focusing and deflection electrostatic plates or coils along the way. The screen is coated with a thin phosphor layer which emits light when impacted by an electron at that point. The voltage applied to the control grid regulates the intensity of the electron beam. Since the brightness of the screen is dependent on the number of electrons hitting the phosphor, the display brightness is a function of the control voltage applied to the grid. For monochrome displays, the colour of the display is dependent on the type of phosphor used. The focusing anode, sometimes called an electrostatic lens, forms the emitted electrons into a thin circular beam (along the Z direction), so that the image created on the screen is a sharp well-defined

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spot. Magnetic focusing coils are common and can produce a narrower beam of electrons, that is, a sharper focus. The electron beam is aimed at a particular point on the screen by passing it through an electromagnetic field generated by the set of deflection coils in the yoke assembly. Two vertical deflection coils generate a field perpendicular in X direction of the electrons, allowing the electron beam to be scanned vertically. And two horizontal deflection coils do the same in the horizontal direction, thus enabling the beam to be positioned anywhere on the face of the tube. The CRT used in oscilloscopes which require faster, more precise and linear positioning of the beam uses electrostatic deflection plates in the tube rather than deflection coils.

Figure 5.7 Basic Components of the CRT CRT INTERFACE SIGNALS The circuit that interfaces the microprocessor buses to the CRT monitor is called the CRT controller. The three basic signals that must be provided to the CRT monitor are the video information, horizontal sync, and vertical sync. Each time horizontal sync is asserted, the electron beam retraces to the left edge of the screen. Each time vertical sync is asserted, the beam retraces to the top of the screen. These signals are usually provided by the CRT controller to synchronize the sweep oscillators in the monitor to the video information. For special applications, such as overlaying of computer generated video on television images, the CRT controller may accept the sync signals as inputs and synchronize the computer-generated video to them. The major interface signals are shown in figure 5.8. Some CRT monitors use signals called horizontal drive and vertical drive instead of the sync signals described above as shown in figure 5.8. These signals have the same period as sync signals but different pulse widths and polarity. 19

Figure 5.8 Major Interface Signals

Figure 5.9 Horizontal and Vertical sync Pulses

Horizontal sync: Retraces beam to the left edge of the screen. Horizontal oscillator: Saw-tooth signal that sweeps the beam horizontally across the screen. Vertical sync: Causes beam to retrace to the top of the screen. Vertical oscillator:Saw-tooth signal applied to the vertical deflection amplifier to move the beam down the screen. Video signal: Determines the intensity of the beam that will strike the screen. The signal is amplified and applied as the accelerating voltage in the CRT.

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Have you understood? 1. What are the advantages of CRT? 2. What are the major components of a CRT? 3. What is a CRT controller? 5.8 CRT CONTROLLER 8275 A CRT controller generates all the signals and coordinates the supporting activities for interfacing and controlling a CRT display with a microprocessor. Intels 8275 is a programmable CRT controller designed to interface raster scan displays with Intel microcomputer systems. This device refreshes the display besides storing the display data obtained from the CPU, in a display buffer (RAM). This also keeps a track of the current display position pointer (cursor) of the screen and offers different formats and styles to the display. 5.8.1 Internal Architecture of 8275 The internal architecture of 8275 is shown in figure 5.10. The functional description of each block is presented in this section.

Figure 5.10 Functional block diagram of 8275

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Data Bus Buffer: this tri-bidirectional 8-bit buffer interfaces the internal circuit of 8275 with the external system data bus, used to read or write the internal registers of 8275 or to send data to the display RAM. Read /Write Control Logic: the definitions of all the input signals accepted by this block will be explained later in the signal description section. This block decodes the lines A0, RD, WR and CS as shown below. CS 0 0 0 0 A0 0 0 1 1 RD 0 1 0 1 WR 1 0 1 0 Operations Read 8275 parameter Reg Write 8275 parameter Reg Read 8275 status Reg Write 8275 command Reg

Character Counter: This is a programmable counter used to determine the number of characters to be displayed per row and the length of the horizontal retrace interval. This driven by CCLK ( Character Clock) input that is derived from the dot clock. The dot clock decides for how much time a smallest dot on the screen which may form a character should be displayed on the screen. Line Counter: This is a programmable counter used to decide the number of rows to be displayed per frame and the length of vertical retrace interval. Light Pen Registers: These are the two registers that store the contents of the character counter and row counter whenever a rising edge is detected at the LPEN input pin. Raster Timing and Video Control: The raster timing circuit controls the timing of the HRTC and VRTC outputs. The video control circuit controls the generation of LA0-LA1 (Line Attribute), HGLT (High Light), RVV ( Reserve Video), LTEN (Light Enable), VSP (Video Suppress) and GPA0-GPA1 (General Purpose Attribute ) outputs. Row Buffers These two 80 characters row buffers are filled from the microcomputer system memory with the character codes to be displayed. While a buffer is displaying a row of characters, the other is being filled with the next row of characters to be displayed. FIFOs These two sixteen-character FIFOs in the 8275 are used to provide extra row buffer length in the transparent attribute mode. Buffer Input/Output Controllers

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These buffer input/output controllers decode the character information being placed in the row buffers. If the character is a character attribute, field attribute or a special code, the controllers decide the appropriate action. For example, end of screen-stop DMA special code will cause the input buffer controller to stop further DMA requests. Then a highlight attribute code causes the Buffer Output Controller to activate the HGLT output. 5.8.2 Signal descriptions of 8275 The pin configuration of 8275 is shown in figure 5.11. .

Figure 5.11 Pin diagram of 8275 The signal descriptions are as follows. Line Counter Outputs (LC0-LC1) These are outputs of the line counter, used to address the character generator for the current line position on the screen. DMA Request (DRQ) This is a DMA request output pin that is used to request for a service of one of the DMA channels of 8257 DMA controller, in DMA mode. DMA Acknowledge (DACK) This is an input pin that accepts the acknowledge signal from a DMA controller , to indicate to the CRT controller that it has been offered a DMA cycle as a response to its DMA request. Horizontal Retrace (HRTC) This output is active during the programmed horizontal retrace interval. During the active HRTC, the VSP output is high and the LTEN is low.

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Vertical Retrace (VRTC) This output signal is active during the programmed vertical retrace interval. During this period, the VSP output is high and the LTEN is low. Read Signal (RD) This is an input control signal used by the CPU to read the internal registers of 8275 Write Signal (WR) This is an input control signal used to write the data into the control registers of 8275 or to write it into the display RAM via row buffers. Light Pen (LPEN) This is an input control signal driven by a light pen system that informs the 8275 that a light pen signal has been detected. Data Bus (DB0 DB7) This is a bidirectional tri-state data bus that is used for read or write operations from / to the 8275 internal registers. Ground (GND) This is ground pin (supply return line) for the internal circuit of the 8275. A0 The input address line A0, if goes high, selects the C port or the command register and if goes low, selects the P port or the parameter register of 8275. Chip Select (CS) This is an active-low chip select input. If this is high, all the read or write operations to 8275 are disabled. Character Code Lines (CC0-CC6) These are output lines from the row buffers and are used for character selection from the character generator ROM. Character Clock (CCLK) This is a clock input that is driven by the dot/timing logic. This frequency decides the time duration allotted for display of a character. Interrupt Request (IRQ) This is an output pin used to generate an interrupt request to the CPU. Highlight (HLGT) This output signal is used to intensify the display at the particular positions on the screen as determined by the character attribute codes or the field attribute codes.

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General Purpose Attribute Codes (GPA0 GPA1) These are the outputs enabled by the general purpose field attribute codes. Video Suppression (VSP) This is an output signal used to blank the video signal to the CRT, which is active during the horizontal and vertical retrace intervals. - At the top and bottom lines of rows, if an underline is programmed to be at line number 8 or above. - When an end of row or an end of screen is detected. - When DMA overrun occurs. - At regular intervals (1/16 frame frequency for cursor, 1/32 frame frequency for character and field attribute) to create blinking displays if specified by the cursor character attribute or field attributes programmed. Reverse Video (RVV) This is an input pin used to indicate to the CRT circuit to reverse the video signal. This is active at the cursor positions, if a reverse video block cursor is programmed. This is also active at the positions specified by the field attribute codes. Light Enable (LTEN) This output is used to enable the video signal to CRT. This is active at the programmed underline cursor position and at the position specified by the attribute codes. Line Attribute Codes (LA0 LA1) These outputs have to be decoded externally by the dot/timing logic to generate the horizontal and vertical line combinations for the graphic displays as specified by the character attribute codes. Vcc This is a +5V power supply pin. 5.8.3 Schematic Interface The 8275 is programmable to a large number of different display formats. It provides raster timing, display row buffering, visual attribute decoding, cursor timing and light pen detection. The 8275 is designed to operate in a microprocessor system with an 8257 DMA controller and the standard character generator ROM for dot matrix decoding. The dot level timings are to be provided by an external circuitry. The interfacing schematic of 8275 with an 8257 DMA controller in a general microprocessor system is shown in figure 5.12.

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Figure 5.12 Interfacing Schematic of 8275 with an 8257 DMAC The 8275 picks up a row of characters to be displayed from the system memory and set them into an 80 character row buffer. The 8275 has two such buffers. When one buffer is being filled up with characters, the other buffer is on display. Thus the two row buffers are displayed one by one till the display frame is over. The number of characters per row and the number of rows per display frame are programmable. When one buffer is being and the other is already displayed, the 8275 requests a DMA cycle to fill the already displayed buffer. This continues till the complete display frame is over. Have you understood? 1. What are the functional components of Intel 8275? 2. What is the necessity to refresh the display? 3. What is the function of buffer input/output controllers of 8275? 5.9 Coprocessors The 8086/8 and 80186/8 are general purpose microprocessors, designed for a very wide range of applications. Typically, these applications need fast, efficient data movement and general purpose control instructions. Arithmetic on data values tends to be simple in these applications. The 8086/8 and 80186/8 fulfill these needs in a low cost, effective manner. However, some applications require extremely fast and complex math functions which are not provided by a general purpose processor. Such functions as square root, sine, cosine, and logarithms are not directly available in a general purpose processor. Software routines required to implement these functions tend to be slow and not very accurate. Integer data types and their arithmetic operations (i.e., add, subtract, multiply and divide) which are directly available on general purpose processors, still may not 26

meet the needs for accuracy, speed and ease of use. Providing fast, accurate, complex math can be quite complicated, requiring large areas of silicon on integrated circuits. A general data processor does not provide these features due to the extra cost burden that less complex general applications must take on. For such features, a special numeric data processor is required one which is easy to use and has a high level of support in hardware and software. The 8087 is a numeric data coprocessor which is capable of performing complex mathematical functions while the host processor (i.e. the main CPU) performs more general tasks. It supports the necessary data types and operations and allows use of all the current hardware and software support for the 8086/8 and 80186/8 microprocessors. The fact that the 8087 is a coprocessor means it is capable of operating in parallel with the host CPU, which greatly improves the processing power of the system. The 8087 can increase the performance of floating point calculations by 50 to 100 times, providing the performance and precision required for small business and graphics applications as well as scientific data processing. The 8087 numeric coprocessor adds 68 floating-point instructions and eight 80-bit floating-point registers to the basic 8086 programming architecture. All the numeric instructions and data types of the 8087 are used by the programmer in the same manner as the general data types and instructions of the host. The numeric data formats and arithmetic operations provided by the 8087 support the proposed IEEE Microprocessor Floating Point Standard. All of the proposed IEEE floating point standard algorithms, exception detection, exception handling, infinity arithmetic and rounding controls are implemented. The IEEE standard makes it easier to use floating point and helps to avoid common problems that are inherent to floating point.

Figure 5.13 Internal Architecture of 8087

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5.9.1 Architecture of 8087 The internal architecture of 8087 is shown in figure 5.13. The 8087 is divided into two sections internally namely the Control Unit (CU) and the Numeric Extension Unit (NEU). The numeric extension unit executes all the numeric processor instructions while the control unit receives, decodes instructions, reads and writes memory operands and executes the 8087 control instructions. These two units may work asynchronously with each other. The control unit is mainly responsible for establishing communication between the CPU and memory and also for coordinating the internal coprocessor execution. The CPU, while fetching the instructions from memory, monitors the data bus to check for the 8087 instructions. Meanwhile, the 8087 CU internally maintains a parallel queue, identical to the status queue of the main CPU. The CU automatically monitors the BHE/S7 line to detect the CPU type, i.e., 8086 or 8088 and accordingly adjusts the queue length. The 8087 further uses the QS0 and QS1 pins to identify the instructions fetched by the host CPU, which identifies the coprocessor instructions using the ESCAPE code bits in them. Once the CPU recognizes the ESCAPE code, it triggers the execution of the numeric processor instruction in 8087. While executing, the ESCAPE code identifies the coprocessor instructions that requires memory operand and also one that does not require any memory operands. If the instruction requires a memory operand to be fetched from memory, then the physical address of the operand is calculated using any one of the addressing modes allowed in 8086 and a dummy read cycle is initiated by the CPU. However, the CPU does not read the operand, rather 8087 reads it and proceeds for execution. If the coprocessor instruction does not require any memory operand, then it is directly executed. Whenever the 8087 is ready with the execution results the CU gets the control of the bus from 8086 and executes a write cycle to write the results in the memory at the pre-specified address. The Numeric Extension Unit (NEU) executes all the instructions including arithmetic, logical, transcendental, and data transfer instructions. The internal data bus is 84 bits wide including 68-bit fraction, 15-bit exponent and a sign bit. When the NEU begins the execution, it pulls up the BUSY signal. This BUSY signal is connected to the TEST input of 8086. If the BUSY signal of 8087 is asserted by it, the CPU recognizes that the instruction execution is not yet complete. This makes 8086 wait till the BUSY pin of 8087, i.e., the TEST input pin of 8086 goes low or, in other words, till the coprocessor executes the instruction completely. The microcode control unit generates the control signals required for execution of the instructions. 8087 contains a programmable shifter which is responsible for shifting the operands during the execution of instructions like FUML and FDIV. The data bus interface connects the internal data bus of 8087 with the CPU system data bus. 5.9.2 Signal Description of 8087

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The pin diagram of 8087 is shown in figure 5.14. This section deals with the different signals of 8087. AD0 AD15 These are the time multiplexed address/data lines. These lines carry addresses during T1 and data during T2,T3,Tw and T4 states. A0 is used, whenever the transfer is on lower byte (D0 D7) of data bus, to derive the chip select. These act as input lines for CPU driven bus cycles, and become input/output lines for the NDP initiated cycles.

A19/S6-A16/S3 These lines are the time multiplexed address/status lines. These function in a similar way to the corresponding pins of 8086. The S6, S4, and S3 are permanently high, while the S3 is permanently low. BHE/S7 During T1 the BHE/S7 pin is used to enable data on the higher byte of the 8086 data bus. During T2, T3, Tw and T4 this is a status line S7. this does not carry any significance in 8088 based systems. Ti, here, denotes the ith clock state of an instruction cycle. QS1, QS0 The queue status input signals QS1 and QS0 enable 8087 to keep track of the instruction prefetch queue status of the CPU, to maintain synchronism with it. The status of these lines can be decoded as given in the following table. Qs1 0 0 1 1 Qs0 0 1 0 1 Queue Status No operation First byte of opcode from queue Empty queue Subsequent byte from queue

These lines of 8087 are connected with the respective lines of 8086/8088. From these signals, 8087 comes to know the status of the internal instruction prefetch queue of 8086. INT The interrupt output is used by 8087 to indicate that an unmasked exception has been received during execution. This is usually handled by 8259A. BUSY

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This output signal, when high, indicates to the CPU that it is busy with the execution of an allotted instruction. This is usually connected to the TEST pin of 8086 or 8088. READY This input signal may be used to inform the coprocessor that the addressed device will complete the data transfer from its side and the bus is likely to be free for the next bus cycle. Usually this is synchronized by the clock generator 8284. RESET This input signal may be used to abandon the internal activities of the coprocessor and prepare it for further execution whenever asked by the main CPU. CLK The CLK input provides the basic timings for the processor operation. Vcc A +5V supply line is required for operation of the circuit GND A return line for the power supply. S2,S1, and S0 These can be either 8087 driven (output) or externally driven (input) by the CPU. If these are driven by 8087, they can be decoded as given in the following table. S2 0 1 1 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 Queue Status Unused Unused Memory read Memory write Passive

These lines become active during T4 (previous), i.e., prior to actual starting of the bus cycle and remain active till T1 or T2 (current). They are suspended during T3 for the next bus cycle. These are used by bus controllers to derive the read and write signals. These signals act as input signals if the CPU is executing a task. RQ/GT0 The request/Grant pin is used by the 8087 to gain control of the bus from the host 8086/8088 for operand transfers. It must be connected to one of the request/grant pins of the host. The request/grant sequence is described as follows:

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An active-low pulse of one clock duration is generated by 8087 for the host to inform it that it wants to gain control of the local bus either for itself or for other coprocessor connected to RQ/GT1 pin of 8087. the 8087 waits for the grant pulse from the host. when it is received, it either initiates a bus cycle if the request is for itself or else, it passes the grant pulse to RQ/GT1, if the request is for the other coprocessor. The 8087 will release the bus by sending one more pulse on RQ/GT0 line to the host either after completion of the last bus cycle initiated by it or as a response to a release pulse on the RQ/GT1 line issued by the other coprocessor. RQ/GT1 This bidirectional pin is used by the other bus maters to convey their need of the local bus access to 8087. This request is further conveyed to the host CPU. At the time of the request, if the 8087 does not have control of the bus, the request is passed on to the host CPU using RQ/GT0 pin. If however, the 8087 has control over the bus when it receives a valid request on RQ/GT1 pin; the 8087 sends a grant pulse during the following T4 or T1 clock, to the requesting master indicating that it has floated the bus. The requesting master gains the control of the bus till it needs. At the end, the requesting master issues an active low, one clock state wide pulse for 8087, to indicate that the task is over and 8087 may regain the control of the bus. The request grant pins may be used by the other bus masters like DMA controllers. 5.9.3 Register Set The 8087 has a set of eight 80-bit registers. Each of the eight data registers in the 8087s register stack is 80 bits and is divided into fields corresponding to the 8087s temporary real data type. At a given point in time the TOP field in the control word identifies the current top-of-stack register. A push operation decrements TOP by 1 and loads a value into the new top register. A pop operation stores the value from the current top register and then increments TOP by 1. Like CPU stacks in memory, the 8087 register stack grows down toward lower-addressed registers. The status word reflects the overall state of 8087. It is stored in the memory and then inspected by the CPU code. The status word is a 16-bit register divided into fields as shown in figure 5.14.

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Figure 5.14 Status Word The busy bit (bit 15) indicates whether the NEU is either executing an instruction or has an interrupt request pending (B=1), or is idle (B=0). Several instructions which store and manipulate the status word are executed exclusively by the control unit, and these do not set the busy bit themselves. The tag word makes the content of each register as shown in figure 5.15. The principal function of the tag word is to optimize the 8087s performance. The tag word can be used, however, to interpret the contents of 8087 registers.

Figure 5.15 Tag Word The instruction and data pointers as shown in figure 5.16 are provided for userwritten error handlers. Whenever the 8087 executes a math instruction, the control unit saves the instruction address, the operand address (if present) and the instruction opcode. 8087 instructions can store this data into memory.

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Figure 5.16 Instruction and Data Pointer The control word register of 8087 allows the programmer to select the required processing options out of available ones. In other words, the 16-bit control word register is used to control the operation of the 8087. The bits B0-B5 are used for masking the different exceptions. An exception may be masked by setting the respective bit in the control word register. The M bit is a common interrupt mask for all the interrupts. If it is set, all the exceptions generated will be masked and the execution may continue. The precision control and rounding control bits control the precision option and rounding option as shown in figure 5.17. The infinity result control bit IC provides control over the number size on both sides, i.e., either + or -.

Figure 5.17 Control Word 33

The 8087, while executing an instruction, may generate six different options. Any of these exceptions, if generated, causes an interrupt to the CPU provided it is not masked. The CPU will respond if the interrupt flag of the CPU is set. If the exceptions are masked the 8087 continues the execution, independent of the responses from the CPU. If any of the six exceptions is masked and it is detected, the 8087 modifies the corresponding bit in the status register, and executes an on-chip exception handler that allows it to continue with the execution. Invalid operation, overflow, underflow, zero divide, denormalized operand and inexact result are the six different options.

Figure 5.18 Communication between Microprocessor and Coprocessor The communication between 8087 and the host CPU have already been discussed. In this section, we study the physical interconnections of 8087 with 8086/8088 and 80186/80188. 8087 can be connected with any of these CPUs only in their maximum mode of operation, i.e., only when the MN/MX pin of the CPU is grounded. In maximum mode, all the control signals are derived using a separate chip known as a bus controller. The 8288 is 8086/88 compatible bus controller while 82188 is 80186/80188 compatible bus controller. The communication between the microprocessor and coprocessor is shown in figure 5.18. The BUSY pin of 8087 is connected with the TEST pin of the used CPU. The QS0 and QS1 lines may be directly connected to the corresponding pins in case of 8086/8088 based systems. However, in case of 80186/80188 systems these QS0 and QS1 lines are passed to the CPU through the bus controller. In case of 8086/8088 based systems the RQ/GT0 of 8087 may be connected to RQ/GT1 of the 8086/8088. The clock pin of 8087 may be connected with the CPU 8086/8088 clock input. The interrupt output of 8087 is routed to 8086/8088 via programmable interrupt controller. The pins AD0-AD15, BHE/S7, RESET, A19/S6-A16/S3 are connected to the corresponding pins of 8086/8088. in case of 80186/80188 systems the RQ/GT lines of 8087 are connected with the corresponding RQ/GT lines of 82188.

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Have you understood? 1. 2. 3. 4. What is the necessity of a coprocessor? What is the coprocessor for 8086/8088 microprocessor? What are the two functional units of 8087 numeric data coprocessor? How the bus is properly shared between the microprocessor and the coprocessor? 5. What is the purpose of the tagword in 8087? Summary 1. I/O functions can be done with the help of either simple integrated circuits or programmable devices. Latches and tri-state buffers are simple integrated circuits whose capabilities are limited. 2. On the other hand, a programmable interfacing device is capable of performing various input/output functions according to the way in which we program the device. 3. A matrix keyboard is a commonly used input device when more than eight keys are necessary. A matrix keyboard reduces the number of connections and hence reduces the number of interfacing devices. 4. The rows and columns of a matrix keyboard do not have any connection and the connection occurs when a key is pressed. In other words, we can say that pressing a key shorts one row and column. 5. In a matrix keyboard, the major task is to identify a key that is pressed and decode the key in terms of its binary value. This task can be accomplished through either software or hardware. 6. Intel 8279 is the keyboard/display controller that is used to interface the keyboard and the display of a system to the microprocessor. The advantage of 8279 is that it is able to drive the signals for both the keyboard and display and hence it is possible for the microprocessor to concentrate in its routine tasks. 7. When a keyboard is interfaced through Intel 8279, the keys are automatically debounced and the keyboard can operate in two different modes: Two key lockout or N-key rollover. 8. In the two key lockout mode, if two keys are pressed almost simultaneously, only the first key is recognized. In the N-key rollover mode, simultaneous keys are recognized and their codes are stored in the internal buffer. 9. Early computers communicated with the user with either indicator lamps or hard copy printers, but today, the primary output device is the electronic display. This is usually the CRT display, although other technologies are available. The CRT display uses the same technology as the television. 10. A CRT controller generates all the signals and coordinates the supporting activities for interfacing and controlling a CRT display with a

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microprocessor. Intels 8275 is a programmable CRT controller designed to interface raster scan displays with Intel microcomputer systems. 11. Various functional components of Intel 8275 are data bus buffer, read/write control logic, character count, line counter, light pen registers, raster timing and video control, row buffers, FIFOs and buffer I/O controllers. 12. The 8087 is a numeric data coprocessor which is capable of performing complex mathematical functions while the host processor (i.e. the main CPU) performs more general tasks. 13. The 8087 is divided into two sections internally namely the Control Unit (CU) and the Numeric Extension Unit (NEU). The NEU executes all the numeric processor instructions while the CU receives, decodes instructions, reads and writes memory operands and executes the 8087 control instructions. In this unit you have learnt about the interfacing of peripherals to the processor using programmable interfacing devices. Programmable interfacing devices provide a number of advantages over handling the peripherals through software routines. You may further explore in this area in terms of the latest processors, their features, embedded systems and other digital systems that are arriving the market. Exercises 1. What do the initialization commands specify in 8279 keyboard/display controller? 2. In a key monitor program, register E is used to save 4-bit codes of two data keys. Write a subroutine to insert a new 4-bit key code that is available in the accumulator; the new code must be inserted as a loworder nibble, and the most significant nibble in register E must be discarded. 3. In a monitor program, register BC is used to save a 16 bit memory address. Write instructions to insert a 4-bit code of a new key in the BC register as a least significant nibble. 4. Check whether the following statements are true or false. a. Serial data communication can not be implemented using the memory mapped I/O. b. In a serial transmission from the MPU to a peripheral, bit D0 is transmitted first after the start bit. c. In a system with the even parity check, the letter M is transmitted with the code 4CH. d. In a system with the odd parity check, the letter A is transmitted with the code C1H. e. ASCII is an 8-bit binary code that represents 256 different characters.

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5. When the 8279 detects a key closure, the IRQ signal interrupts the 8085, using RST 5.5. The interrupt service routine sends the command word to read from the keyboard, reads the character data from the keyboard, and stores it in the input buffer of the systems R/W memory. Write down the instructions for initialization and interrupt routine to read the keyboard. Answers 1. The initialization commands specify left or right entry and key rollover, clock frequency prescaler, starting address and incrementing mode of the FIFO RAM, RAM address to read and write data and incrementing mode, blanking format. 2. SHIFT: PUSH PSW MOV A,E ADD A ADD A ADD A ADD A MOV E,A POP PSW ANI 0FH ORA E MOV E,A RET 3. INSERT: PUSH H MOV H,B MOV L,C DAD H DAD H DAD H DAD H ANI 0FH ORA L MOV B,H MOV C,A POP H RET 4. a. F b. T c. F d. T e. F 6. Initialization MVI A,00H STA 1900H

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Interrupt Routine to Read Keyboard PUSH H PUSH PSW LXI H,1900H MVI M,40H DCR H MOV A,M ANI 3FH STA IBUFF POP PSW POP H RET

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