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----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 12:48:45 04/28/2010 -- Design Name: -- Module Name: fulladr - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladr is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; SUM : out STD_LOGIC; Co : out STD_LOGIC); end fulladr; architecture Behavioral of fulladr is begin SUM <= (A XOR B) XOR Cin; Co <= (A AND B) OR (B AND Cin) OR (Cin AND A); end Behavioral;
TESTBENCH
// Engineer: // // Create Date: 12:53:21 04/28/2010 // Design Name: fulladr // Module Name: E:/xylintest/FULADD/fuladdtbc.v // Project Name: FULADD // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: fulladr // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////
// Outputs wire SUM; wire Co; // Instantiate the Unit Under Test (UUT) fulladr uut ( .A(A), .B(B), .Cin(Cin), .SUM(SUM), .Co(Co) );
initial begin // Initialize Inputs A = 0; B = 0; Cin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here A = 0; B = 0; Cin = 1; // Wait 100 ns for global reset to finish #100;
A = 0; B = 1; Cin = 0; // Wait 100 ns for global reset to finish #100; A = 0; B = 1; Cin = 1; // Wait 100 ns for global reset to finish #100; A = 1; B = 0; Cin = 0;
// Wait 100 ns for global reset to finish #100; A = 1; B = 0; Cin = 1; // Wait 100 ns for global reset to finish #100; A = 1; B = 1; Cin = 0; // Wait 100 ns for global reset to finish
#100; A = 1; B = 1; Cin = 1; // Wait 100 ns for global reset to finish #100; end endmodule
Waveform
-- Engineer: --- Create Date: 09:58:56 04/28/2010 -- Design Name: -- Module Name: haadd - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity haadd is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Ca : out STD_LOGIC; Sum : out STD_LOGIC); end haadd; architecture Behavioral of haadd is begin Sum <= A Xor B; Ca <= A and B; end Behavioral;
TEST BENCH `timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 10:13:47 04/28/2010 // Design Name: haadd // Module Name: E:/xylintest/halfaddr/haaddtbc.v // Project Name: halfaddr // Target Device: // Tool versions: // Description:
// // Verilog Test Fixture created by ISE for module: haadd // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////
module haaddtbc; // Inputs reg A; reg B; // Outputs wire Ca; wire Sum; // Instantiate the Unit Under Test (UUT) haadd uut ( .A(A), .B(B), .Ca(Ca), .Sum(Sum) );
initial begin // Initialize Inputs A = 0; B = 0; // Wait 100 ns for global reset to finish #50; A = 0; B = 1; // Wait 100 ns for global reset to finish #50; A = 1; B = 0; // Wait 100 ns for global reset to finish #50; A = 1; B = 1; // Wait 100 ns for global reset to finish #50; // Add stimulus here end endmodule
Waveform:
Boundary Scan
UCF NET "A" LOC = L13; NET "B" LOC = L14; NET "Sum" LOC = F12; NET "Ca" LOC = E12;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity mux2 is Port ( s : in STD_LOGIC; d : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC); end mux2;
architecture Behavioral of mux2 is begin --process(s,d) --begin -- if s='0' then Y<=d(0); -- else y<=d(1); -- end if; --end process;
y<=d(conv_integer(s));
--y<= d(1) when s='1' else d(0); end Behavioral; architecture Behavioral of multiplexer is
begin
process(s,i) begin if(i='0') then y<=s(0); else y<=s(1); end if; end process; end Behavioral;
// Design Name: multiplexer // Module Name: F:/VHDL_FPGA/classwork/twoonemux/multiplexer_vtf.v // Project Name: twoonemux // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: multiplexer // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////
module multiplexer_vtf;
// Outputs wire y;
// Instantiate the Unit Under Test (UUT) multiplexer uut ( .s(s), .y(y), .i(i) );
end
endmodule
WAVE FORM
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity fa2 is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; sum : out STD_LOGIC; cry : out STD_LOGIC); end fa2;
c : out STD_LOGIC);
end component;
signal s1,c1,c2:std_logic;
end Behavioral;
VHDL TESTBENCH: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
COMPONENT fa2 PORT( x : IN std_logic; y : IN std_logic; z : IN std_logic; sum : OUT std_logic; cry : OUT std_logic ); END COMPONENT;
--Inputs signal x : std_logic := '0'; signal y : std_logic := '0'; signal z : std_logic := '0';
--Outputs signal sum : std_logic; signal cry : std_logic; constant clk_period:time:=100ns; BEGIN
-- Instantiate the Unit Under Test (UUT) uut: fa2 PORT MAP ( x => x,
-- No clocks detected in port list. Replace <clock> below with -- appropriate port name
-- <clock>_process :process -- begin ------ end process; <clock> <= '0'; wait for <clock>_period/2; <clock> <= '1'; wait for <clock>_period/2;
x<= not x after 2*clk_period; y<= not y after clk_period; z<= not z after clk_period/2; -- Stimulus process stim_proc: process begin
END;
WAVE FORM:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity decoder2to4 is Port ( A : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC_VECTOR (3 downto 0); EN : in STD_LOGIC); end decoder2to4;
architecture Behavioral of decoder2to4 is signal w:std_logic_vector(2 downto 0); --signal s:integer range 0 to 256; begin w<= EN & A;
--end if; --end process; WITH w SELECT Y<= "0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", "ZZZZ" WHEN OTHERS ;
--process(A,EN) --begin
--if EN='0' then Y<=(Y'range=>'Z'); -- elsif (A="00") then Y<="0001"; -- elsif (A="01") then Y<="0010"; -- elsif (A="10") then Y<="0100"; -- else Y<="1000";
-- case A is ----when "00"=>Y<="0001"; when "01"=>Y<="0010"; when "10"=>Y<="0100"; when others =>Y<="1000";
////////////////////////////////////////////////////////////////////////////////
module decoder2to4_test_veri;
// Instantiate the Unit Under Test (UUT) decoder2to4 uut ( .A(A), .Y(Y), .EN(EN) );
initial begin // Initialize Inputs A = 00; EN = 0; // Wait 100 ns for global reset to finish #100;
A = 00; EN = 1;
A = 01; EN = 1;
A = 10; EN = 1;
A = 11; EN = 1;
// Wait 100 ns for global reset to finish #100; // Add stimulus here end
endmodule
VHDL TESTBENCH LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
ENTITY decoder2to4_test_vhd IS END decoder2to4_test_vhd; ARCHITECTURE behavior OF decoder2to4_test_vhd IS -- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder2to4 PORT( A : IN std_logic_vector(1 downto 0); Y : OUT std_logic_vector(3 downto 0); EN : IN std_logic ); END COMPONENT; --Inputs signal A : std_logic_vector(1 downto 0) := (others => '0'); signal EN : std_logic := '0';
--Outputs
BEGIN -- Instantiate the Unit Under Test (UUT) uut: decoder2to4 PORT MAP ( A => A, Y => Y, EN => EN );
-- No clocks detected in port list. Replace <clock> below with -- appropriate port name -- constant <clock>_period := 1ns; -- <clock>_process :process -- begin ------ end process; -<clock> <= '0'; wait for <clock>_period/2; <clock> <= '1'; wait for <clock>_period/2;
A(0)<= not A(0) after 50ns; A(1)<= not A(1) after 100ns;
-- Stimulus process stim_proc: process begin -- hold reset state for 100ms. EN<='0'; wait for 100ns;
END;
Waveform:
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
signal ff:std_logic;
begin
process(clk,rst)
JK:=J & k; case JK is when "01"=>ff<='0'; when "10"=>ff<='1'; when "11"=>ff<=not ff; when others => ff<=ff; end case;
end if;
end process;
--if rst='0' then ff<='0'; -- elsif falling_edge(clk) then ----end if; --end process; --Q<=ff; --QBAR<=not ff; end Behavioral; Q<=(J and QBAR) or ((not k) and Q);
COMPONENT JKFF1 PORT( rst : IN std_logic; clk : IN std_logic; J : IN std_logic; K : IN std_logic; Q : INOUT std_logic; QBAR : INOUT std_logic ); END COMPONENT;
--Inputs signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal J : std_logic := '0'; signal K : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT) uut: JKFF1 PORT MAP ( rst => rst, clk => clk, J => J, K => K, Q => Q, QBAR => QBAR );
-- Clock process definitions -- clk_process :process -- begin ------ end process; clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2;
begin
rst<='1'; J<='1';
END;
// Create Date: 15:58:18 06/08/2010 // Design Name: JKFF1 // Module Name: E:/xilinxprograms/comb/JKFF1_tset_veri.v // Project Name: comb // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: JKFF1 // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////
module JKFF1_tset_veri;
// Instantiate the Unit Under Test (UUT) JKFF1 uut ( .rst(rst), .clk(clk), .J(J), .K(K), .Q(Q), .QBAR(QBAR) ); initial begin // Initialize Inputs clk = 0; forever #10 clk=~clk;
end
rst=0; J=0;
K=0; #50;
end
endmodule
Waveform:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity Dff1 is Port ( D : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC); end Dff1;
end Behavioral;
//////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:12:42 08/03/2010 // Design Name: Dff1 // Module Name: E:/xilinxprograms/comb/dff_test_veri.v // Project Name: comb // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: Dff1 // // Dependencies: // // Revision:
module dff_test_veri;
// Outputs wire q;
// Instantiate the Unit Under Test (UUT) Dff1 uut ( .D(D), .clk(clk), .rst(rst), .q(q) );
end
D=1; rst=1;
#100;
D=1; rst=1;
end
endmodule
-- Create Date: 14:19:07 08/03/2010 -- Design Name: -- Module Name: E:/xilinxprograms/comb/dff_test_vhd.vhd -- Project Name: comb -- Target Device: -- Tool versions: -- Description: --- VHDL Test Bench Created by ISE for module: Dff1 --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL;
COMPONENT Dff1 PORT( D : IN std_logic; clk : IN std_logic; rst : IN std_logic; q : OUT std_logic ); END COMPONENT;
--Inputs signal D : std_logic := '0'; signal clk : std_logic := '0'; signal rst : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT) uut: Dff1 PORT MAP ( D => D, clk => clk, rst => rst, q => q );
-- Clock process definitions -- clk_process :process -- begin ----clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2;
-- end process; -clk<= not clk after clk_period/2; -- Stimulus process stim_proc: process
begin
rst<='1'; D<='1';
END;
Waveform:
Design block):
library IEEE;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
architecture Behavioral of SIPO1 is signal state:std_logic_vector(n-1 downto 0); begin process (rst,clk)
begin
if rst='0' then state<=(others=>'0'); elsif rising_edge(clk) then if R_L='0' then state<=si & state(n-1 downto 1); else
state<=state(n-2 downto 0) & si; end if; end if; end process;
q<=state;
end Behavioral;
//////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:00:30 08/03/2010 // Design Name: SIPO1 // Module Name: E:/xilinxprograms/memory/SIPO_test_veri.v // Project Name: memory // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: SIPO1
module SIPO_test_veri;
// Instantiate the Unit Under Test (UUT) SIPO1 uut ( .rst(rst), .clk(clk), .si(si),
.R_L(R_L), .q(q) );
end
rst = 1;
si = 0; R_L = 0; #50;
rst = 1;
si = 0; R_L = 0; #50;
end
endmodule
Waveforms:
architecture counter_example_a of counter_example is -signal cnt_led : std_logic_vector(3 downto 0):=(others=>'0'); begin process(RESET, CLK) is begin
if RESET = '0' then cnt_led <=(others=>'0'); elsif falling_edge(CLK) then if LOAD = '1' then cnt_led <= "0101"; -elsif (cnt_led<"1001") then cnt_led <=cnt_led + "0001";
cnt_led <=(others=>'0');
-- Module Name: E:/xilinxprograms/counter1/counter_test1_vhd.vhd -- Project Name: counter -- Target Device: -- Tool versions: -- Description: --- VHDL Test Bench Created by ISE for module: counter_example --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
COMPONENT counter_example PORT( CLK : IN std_logic; RESET : IN std_logic; LOAD : IN std_logic; Q : OUT std_logic_vector(3 downto 0) ); END COMPONENT;
--Inputs signal CLK : std_logic := '0'; signal RESET : std_logic := '0'; signal LOAD : std_logic := '0';
-- Instantiate the Unit Under Test (UUT) uut: counter_example PORT MAP ( CLK => CLK, RESET => RESET, LOAD => LOAD, Q => Q );
-- No clocks detected in port list. Replace <clock> below with -- appropriate port name
-- <clock>_process :process -- begin ------ end process; -clk<=not clk after clk_period/2; <clock> <= '0'; wait for <clock>_period/2; <clock> <= '1'; wait for <clock>_period/2;
-- Stimulus process stim_proc: process begin wait for 50ns; RESET <= '0'; LOAD <= '0'; wait for clk_period * 2;
RESET <= '1'; LOAD <= '0'; wait for clk_period * 20;
RESET <= '1'; LOAD <= '0'; wait for clk_period * 10;
wait;
end process;
END;
Waveform:
-- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity add_sub4bit is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); mode : in STD_LOGIC; sum_diff : out STD_LOGIC_VECTOR (3 downto 0); carry_borw : out STD_LOGIC);
end add_sub4bit;
component fa1
Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; sum : out STD_LOGIC; cry : out STD_LOGIC); end component;
component xor_2
end component;
signal cout :std_logic_vector(4 downto 0); signal bbar :std_logic_vector(3 downto 0);
begin
cout(0)<=mode;
l2:for i in 3 downto 0 generate x4:fa1 port map(a(i), bbar(i), cout(i), sum_diff(i),cout(i+1)); end generate l2;
carry_borw<=cout(4);
end Behavioral;
// Design Name: add_sub4bit // Module Name: E:/xilinxprograms/adder_sub/add_sub4bit_test_veri.v // Project Name: adder_sub // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: add_sub4bit // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////
module add_sub4bit_test_veri;
// Outputs
// Instantiate the Unit Under Test (UUT) add_sub4bit uut ( .a(a), .b(b), .mode(mode), .sum_diff(sum_diff), .carry_borw(carry_borw) );
end
endmodule
Waveform: