LAB 1: INTRODUCTION TO FPGA HARDWARE, CONTROL DESIGN AND SIMULATION

ME475

OBJECTIVES
1. 2. 3. SimulatethesystemtimeresponseusingLabVIEWsoftware. DevelopanunderstandingoftheNIcRIOandFPGAhardware. WriteasimpleLabVIEWFPGAprogram.

INTRODUCTION
Throughout the semester LabVIEW will be used to control and simulate dynamic systems. This lab provides an introduction to the control and simulation tools available in LabVIEW. After a brief introduction to the simulation approachyouwillimplementasimulationoftheservotableyoustudiedinthepreviousweek. Engineering control projects often need to perform simple, but highspeed computation. Software solutions are too slow for such applications, or have unreliable timing. Budget or scale constraints can prevent the use of faster, custom designed integrated circuits (ICs). In this case Field Programmable Gate Arrays (FPGAs) provide a solution in the form of a userprogrammable integrated circuit that performs nearly as well as a production made ICatafractionofthecost. LabVIEW provides software tools that can be used to directly integrate FPGAs into higherlevel software applications. In this lab the use of FPGA hardware with LabVIEW is introduced. For additional information about usingLabVIEW,pleasecheckoutoneofthemanytutorialsavailableonline.

BACKGROUND LABVIEW SIMULATION

LabVIEW can be used to simulate a dynamic system in block diagram form. This section will describe how to simulatetheblockdiagraminLabVIEW. Considerthefollowingsecondorderlinear,constantcoefficientdifferentialequation:

t by t cy t u t ,given y 0 , y 0 ay

whichhasaninputoutputtransferfunctionof
Y s U s 1 as bs c
2

ThistransferfunctioncanberepresentedinblockdiagramformasshowninFigure1.

Figure1:Blockdiagramformofasecondordertransferfunction.

To simulate this system first create a new VI in LabVIEW by clicking FileNew VI. Then follow the steps below to complete the simulation of the block diagram in Figure 1 while using the parameter values a 1.25 , b 1.25 , and c 3.75 . 1. In the Block Diagram window right click and hover over the Control Design & Simulation menu and thenclickonthethumbtackintheupperleftcornertokeepthemenuopenasshowninFigure2. 2. ClickontheSimulationbutton,andthenontheControlandSimulationLoop.Withthistoolselected drawaboxintheBlockDiagramwindowtocreateanewControlandSimulationstructureasshown inFigure3. Click the Signal Generation button and then select the Step Signal tool. Click inside the simulation looptoplacethestepsignalintheblockdiagram. Return to the Simulation menu by clicking the up arrow, and then press the Continuous Linear SystemsbuttonandplacetwoIntegratorsintheblockdiagram.

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 Figure2:OpentheControlDesign&Simulationmenu.

Figure3:AblankControlandSimulationLoophasbeencreated.

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ReturntotheSimulationmenuandthenentertheGraphUtilitiesmenu.PlaceaSimTimeWaveform iconintheblockdiagram. Return to the Simulation menu and then enter the Signal Arithmetic menu. Place three Gain icons andaSummationiconintheblockdiagram.TheblockdiagramshouldnowlooklikeFigure4. Double click on the summation icon and increase the number of terminals to four: one +, two, and one =. Right click on the lower gain terms and select Reverse Terminals. Then connect the terminals asnecessarybyhoveringovertheiconsandclickingtoinsertwires. EachgainissetbyrightclickingitsiconandselectingConfiguration. The simulation can now be executed by clicking the rightpointing arrow button on the Front Panel. The simulation result should appear as shown in Figure 5 (you may have to scroll the front panel to findtheplot.)

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 Figure4:Blockdiagramwithmaincomponentsinplace.

Figure5:Completesimulationresult.

FPGA BACKGROUND
TheabovesectiontellsushowtodosimulationofblockdiagramsusingLabview.However,Inrealapplications,we needtodealwithphysicalsystemsratherthanvirtualblockdiagrams.Inthiscase,weneedarealtimecontroller, which takes in the measurement signal from the physical systems, computes the control law and sends out the controlcommandtothephysicalsystemsinrealtime.

The National Instruments cRIO is a hardware chassis that can be used to do this job. It includes a computer controller running the LabVIEW realtime operating system, and an FPGA that interfaces with the realtime computer to control various modules installed in the chassis. The chassis communicates with a host computer via TCP/IP.ThisarrangementisillustratedinFigure6.Specifically,thewholeschemeconsistsofthreelevels: 1. HostComputer(highestlevel):Providesuserainterfaceforprogrammingandmonitoringthesystem. Usersdoprogramminginhostcomputer,andthencompiletheprogramsandsendthemtothelower levels.Realtimeprogramsarenotrunningatthislevel.Whenthelowerlevelprogramsarerunning, datafromlowerlevelsaresenttothehostcomputeranddisplayedonthescreensothattheusercan monitorthewholesystem. 2. Realtime Computer (medium level): Receives the data from FPGA level, executes the control algorithmsandsendsthedatatoFPGAlevel.Thislevelisimplementedinrealtimeevery Tm seconds. But the sampling rate 1/ Tm cannot be too high because this level may need to execute some complicatedcontrolalgorithms. 3. FPGA Modules (lowest level): Takes in the measurements of the signals from physical systems, do some simple processing of the data, and sends out the control command. The bottom level FPGA program is implemented in very high sampling rate because it only has to do some simple data processingfortheinputsandoutputs.

When the program is running, each level does its own job: host computer supervises the whole system, realtime controllerimplementsthemajorcomplicatedalgorithmsandFPGAmoduleprocessesinputoutputdata.Thethree levels interact with each other by exchanging data through channels and memories inside the NI hardwares. The datatransferissafeandsecure. The modules installed in the lab hardware are described in Table 1. All connections from the cRIO used in the lab are made through the connector box to which the cRIO is mounted. Each connector is labeled according to the namingschemeusedwithinLabVIEWtomaketheassociationbetweensoftwareandhardwareselfexplanatory.

Figure6:Hostandrealtimecomputerarrangement. Table1:cRIOmoduledescriptions.

Slot# 1 23 4 5

ModuleType NIcRIO9022 NI9505 NI9401 NI9263 NI9205

ModuleDescription RealTimeControllerwith256MBDRAM,2GBStorage FullHBridgeBrushedDCServoDriveModule 8Ch.,5V/TTLHighSpeedBidirectionalDigitalI/OModule 4Channel,100kS/s,16bit,10V,AnalogOutputModule 32Ch200mVto10V,16Bit,250kS/sAnalogInputModule

FPGA TUTORIAL
ThistutorialwilldescribeaLabVIEWprojectthatusestheFPGAtogenerateandmeasureananalogvoltagesignal. It should be noted that, two vi files need to be programmed and implemented. One is the FPGA vi file to be implemented in the FPGA level, the other is the realtime controller vi to be implemented in the realtime computerlevel.

HARDWARE SETUP
1. Using BNC cables and a Tjunction, connect one of the analog output signals on cRIO station to an analog inputandtotheoscilloscope.

PROJECT SETUP
1. 2. 3. OpenLabVIEWandselectNewEmptyProjectfromtheGettingStartedwindow. RightclickonthetopprojectheadingintheprojectwindowandselectNewTargetsandDevices. Select Existing target or device, then select the RealTime CompactRIO folder, and then the CompactRIO devicecorrespondingtoyourworkstation. IntheSelectProgrammingModedialogboxchoosetheLabVIEWFGPAInterfaceoption. ExpandtheChassisandFPGAnodesintheprojectwindow.RightclickonMod4(Slot4,NI9263)andselect Properties.ChangethecalibrationmodetoRawandclickOK. Rightclick on Mod 5 (Slot5, NI 9205) and select Properties. Change the calibration mode to Raw and the TerminalModetoDIFFforchannelsAI16AI23.ThenclickOK.

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FPGA LEVEL CODE IMPLEMENTATION

1. 2. 3. Expand the Chassis node in the project window, rightclick on the FPGA Target heading and select New VI. PlaceaWhileLoopontheblockdiagram. Drag an FPGA I/O Node for Mod5/AI16(or the analog input you selected on the cRIO station) from the ProjectWindowintotheWhileLoop. Place a second While Loop on the block diagram and add an FPGA I/O Node for Mod4/AO0 (or the port youselected.) Rightclick on the Mod5/AI16 output wire and select CreateIndicator on the front panel and label it as AnalogInput.RightclicktheindicatoriconontheblockdiagramandensureAdapttoSourceisselected. CreateaVerticalPointerSlideonthefrontpanelandlabelitasAnalogOutput.Setthelimitsas32768to 32767,andconnecttheVerticalPointerSlidecontroltotheA0Nodeontheblockdiagram. WireaFALSEBooleanConstanttotheLoopConditionterminalforbothWhileloops.TheVIblockdiagram andfrontpanelshouldnowappearasshowninFigure7. Save the VI and the project, then rightclick on the VI in the project tree and select Compile (Run). This processcantake10minutesormore.

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After the build process completes, you may run the VI by click the play button. Adjust the analog output valueandwatchtheresponseintheanaloginputvaluetoverifyproperoperation.

Figure7:FrontpanelandblockdiagramofFPGAprogram.

REAL TIME COMPUTER LEVEL CODE IMPLEMENTATION

1. 2. 3. RightclickontheNicRiotargetheadingintheprojecttreeandselectNewVI. PlaceaControl&SimulationLoopontheblockdiagram. Doubleclick on the lefthand side of the simulation loop to bring up theConfigure Simulation Parameters window. Set the Final Time to be Inf, the ODE Solver to be RungeKutta 1 (Euler), and the Step Size to be 0.01. ClickontheTimingParameterstab.ChecktheSynchronizeLooptoTimingSourceboxandchecktheAuto Periodbox.SelectOKtoclosethewindowandsavethesettings. Go to the Signal Generation subpalette and place a Sine Signal block within the simulation loop on the blockdiagram. Doubleclick on the Sine Signal block to open the Sine Signal Configuration page. Select the amplitude parameterandthenchangetheParametersourcetobeTerminal. Change the frequency to 2 and leave the Parameter source for this parameter at its default of ConfigurationDialogBox.SelectOKtoclosetheSineSignalConfigurationpageandsavethesettings. GototheFPGAInterfacepaletteandplacetheOpen FPGAVIReferenceVIandplaceitonthe diagramto the left of the Simulation Loop. Doubleclick on the VI and link it to the FPGA VIthat was created earlier. ClickOKtoclosetheSelectVIwindow.

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Place an FPGA Interface Read/Write Control VI on the block diagram. Connect the Open FPGA VI ReferencetotheRead/WriteControlVI.

10. Place an FPGA Interface Close FPGA VI Reference on the block diagram to the right of the Simulation Loop.ThenconnectittotheRead/WriteControlVI. 11. RightclickontheRead/WriteControlVIandselectAddElement. 12. Leftclick on the first element in the Read/Write Control VI and select Analog Output. Leftclick on the secondelementintheRead/WriteControlVIandselectAnalogInput. 13. WiretheSineSignalblocktotheAnalogOutputelementoftheRead/WriteControlVI. 14. GototheSimulationGraphUtilitiessubpaletteandplaceaSimTimeWaveformblockonthediagram. 15. ConnecttheAnalogInputelementoftheRead/WriteControlVItotheSimTimeWaveformblock. 16. CreateaVerticalPointerSlideonthefrontpanelandlabelitasAmplitude.Setthelimitstoaminimumof 0andmaximumof32767.ThenconnecttheAmplitudecontroltotheSineSignalblock. Yourblock diagram should now appear asshown inFigure 8. Runthe realtime VI on theCompactRIO target. WhiletheVIisrunning,varytheamplitudeofthesinewavewiththesliderasshowninFigure9.

Figure8:Realtimecodeblockdiagram.

 Figure9:Examplefrontpanelshowingvarioussinewaveamplitudes.

AGILENT TECHNOLOGIES INTUILINK SCOPE TOOLBARS

The IntuiLink Scope toolbar can be used to load the measured signal waveform and data from the Agilent DSO1012A scope. The package includes two programs: one is for Word, the other one is for Excel. The waveform can be acquired and automatically embedded into your current Word or Excel document. The waveform can be saved as bitmap image file. Also, in Excel, you can obtain the data log of the waveform. This program will be very handy when you are trying to capture a signal to put in your lab reports or to perform post processing of the waveformdatausingeitheraspreadsheetorMATLAB. In the IntuiLink toolbar image refers to the waveform image shown on the scope display screen. The word waveformreferstothesignalvoltagevalueofthewaveform.Thewaveformdataconsistsoftimeandamplitude information.TheproceduresgivenbelowdescribehowtousetheIntuiLinktoolbar.

EXCEL
1. 2. Turnonthefunctiongenerator,scopeandconnectthescopetothesignalofinterest. OpenExcelandclicktheAddInstabasshowninFigure10.

 Figure10:AgilentIntuiLinktoolbarforExcel.

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Click on the 2nd button Connect to Scope. In the window that opens, click on the item starting with USB in the Select Addresses pane. Then click the Identify Instrument(s) button. The DSO1012A scope should appear in the pane on the right. Select the identified scope and click OK as shown in Figure 11. Theothertoolbarbuttonscannowbeusedtoacquireimageorwaveformdata.

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WORD
TheIntuiLinktoolbarmustbemanuallyaddedtoWordusingthefollowingsteps: 1. ClickontheOfficebutton,andthenclicktheWordOptionsbutton. 2. Select AddIns on the left hand pane, then select Word AddIns in the Manage: dropdown. Then click the Gobutton. In theTemplates tabcheck the Agt1000.dot item in the Global templates and addins pane.If that option is not available, click the Add... button and navigate to the template located at c:\Program Files\Agilent\IntuiLink\1000Toolbar\Agt1000.dot. TheAddInstabisnowavailable,andcanbeusedasdescribedintheExcelsection. If macros are disabled for security reasons, they can be enabled by clicking the Office button, then Word Options.SelectTrustCenterinthelefthandpane,andthenTrustSettingsintherighthandpane.In the Macro Settings select Enable All Macros Restart Word, readd the toolbar, and the toolbar should then work.

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Figure11:Thescopemustbeidentifiedpriortouse.

REQUIREMENTS
The servo table consists of an electric motor with a geared shaft driving an external load. This can be modeled usingthecircuitdiagramandfreebodydiagramsgiveninFigure12.TheparametervaluesarelistedinTable2.

Figure12:Servotablemotorcircuit(left),armaturefreebodydiagram(center),andloadfreebodydiagram(right). Table2:Servotableparametervalues.

Parameter LA RA
KT KB JA BA N

Value 10 H 10 0.06 Nm A 0.06 Nm A

4.7 10-6 3 10-6

2

JL BL

10.4 10-6 7 10-6

Themotortorque, Tm ,isrelatedtothearmaturecurrent, i bythetorqueconstant, KT :

Tm KT i

andthebackEMF, eb ,isrelatedtotheangularvelocitybythebackEMFconstant, K b : Themotorcircuitdynamicsaredescribedby

R i V e LA i A b

. eb K b

where LA is the armature inductance, RA is the resistance, and V is the applied voltage. Summing moments aboutthearmatureyields
B J A A Tm T

where J A is the armature moment of inertia, BA is the friction coefficient, and T is the load torque. Summing momentsabouttheloadsimilarlyyields
1 N2

J B T
L L

where J L istheloadmomentofinertia, BL istheloadfrictioncoefficient,and N isthegearratio.Combiningthe aboveequationsandconvertingtoablockdiagramleadstotheresultshowninFigure13.

Figure13:Servotableblockdiagram.

GROUP WORK80 PTS.

1. Implement a LabVIEW simulation of the servotable block diagram given inFigure 13 with a one volt .(30pts.) stepinput,andincludeascreenshotorprintoutofthesimulatedresponseof and
L
L

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Rightclick on the simulation loop and select Configure Simulation Parameters. Change the Solver MethodtoEulerwithastepsizeof0.01sandrepeatstep1.(5pts.)

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Complete the FPGA tutorial given above and include a screenshot or print out of the front panel showingthemeasuredsinewaveatvariousamplitudes.(30pts.) Connect the output to the oscilloscope to verify that the sine signal is correct. Include a screenshot orprintoutfromtheoscilloscopeinyourreport.(15pts.)

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INDIVIDUAL WORK20 PTS.

1. What are some differences between the simulation responses generated by the Euler and Runge Kuttamethodsandwhatarethereasons?(10pts.) ReorderingthelocationofthechassismodulesrequirestheFPGAcodetoberecompiled.Whyisthis? (5pts.) What are some advantages and disadvantages of FPGAs compared to microprocessors and ICs? (5 pts.)

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