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The 8051 Microcontroller Address Decoding

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Address Decoding
Address decoding is the process of generating chip select (CS) signals from the address bus for each device in the system. The address bus lines are split into two sections: The N most significant bits are used to generate the CS signals for different devices. The M least significant bits are passed to the devices as addresses to the different memory cells.

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An Example
Lets assume a simple microprocessor with 10 address lines. Lets assume we wish to implement 1 KB memory using 128x8 memory chips. Solution: We will need 8 memory chips (8 x 128 bytes = 1 KB). We will need 3 address lines to select each one of the 8 chips. Each chip will need 7 address lines to address its internal memory cells.

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Address Decoding Methods

The previous example specified that all addressable memory space was to be implemented but there are some situations where this requirement is not necessary. If only a portion of the addressable space is going to be implemented there are two basic address decoding strategies.
Full address decoding: All the address lines are used to specify a memory location. Each physical memory location is identified by a unique address. Partial address decoding: Since not all the address space is implemented, only a subset of the address lines are needed to point to the physical memory locations. Each physical memory location is identified by several possible addresses.
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Full Address Decoding

Lets assume the same microprocessor with 10 address lines (1 KB memory). Lets assume we wish to implement 512 bytes memory using 128x8 memory chips.

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Partial Address Decoding

Lets assume the same microprocessor with 10 address lines (1 KB memory). Lets assume we wish to implement 512 bytes memory using 128x8 memory chips. (Same requirements as the previous slide)

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Implementing Address Decoders

Logic gates (such as ANDs, ORs, NANDs, NORs, ) Decoder ICs (such as 74138, 74154, ) ROMs containing look-up tables (LUTs)

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Address Decoding for 8051

If multiple ROMs and/or RAMs are interfaced to an 8051, address decoding is required. Typically, a decoder IC such as 74138 is used with its outputs connected to the chip select (/CS) inputs on the memory ICs. 8051 usually uses ROMs as code memory and RAMs as data memory. External ROMs and RAMs are enabled by different hardware signals:
ROMs are enabled by /PSEN signal. RAMs are enabled by /RD and /WR signals.

ROMs and RAMs may have the same address.

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Memory Organization

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Accessing External Code Memory o External code memory is ROM enabled by /PSEN signal. o Port 0 & Port 2 are unavailable as I/O ports. o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus.

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Accessing External Data Memory o External code memory is RAM enabled by /RD & /WR signals using MOVX instruction. o Port 0 & Port 2 are unavailable as I/O ports. o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus.

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ROM

RAM

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ADDRESS BUS [A0-A15] DATA BUS [D0-D7]

U2 A0 A1 A2 A3 A4 A5 A6 A7 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 LE OE 74LS373 3 4 7 8 13 14 17 18 11 1 D0 D1 D2 D3 D4 D5 D6 D7 ALE D0 D1 D2 D3 D4 D5 D6 D7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 30 pF C2 Y1 12 MHz 31 9 +5 V 40 30 pF +5 V +5 V C3 10 uF SW1 U1 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 EA RST VCC 8951 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE PSEN 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 A8 A9 A10 A11 A12 A13 A14 A15 RXD TXD /INT0 /INT1 T0 T1 /WR /RD ALE /PSEN

C1

R1 100

RESET

R2 8.2 k

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ROM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 +5 V /PSEN /CS0 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 1

U3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE PGM CE VPP

2764 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 1

U4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE PGM CE VPP

2764 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7

+5 V /PSEN /CS1

0000H-1FFFH
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2000H-3FFFH
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RAM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 /RD /WR +5 V /CS0 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 26

U5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE WE CS1 CS2

6264 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 26

U6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE WE CS1 CS2

6264 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7

/RD /WR +5 V /CS1

0000H-1FFFH
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2000H-3FFFH
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ADDRESS DECODER
U7 A13 A14 A15 +5 V 1 2 3 6 4 5 A B C G1 G2A G2B 74LS138 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 /CS0 /CS1 /CS2 /CS3 /CS4 /CS5 /CS6 /CS7

CS /CS0 /CS1 /CS2 /CS7

Address 0000H 1FFFH 2000H 3FFFH 4000H 5FFFH

E000H - FFFFH

74138 C
A15

B
A14

A
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

CS /CS0 /CS1 /CS2

0 0 0 1

0 0 1

0 1 0

X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

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/CS7

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EXTRA OUTPUT PORTS

Eg. To output 0FH to this port U8 MOV A,#0FH D0 3 MOV DPTR,#4000H D1 4 D0 D2 7 D1 MOVX @DPTR,A D2

ADDRESS: 4XXXH
U9A /CS2 /WR 2 1 3 74LS02

D3 D4 D5 D6 D7

8 13 14 17 18 11 1

D3 D4 D5 D6 D7 LE OE 74LS373

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

Eg. To output F0H to this port U10 MOV A,#0F0H D1 3 MOV DPTR,#6000H D2 4 D0 D3 7 D1 MOVX @DPTR,A D2

ADDRESS: 6XXXH
U9B /CS3 /WR 5 4 6 74LS02

D4 D5 D6 D7 D8

8 13 14 17 18 11 1

D3 D4 D5 D6 D7 LE OE 74LS373

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

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+5 V

EXTRA INPUT PORTS

10 K

Eg. To input from this port U11 MOV DPTR,#4000H D0 2 MOVX A,@DPTR D1 3 A0
D2 D3 D4 D5 D6 D7 3 /RD 2 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7

ADDRESS: 4XXXH
U12A 74LS32 /CS2 1

B0 B1 B2 B3 B4 B5 B6 B7

18 17 16 15 14 13 12 11 +5 V

DIR G 74LS245 10 K

Eg. To input from this port U13 MOV DPTR,#6000H D1 2 MOVX A,@DPTR D2 3 A0
D3 D4 D5 D6 D7 D8 6 /RD 5 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7

ADDRESS: 6XXXH
U12B 74LS32 /CS3 4

B0 B1 B2 B3 B4 B5 B6 B7

18 17 16 15 14 13 12 11

DIR G 74LS245

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References
I. Scott Mackenzie, The 8051 Microcontroller Cc ti liu trn Internet khng trch dn hoc khng ghi tc gi

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