Autumn VHDL course for TKK

Digital design with Hardware Description Languages

Autumn 1999 Mikael Platan (mikael.platan@nokia.com) Mark Davidson (allan.davidson@nokia.com) Vesa Koskela (vesa.j.koskela@nokia.com)

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VHDL = VHSIC Hardware Description Language

This course will cover two main topics: 1.) The VHDL language and it constraints. 2.) Why one would want to use the language in digital design. However, other questions will be answered such as Where does it fit on the world map of hardware design? Why is it here? Why ever use VHDL?

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VHDL
VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit

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Hardware Description Languages

There are many HDLs with different features and goals: - VHDL: U.S. Department of Defense sponsored project (first standard 1987) Most wide spread in Europe - VERILOG: Proprietary language first then opened to the public (late 80 s) Most wide spread in the USA - UDL/I: Unified Design Language for IC:s. Developed in Japan for common interchange format between CAD tools. - SILAGE: Suited for DSP application.

VHDL and VERILOG are the most common!

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VHDL History
- Originated from the US Government VHSIC program A need was seen for a method in which to describe a digital circuit in such a manner that it was free from any technical constraints. This would allow the Department of Defense to replace an obsolete component with a new one without large amounts of re-design work. - Further developed by Institute of Electrical and Electronics Engineers (IEEE) - Adopted as an IEEE STANDARD1076 in 1987 Hence VHDL-87! - All IEEE standards are subject to a review every 5 years This is where VHDL-93 comes from!
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VHDL - language
IEEE standard hardware description language 1076-1987 VHDL-87 Is based on the ADA language VHDL s worst competitor is VERILOG New VHDL version was approved in 1993. VHDL-93 New VHDL version to be approved early this year. It contains analog signal support. For digital design/modeling Also a AHDL (Analog HDL) is being developed. This is due to the growing importance of mixed signal systems. Most important application is in ASIC (Application Specific Integrated Circuit) design It is used for modeling, simulation, logic synthesis and testing Common method of modeling between designers and design tools

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VHDL features
Parallelisms. Different processes can be active independently of each other. This is fundamentally an accurate model for a digital system. Supports hierarchical design, topdown or bottom-up. Supports reuse through its library/package functions where functions and components can be collected Strongly typed language. This is similar to Pascal and other Software programming languages. It means that operands must be of the correct type for a operator to be called
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Dynamic types and their use with e.g. attributes: FOR i IN j range LOOP ... where the variable j s range can dynamically changed. Overloading. E.g. the same function can be called with different types of parameters. This is related to typing. To use the same function (operator) on different types of objects (operand) one must define it multiply to be compatible with all the required types.

VHDL - world
Good overview from Internet: http://vhdl.org FAQ, Frequently Asked Questions, in VHDL: http://vhdl.org/vi/comp.lang.vhdl/ VHDL International organizations e.g. standardization Usenet news groups: comp.lang.vhdl Tutorials on the net, VHDL models, libraries, news etc Many conferences. e.g. DAC http://www.mkp.com Documents: 1076-1987 Standard VHDL Language Reference Manual, IEEE standard VHDL... (-93) Numerous books: e.g. Perry VHDL, Bhasker - A VHDL primer Numerous VHDL products, also some Public Domain. The most known manufacturers: Synopsys, Mentor, Cadence, Summit, Renoir, TransEDA Design, Lecturing, Consulting, Subcontracting

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Modeling Digital Systems

Digital system = Any digital circuit that processes or stores information These systems are complex: We need to recognize them as complex and have to find ways to deal with the complexity The most important way is to adopt a systematic methodology of design The term MODEL will refer to our understanding of a system. A model should allow us to make predictions about the system. There can be several models of one system!
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Why MODELs
1) Formal model to communicate requirements. 2) Communicate and enhance the understanding of the function of a system 3) Models will allow testing and verification of a design using simulation. Thus allowing for the correction of errors before the system is manufactured. 4) Formal verification of the correctness of a design 5) To allow SYNTHESIS of circuits

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Why use Hardware Description Language for modeling

To model the design To verify the model To implement the model in hardware (synthesizing) Using a language to do this allows for more levels of abstraction. Giving the designer more freedom to implement ideas, rather than specifics, results in higher quality designs in a shorter time.

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Remember!
The idea behind all of these arguments is that: We want to achieve maximum reliability in the design process for a minimum cost and design time!!

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Domains and Levels of Modeling

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Functional
At the most abstract level the system may be described in terms of ALGORITHMS NOTE! This is often called BEHAVIOURAL MODELING Example: loop for each data input loop read the value on this input; scale the value using the current scale factor for this input convert and write.... end loop; wait for 10ms; end loop;
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Structural
The system may be described as an interconnection of components like processors, memories and i/o devices. Sometimes called as the Processor Memory Switch, PMS, level. Example:

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Geometric
Top level abstraction: How the components described in the structural model are organized on the silicon die. Pad frame

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Next level in abstraction: REGISTER TRANSFER LEVEL

Register Transfer Level: Structural model: Example:

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Register Transfer Language (RTL)

In the functional domain a Register Transfer Language is used to specify the operation of a system at the Register Transfer Level: Example: MAR <- PC, memory_read <- 1 PC <- PC + 1 wait until ready = 1 IR <- memory_data memory_read <- 0

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Most designers work more and more away from the center

Tools help designers work away from the center

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Why VHDL as modeling language?

Includes facilities to describe structure and function at VARIOUS levels of abstraction (above gate level) Has an attribute mechanism to annotate information from the geometric domain. It can be used for specification, simulation and hardware synthesis It is widely supported by CAD tool vendors. It is a standard being continuously reviewed.

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Graphical Entry tools - need anymore to learn VHDL?!

Today many Graphical Entry tools that automatically generate VHDL code exist (Summit, Renoir) They are becoming so good that they are already being used in production The need for writing actual code may have been reduced due to GE tools but: 1) the need to understand what was auto generated is still there 2) we still have to manage large amounts of vhdl blocks 3) VHDL is still the descriptive part 4) Many of the GE tools are not producing correct or optimized code in all situations. GE tools should be viewed as a complement not a replacement to VHDL.
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VHDL Modeling Concepts

We have discussed three domains of modeling: 1) Function 2) Structure 3) Geometry We will now introduce VHDL elements to describe the basic modeling concept in each of the above 3 domains. NB: The objective is to GET A FEEL for VHDL as a description language - All these will be discussed in detail later.

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Entity

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Elements of Behavior
- Internal function of an entity is called ARCHITECTURE - An architecture can have a number of alternative functions - A behavioral architecture of an entity consists of Process statements - Process statements are a collection of actions executed in sequence (sequential statements) Example:

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architecture behav of reg4 is begin storage : process is variable stored_d0, stored_d1, stored_d2, stored_d3 : bit; begin if en = '1' and clk = '1' then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; end if; q0 <= stored_d0 after 5 ns; q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns; wait on d0, d1, d2, d3, en, clk; end process storage; end architecture behav;
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Elements of Structure
An implementation of an entity can be viewed as being composed of subsystems An architecture body that only has interconnected subsystems is called an structural architecture body Example:

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Structural composition

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Subsystem description
entity d_latch is port ( d, clk : in bit; q : out bit ); end d_latch; architecture basic of d_latch is begin latch_behavior : process is begin if clk = '1' then q <= d after 2 ns; end if; wait on clk, d; end process latch_behavior; end architecture basic; entity and2 is port ( a, b : in bit; y : out bit ); end and2; architecture basic of and2 is begin and2_behavior : process is begin y <= a and b after 2 ns; wait on a, b; end process and2_behavior; end architecture basic;

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Structural architecture
architecture struct of reg4 is signal int_clk : bit; begin bit0 : entity work.d_latch(basic) port map (d0, int_clk, q0); bit1 : entity work.d_latch(basic) port map (d1, int_clk, q1); bit2 : entity work.d_latch(basic) port map (d2, int_clk, q2); bit3 : entity work.d_latch(basic) port map (d3, int_clk, q3); gate : entity work.and2(basic) port map (en, clk, int_clk); end architecture struct;
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Mixed Models

In models it can be and is often useful to mix structural and behavioral models

One of the strengths of VHDL is the amount of freedom it gives to the designer. Good design is using the appropriate method of modeling.

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Test benches
It is an entirely self-contained entity, with no port list, that stimulates the VHDL block under test. The block under test is instantiated as a component in the test bench and structurally connected to the test bench. Test benches will be covered more in detail in lecture #6.

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Analysis, Elaboration and Execution

Analysis: The process of checking the syntax and semantics of the code Elaboration: Going through the design hierarchy and creating all of the objects defined in the declarations. Execution: The passage of time is simulated in discrete steps.

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Reserved Words in VHDL -93

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Extended Backus-Naur Format (EBNF)

For syntax description EBNF is used throughout the book.

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