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A Current Consumption Measurement Approach for FPGA-Based Embedded Systems

ilvinas Nakutis, Member, IEEE

AbstractIn this paper, an approach for the currentconsumption measurement of a eld-programmable gate array (FPGA)-based embedded system is presented. This approach is based on the current conversion to pulsewidth using the external-to-FPGA capacitor charging circuit and comparator. The pulsewidth is then measured using the timer synthesized inside the FPGA. Measurement uncertainty budget analysis is performed. It reveals the parameters mostly affecting steadystate current measurement uncertainty. Sources contributing to the budget of current measurement uncertainty include directly measured pulsewidth, manufacturing scattering of measurement setup component parameters, and their uctuations in response to the measured current value. A calibration procedure enabling to reduce the inuence of charging circuit component manufacturing tolerances on measurement uncertainty is suggested. The current measurement prototype is developed and tested. Measured pulsewidth jitter is estimated experimentally using the prototype. The jitter inuence on measurement uncertainty is modeled by including the corresponding quantity in the measurement model. The inuence of the temperature on measurement uncertainty is estimated using Monte Carlo simulation. Index TermsCurrent measurement, debugging, eldprogrammable gate arrays (FPGAs), measurement techniques, uncertainty.

I. I NTRODUCTION HE POWER consumption of an embedded system (ES) is a key issue in todays high-performance designs and battery-powered devices used for wireless, medical, utility metering, electronic infotainment, and mobile communication applications. The key programmable components of a modern ES are a microcontroller and/or a eld-programmable gate array (FPGA). These components power consumption depends on the executed program, operation mode (active or low power), conguration, and data processed. Software-related power is not constant and may uctuate in response to the running software or FPGA conguration. When targeting the minimization of ES power consumption, both the methods and the tools for power estimation are

Manuscript received June 14, 2012; revised December 4, 2012; accepted December 5, 2012. Date of publication March 6, 2013; date of current version April 3, 2013. The Associate Editor coordinating the review process for this paper was Dr. Theodore Laopoulos. The author is with the Department of Electronic and Measurement Systems, Kaunas University of Technology, 51368 Kaunas, Lithuania (e-mail: zilvinas. nakutis@ktu.lt). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIM.2013.2245036

necessary. It is vital that engineering practice would adapt efforts to minimize the power consumption of equipment in every design cycle to potentially save several hundreds of milliwatts per electronic unit. These units run every day and are used in large quantities (telecommunications infrastructure, medical monitoring, household and ofce equipment, security applications, car infotainment, etc.), which means that minimizing power consumption could equate to considerable energy savings on both national or international scales. To pave the road toward minimizing ES power consumption design, teams must be aware of appropriate tools and solutions that are inexpensive and conveniently integrated into standard design ow. In my opinion, there is still a distinct need for such solutions. Available commercial systems like J-Link Ultra [1] from IAR Systems and PowerScale [2] from Hitex Development Tools are still very expensive. Both of the aforementioned tools utilize dynamic current consumption (CC) measurement using a resistive shunt method. The shunt resistor must either be assembled on the ES [1] or can be built inside the probe that is connected to the ES using dedicated pins [2]. So-called probes, or adapters, are usually implemented as external devices that are connected between the ES and the workstation computer during the development. Manufacturers do not disclose the implementation of their measuring probe schematics. The stated sampling frequency is 50 kHz [1] or 100 kHz [2]. A current measurement resolution of 1 mA is specied in [1]. A current measurement range of 200 nA500 mA is specied in [2]. J-Link Ultra is a tool highly integrated with the IAR Electronic Workbench development environment. The environment can display the power consumption prole with respect to the software executed by the embedded microprocessor. PowerScale offers similar features and has an open interface for use with various development environments. However, none of these tools is intended for FPGA-based ES power consumption monitoring. Therefore, a simple solution for power estimation in FPGA-based designs is considered in [3]. The goal of this research is to perform a current measurement uncertainty analysis. The uncertainty is important when design teams, working with different instances of ES, need to compare the CC of their designs. The comparison of measured currents only makes sense when the measurement uncertainty is known. It is assumed that the measurement setup cannot be calibrated using any reference equipment, and therefore, the uncertainty can be estimated using information available from manufacturers of components composing the measurement setup and information gained from simulation or experimental measurements of the setup.

0018-9456/$31.00 2013 IEEE

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II. R ELATED W ORK An overview of the current status of ES power consumption measurement challenges, methods, and instrumentation is presented in [4] and [5]. Known methods for ES power consumption estimation are based on current measurement in supply lines using a shunt resistor [6], [7], current mirror [8], [9], sleep transistor resistance [10], charge transfer [11], battery status monitoring [12], or thermal chip status monitoring [13]. The most popular and least expensive [14] current-sensing method utilizing a shunt resistor is usually implemented using a current shunt amplier (CSA) or differential amplier followed by an analog-to-digital converter [15]. Since the supply voltage of an ES with FPGA is usually kept constant in a narrow range, for example, 1.20 0.05 V or 3.30 0.05 V, then power estimation mainly deals with the estimation of the current. Power estimation techniques can be separated into on-chip and external according to the placement of the measurement circuitry. On-chip techniques usually employ extra semiconductor components manufactured together with the main chip (microprocessor) at the silicon level [10], [13]. The techniques that require some measurement circuit components to be placed outside the chip [16] need extra printed circuit board (PCB) area close to the chip. Although it is obviously a disadvantage, this approach preserves a possibility for the power estimation of all chips available on the market. In this paper, a technique that requires only an external shunt resistor, low-pin-count integrated amplier, comparator, and a few passive components is proposed. The rest of the measurement circuit is synthesized from FPGA resources. A typical current measurement setup contains the currentsensing circuit and the analog voltage conversion to digital code. In this paper, current sensing using a shunt resistor connected to the off-the-shelf CSA is adapted. The conversion of the amplier output voltage to digital code can be done either by the following: 1) using off-the-shelf analog-to-digital converter (ADC) chips (additional PCB area and routing are drawbacks); 2) using successive approximation or delta-sigma ADC principles [16] whose implementation needs some passive components external to FPGA and some FPGA resources for ltering; or 3) converting voltage to pulsewidth (time) that can be measured using a timer. Seeking to minimize the amount of external components and necessary FPGA resources, the setup applying voltage-to-time conversion is selected for the further analysis. In Section III, the proposed current measurement setup is explained. Then, Section IV is dedicated to discussing its implementation, and nally, Section V is intended to present the measurement uncertainty analysis. III. M EASUREMENT S ETUP A. Measurement Technique and Circuit The considered measurement technique is based on converting measured current to voltage, and later to pulsewidth. The pulsewidth is then measured using the high-frequency oscillator as the reference signal. As overviewed in [3] for the reference signal, one may either use an external clock generator or a clock signal whose frequency is multiplied by the internal phase-

Fig. 1. Measurement circuit.

locked loop (PLL) of the FPGA. Typical external oscillators used in FPGA systems are 27- or 50-MHz quartz stabilized oscillators, and currently marketed FPGA PLL output frequencies can reach up to 200 MHz or even 500 MHz [3]. The proposed circuit is shown in Fig. 1. It consists of a shunt resistor RS , a CSA U1, an antialiasing lter (R2 , R3 , and C2 ), and a capacitor C1 . Capacitor C1 is charged through resistor R1 and discharged by the switch SW1. Comparator U2 is used to detect the time moment when the capacitor C1 voltage VC becomes equal to the CSA output voltage VA . Current source generator IG is used to model the CC of the ES. VCC represents the supply voltage of the FPGA core. The market overview provided in [3] indicates that FPGA core supply voltages currently are 0.9 V, 1.0 V, 1.2 V (most often), or 1.5 V. Therefore, only CSA with common-mode input range inclusive of VCC is suitable for the setup. For the further analysis and prototype implementation, CSA INA193 from Texas Instruments (TI), Inc. [17] is selected. Resistors R5 and R6 implement the external hysteresis. The antialiasing lter (R2 , R3 , and C2 ) limits the spectral bandwidth of the input signal in order to suppress spectral components with frequencies above fstop . The recommended attenuation in decibels Lstop at the stop frequency fstop = FS fcut must not be less than the dynamic range [18]. The expected measurement relative uncertainty is 2%, which corresponds to the attenuation Lstop = 33 dB. The sampling frequency is assumed FS = 50 kHz, as it seems to be the typical sampling frequency used by most manufacturers of dynamic power estimation tools [1], [2]. The expression for the lters cutoff frequency fcut can be taken from the CSA data sheet [17] fcut = 1/ (2 (2R2 )C2 ) . (1)

If R2 = R3 = 100 and C2 = 680 nF, it can be calculated that fcut = 1.17 kHz. Keeping in mind the 6-dB/octave attenuation slope of the rst-order RC lter, one can estimate that the attenuation at the frequency fstop is roughly 33 dB. Due to the voltage drop on the shunt resistor, a resistance must be selected so that one does not violate the permissible limits of FPGA supply voltage. Most of FPGA core voltages allow approximately 0.05-V tolerance of supply voltage. Therefore, the shunt resistance RS = 0.5 is acceptable for

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the measurement of currents not exceeding 100 mA so that the voltage drop on the shunt resistor is 100 mA 0.5 = 0.05 V. The reduction of the shunt resistance can increase the maximum measured current. For example, a shunt resistor RS = 0.05 would allow one to measure the currents up to 1 A. One downside of the reduced shunt resistance is the reduced measurement sensitivity. CSA gain errors usually tend to increase in the range of lower input voltages [17]. Therefore, using a lowresistance shunt may cause additional measurement errors. An additional source of errors in the case of the low-resistance shunt may be the soldering contact resistance [14], [19]. The inuence of the shunt resistor soldering can be addressed by using the four-wire Kelvin principle [14], and by following special recommendations for PCB pad layout congurations as described in [19]. Therefore, in the measurement uncertainty analysis in Section V, the inuence of soldering resistance is neglected. The developer, having a preliminary knowledge about the range of CC of an ES, could choose the appropriate shunt resistance. The selection of RS = 0.5 in the schematics shown in Fig. 1 for further analysis is only one possible example that is used to demonstrate the operation of the proposed setup and to present the uncertainty analysis with numerical values. B. Measurement Model The derivation of the relationship between the measured current, the directly measured pulsewidth, and the parameters of circuit components is given hereinafter. At the beginning of a sampling period, the capacitor C1 is discharged, and the voltage VC (t) is equal to zero. This condition causes comparator output voltage VK to be close to ECC . The comparator output changes its state to VK 0 V at the time moment ti when negative input voltage Vin exceeds positive input voltage Vin+ . Taking into account the internal hysteresis Vh0 and the comparator offset voltage VOS , the comparator output state change moment ti must comply with the following equation: Vin+ (ti ) = Vin (ti ) + VOS Vh0 /2 (2)

where = R 1 C1 ti = tm tpd + tn . (6) (7)

In (7), tm is the pulsewidth measured by the timer synthesized from FPGA resources, tpd is the comparator switching (propagation) delay, and tn is the quantity used to model the jitter of the comparator switching moment due to the inuence of noise in the measurement circuit. The term tn is considered a random quantity with zero mean and standard deviation (its detailed estimation is provided in Section V-A). The mean value of tn is used for ti estimation by (7). The standard deviation of tn is used for the estimation of jitter inuence on the current measurement uncertainty. Substituting (3)(7) to (2) and expressing current iCC , the following measurement equation can be derived: iCC = 1 ECC 1 e(tm tpd +tn / ) GRS (1 kh ) +VOS Vh0 /2 ECC kh VOSA G(1 kh ) (8)

where kh = R5 /(R5 + R6 ). In order to encounter the inuence of temperature variations on the real values of the passive components, each resistance R and capacitance C is substituted by the corresponding expressions R = Rn (1 + R T ) C = Cn (1 + C T ) (9) (10)

where Vin (ti ) = VC (ti ). Neglecting both comparator input resistance (which is usually much larger than the resistance of R5 and R6 ) and CSA output resistance (1.5 according to the manufacturers specication), the positive comparator input voltage Vin+ can be related to the voltage VA at the amplier output Vin+ = VA + (VK VA ) R5 . R5 + R6 (3)

where Rn and Cn are nominal values, R and C are temperature sensitivity coefcients in ppm/ C units, and T = T T0 , where T0 = 20 C and T is the ambient temperature. The real value of CSA gain factor G is inuenced by the manufacturing tolerance and temperature uctuations. Gain factor G is therefore modeled by the expression G = G0 + dGR + dGT (11)

VA can also be expressed in the following way: VA = (iCC (t) RS + VOSA ) G (4)

where G is the gain factor of the CSA and VOSA is the offset voltage of the CSA. Capacitor charging voltage at the comparator state toggling moment can be written VC (ti ) = ECC (1 eti / ) (5)

where G0 is the gain nominal value and dGR and dGT represent correspondingly deviations from the nominal value due to manufacturing tolerance and the temperature inuence. It may be seen from the manufacturers specication [17] that the nominal gain G0 depends on the input voltage level and tends to increase at the lower input voltages. The CSA input voltage is related to the measured pulsewidth tm . Points {tmi , G0i }, i = 1, 10, of the relationship between G0 and tm are obtained by simulating the measurement circuit (see Fig. 1) in the range of input currents from 5 to 100 mA using a Tina-TI simulator from TI [20]. The Tina-TI simulator is based on the industry standard SPICE simulator and is freely distributed together with many simulation models for components like the CSA and comparator used in this work.

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Fig. 2.

System architecture.

It is found that the relationship between G0 and tm can be approximated by G0 G0Apr (tm ) = k G1 + kG4 + dG0Apr (12) k G2 ( t m k G3 )

Fig. 3. Prototype coupled with Altera DE2 board.

B. CC of Measurement Circuit The CC of the measuring part of the proposed system is composed from the current that is consumed inside the FPGA and the current consumed by the external components. The current that is consumed by modules I -timer and Debug IP core (see Fig. 2) ultimately depends on their implementation and particular FPGA type. Approximate current estimates in the case of Altera Cyclone II FPGA are obtained using Altera PowerPlay analyzer (utility of Altera Quartus 12.0 development environment). The module I -timer is described in Verilog language. It implements a 32-b counter with the gate input driven from the comparator output. The module I -timer is also responsible for the capacitor C charging and discharging (see Fig. 2) in the rate of sampling frequency (50 kHz). The external clock frequency used for I -timer clocking is set to 50 MHz. The Debug IP core (Altera SignalTap analyzer) is congured to hold 32-b samples in a 4 K buffer. In such a setup, the power simulator reports a 4.09-mA total CC of both I -timer (1.02 mA) and Debug IP core (3.07 mA) modules. This current should be subtracted from the FPGA CC measurement result to estimate the CC of FPGA application conguration. The preliminary estimate of the CC imeas (assuming VCC = 3.3 V) of the external to the FPGA circuit, which is assembled in the prototype, is carried out using a dc amperemeter (MX 594 Meteix) inserted in the supply line at the output of the ECC source (see Fig. 1). Quiescent current is measured with no recharging of capacitor C1 and by disconnecting the comparator output from the FPGA input. The measured current is imeas = 5.50 mA. During the normal system operation, the current imeas is dependent on the current owing through the shunt resistor. The largest current imeas = 6.20 mA is observed when the shunt resistor current is close to 0 mA and comparator output is at the high-level state over the whole sampling period. Current imeas is the sum of static Is and dynamic Id currents, imeas = Is + Id . It is well known that dynamic current appears as the result of switching activities in the circuit and is proportional to the switching frequency. The static current represents leakages that do not depend on switching activities. After obtaining current measurement imeas1 = 6.20 mA at the

where kG1 , kG2 , kG3 , and kG4 are coefcients that are found by tting expression (12) to the data set {tmi , G0i }, i = 1, 10. Part dG0Apr is included to represent the approximation error. Equation (8), together with (6) and (9)(11), is considered as the measurement model in the further analysis. IV. I MPLEMENTATION D ISCUSSION A. System Architecture The possible system architecture is presented in Fig. 2. The pulsewidth measurement module called I -timer is synthesized from FPGA resources. The time-controlled switch (SW1 in Fig. 1) is implemented using the high-impedance output of general-purpose input/output GPIO1. The comparator COMP can also be implemented inside the FPGA using the internal comparator of low-voltage differential signaling (LVDS) inputs that are available in most FPGAs [16]. However, the suitability of these comparator parameters and the possibility to access it in non-LVDS input mode still need to be veried. The I -timer output can be connected to the standard debug cores, for example, the Altera SignalTap analyzer or Xilinx ChipScope. The current measurement results can be delivered to the graphical interface of integrated development environment like Altera Quartus, Xilinx isePack, etc., through the debug core connected to a standard Joint Test Action Group (JTAG) port. Finally, the time instance of the current measurement can be synchronized with the processes of the main application conguration of FPGA. The prototype developed is shown in Fig. 3. The small PCB board hosts the CSA, recharging circuit, and comparator. The shunt resistor is soldered on the Altera DE2 board. The recharging control signal GPIO1 and the comparator output signal GPIO2 are connected via a standard general-purpose input/output port header of the Altera DE2 board. The driving GPIO1 signal is forced to ground (logic 0) for C1 discharging and set to high-impedance state for C1 charging.

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frequency of 50 kHz and imeas2 = 6.15 mA at the frequency of 20 kHz, it can easily be found that Id constitutes only 1.3% of the total CC at the 50-kHz sampling frequency. It can be mentioned that the decisive contribution in the budget of imeas belongs to the sum of quiescent currents of the comparator and CSA, as can be found from manufacturers data sheets. C. RC Calibration Procedure The analysis of the current measurement uncertainty budget reveals (presented in Section V) a signicant inuence of capacitor C1 manufacturing tolerance. The NP0 class ceramic capacitor with 5% tolerance is used for C1 . In order to reduce the impact of its manufacturing tolerance, a calibration procedure at the beginning of the work session can be applied for the quantity [see (6)]. Using switch SW, the reference voltage Vref = VCC can be connected to the positive input of the comparator. From (2)(7) and substituting VA by Vref , the following equation can be derived: Cal = (tmCal tpd tn ) ln 1
Vref R6 +VK R5 R5 +R6

TABLE I U NCERTAINTY S OURCES

VOS +Vh0 /2

(13)

ECC

where tmCal is the measured pulsewidth corresponding to the Vref applied at the positive input of the comparator. V. U NCERTAINTY A NALYSIS A. Methodology Current measurement uncertainty is a combination of steadystate and dynamic parts. The dynamic uncertainty is caused by sampling errors that are dependent on the transfer function of the antialiasing lter and the characteristics of the measured current waveform. It is expected that the measured current waveform should be a band-limited train of pulses (rectangular and steplike waveform as called in [21]). Indeed, the CC uctuations may be caused by switching on/off various modules of FPGA application conguration. The measurement of the CC waveform is an intermediate step during an ES design. The nal goal usually is to estimate the energy demanded from the supply source in the time period of interest. To estimate the energy, the average current value over that period must be multiplied by the supply voltage and by the duration of the time period. The analysis of rectangular and steplike waveforms average value estimation errors resulting from low-pass ltering (including antialiasing ltering) is presented in [21] and can be adapted to derive the dynamic uncertainty of the energy estimation. The law of uncertainty propagation is used to estimate the steady-state uncertainty u(iCC ) of indirectly measured current iCC according to the Guide of the Expression of Uncertainty in Measurement (GUM)
N

(8)]. The measurement model (8) includes not only the directly measured quantities but also parameters characterizing components used for measurements (see Fig. 1) like shunt resistance RS , CSA gain factor G, etc. Due to the manufacturing tolerances, these parameters can be treated as random quantities. Indeed, two independent designers having separate identically assembled instances of the proposed current measurement setup and measuring equal currents will not obtain the identical results because of component parameters manufacturing scattering. Therefore, some of u(xj ) in (14) represent the standard deviation of schematic parameters as provided by the manufacturer or estimated otherwise. B. Uncertainty Sources The current measurement uncertainty of the setup (see Figs. 1 and 2) is dened by the model (8) and probability distributions of quantities included in the model. Uncertainty sources along with their distributions are listed in Table I. The distributions of dGR , dGT , RS , R6 , R5 , R1 , C1 , VOS , and VOSA are determined following the GUM recommendation to assign the rectangular probability distribution to the random quantity if only its range is known. This is the most frequent case with the parameters provided in manufacturers data sheets. For example, if one nds that the resistance tolerance is 1% and its nominal value is 0.5 , then the resistance value can be characterized as a random quantity whose probability distribution is rectangular, mean value is M = 0.5 , and half width of the distribution is HW = 0.005 (notation used in Table I is R: M = 0.5 and HW = 0.005 ). The GUM Workbench calculator is able to assign the input quantity either rectangular or normal distributions. The standard uncertainty is calculated from the half width of the rectangular distribution ac cording to the expression u(xj ) = HW/ 3. For the quantities

u2 (iCC ) =
j =1

(iCC /xj )2 u2 (xj )

(14)

where u(xj ), j = 1, N , represent standard uncertainties of the directly measured quantities [for example, pulsewidth tm in

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distributed normally, for example, tn , the standard deviation is entered directly and is then used by the GUM Workbench calculator for the appropriate u(xj ) = u(tn ) value in (14). The selection of distributions and nding their parameters of the other input quantities listed in Table I are commented hereinafter. The approximation error [see (12)] of the CSA gain factor dependence on pulsewidth tm is a random quantity with the rectangular distribution having zero mean and half width equal to max(|G0 G0Apr |). The pulsewidth tm is the direct measurement result obtained using the digital timer I -timer. Assuming that a typical 50-MHz frequency generator [3] is used for the reference clock, the half width of the distribution is HW = t = Tref /2 = 10 ns. The uncertainty of propagation delay tpd is acquired from measurement circuit (see Fig. 1) simulation results. The coordinates of ten points of the relationship between tpd and the generator IG current in the range from 5 to 100 mA are rst obtained using the Tina-TI simulator. Then, the largest and the smallest observed tpd values are selected for tpd scattering range limit characterization. The mean value of tpd is set to the middle of the found range. The manufacturers specied tpd is not used because it is usually given at xed and constant voltage differences at the comparator inputs. On the opposite, in the measurement circuit, one of the input voltages (negative input) is not constant, nor is the speed of its change. The inuence of circuit noise on the comparator switching moment (keeping measured current xed) is represented by the quantity tn . Its probability distribution is estimated experimentally using the developed prototype (see Fig. 3) and utilizing the statistics collection capability of a Yokogawa DLM2000 oscilloscope. The number of acquisition periods used for pulsewidth ti duration probability distribution and its standard deviation estimation is set to 300. It is found that pulsewidth exhibits normal distribution whose standard deviation depends on the measured current. The current stimulus is generated using laboratory dc supply source. The largest standard deviation of 40 ns is observed at the lowest input current iCC = 5 mA. The mean value of time constant Cal is set to the product of nominal values of charging circuit resistance and capacitance R1 C1 . Time constant standard uncertainty is estimated using the GUM Workbench from the model (13) and the probability distributions of other uncertainty sources given in Table I. The nominal value of tmCal needed for uncertainty estimation is obtained from (13) by assuming Cal = R1 C1 . The nominal values of Vref and ECC are supposed to be measured using a 0.5% accuracy digital multimeter. C. Temperature Inuence Resistance and capacitance values of passive components and parameters of active components (CSA gain factor, CSA, and comparator offset voltages) are inuenced by the ambient temperature [see (9) and (10) and [17]]. Therefore, measurement results depend on temperature. The signicance of temperature uctuation inuence on measurement uncertainty is estimated using the Monte Carlo (MC) method. The method based on the uncertainty propaga-

tion law (14) is not applicable because of zero partial derivatives iCC /R , iCC /C , and iCC / T of (14). Temperature sensitivity coefcients (s.c.) are listed in Table I. Notation = 100 ppm/ C means that the mean value of is equal to 0 and the half width of the rectangular probability distribution is equal to 100 ppm/ C. MC simulation is the mathematical method applicable for uncertainty estimation when some derivatives of input quantities are equal to zero. It is based on the computer generation of samples of input quantities according to their known probability distributions and calculating the output (measured) value estimate. After performing a large number of simulated experiments, the standard deviation which represents standard uncertainty is estimated. The MC estimation method is implemented in the GUM Workbench calculator. Input information needed for iCC uncertainty estimation includes the model (8) and the probability distributions of input quantities given in Table I. Temperature is assumed to vary randomly within the range +20 C 15 C (laboratory conditions). The MC simulation is run as follows: 1) rst, by setting all s.c. of passive components to be random within their specied range (for example, shunt resistor s.c. is a random quantity with the rectangular distribution within the range from 100 ppm/ C to +100 ppm/ C); 2) second, by assigning all s.c. equal to their maximum values; and 3) third, by assigning all s.c. to zero. In neither of these cases, any noticeable difference in the estimated current measurement standard uncertainty is observed (the uncertainty estimates are provided with three signicant digits). Because of this, it is concluded that the temperature variation in normal laboratory conditions is negligible when compared to the rest of the uncertainty sources. Even by allowing the temperature to uctuate in the range of +20 C 100 C, its inuence on the uncertainty is still negligible. Therefore, even FPGA warm-up during its operation does not seem to be an issue. One troublesome parameter remains, the CSA gain factor error. In the INA193 specication [17], only the graphical curve is given to represent gain error versus temperature dependence in the range from 40 to +125 C. The maximum gain error is 1%. Error could be much lower in the temperature range of +20 15 C. However, the value of 1% is used in the following estimation in order not to underestimate uncertainty. D. Current Measurement Uncertainty Budget Using the measurement model (8) and uncertainty sources listed in Table I, the steady-state current measurement Type B uncertainty is estimated using the GUM Workbench from Metrodata GmbH. The uncertainty contribution index bj for each j th quantity is calculated using the GUM Workbench bj = (iCC /xj )2 u2 (xj ) 100%. u2 (iCC ) (15)

The uncertainty contribution index for each j th quantity is calculated at several values of the measured current, and the uncertainty budget is plotted in Fig. 4. In fact, the value of tm is

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Fig. 5.

Current measurement relative standard uncertainty.

Fig. 4. Current measurement uncertainty budget.

changed in each calculation to obtain the current values shown on the axis Current in Fig. 4. The uncertainty budget indicates that, in the lower currents, range comparator offset voltage plays the decisive role. In the upper current range, CSA gain factor errors contribute the most to the uncertainty. The inuence of the comparator offset can be reduced by choosing a comparator with lower offset voltage that most probably will mean an increase in the setup cost. Another possibility could be a calibration procedure similar to the previously described calibration. Indeed, if one would measure widths of two pulses, each corresponding to the different reference voltages, then the solution of the system of two (13) could give an estimate of both the time constant and the comparator offset voltage. The inconvenience of such an approach is in the need of additional external reference voltage and a switch for temporary reference voltage connection to the positive input of the comparator. Offset voltage VOS uctuations due to the temperature changes and the supply voltage instability are neglected due to small sensitivity coefcients, and only its manufacturing distribution is considered. The random part dGR of the gain factor is dened by the implementation of CSA and by the tolerance of resistors R2 and R3 [17]. The reduction of the inuence of this factor requires the selection of more precision CSA and resistors which will have an impact on the setup cost. Similarly, the noticeable inuence of the shunt resistor tolerance and the inuence of time constant Cal standard deviation may be targeted by switching to passive components with better manufacturing tolerances. The relative standard uncertainty in the investigated measured current range from 5 to 100 mA is shown in Fig. 5. Expanding the measurement range toward higher currents can be done by reducing the shunt resistance as discussed in Section III-A. To ensure FPGA supply voltage level within the specied tolerance limits of 0.05 V, the input voltage of the CSA should not exceed 0.05 V. The nominal CSA gain G0 = 20 ensures that the largest voltage at the output of CSA is VAmax = 1 V. By substituting VK = ECC and VA = VAmax , it can be found that the largest voltage at the positive input of the comparator is Vin+max 1 V. In the case of the 50-kHz

sampling frequency, the voltage Vin must reach the voltage Vin+max latest at the time moment tmax = 1/(50 kHz) = 20 s. Since = 51.7 s > tmax , then the derivative of exponential charging curve at the time moment tmax is not close to zero and the inuence of noise does not affect measurement signicantly. In order to decrease the sampling frequency, the time constant should be increased to ensure that > tmax . Expanding the measurement range toward lower currents is mostly restricted by VOS (see Fig. 4). Comparator offset voltage VOS remains constant through the entire range of measurement currents, but the relative uncertainty increases when the measured current value is in the lower range. The additional uncertainty increase in the lower current range is caused by the inuence of the noise jitter and the increasing gain errors of the CSA at the lower levels of CSA input voltages. Indeed, as it is found from the experimental investigation of jitter, its standard deviation tends to increase when the comparator positive input voltage gets closer to zero. VI. C ONCLUSION A CC measurement method based on current-to-time conversion can be implemented using few external-to-FPGA components and is conveniently adaptable to various FPGA development tools, such as signal analyzer cores. The increase of the current measurement relative steadystate uncertainty in the lower current range (up to 5 mA) is mainly due to the comparator offset voltage manufacturing tolerance. The inuence of the pulsewidth jitter in measurement schematics and the current shunt gain errors are other appearing sources of uncertainty. Uncertainty caused by the CSA gain factor becomes a most contributing part in the high-current range (up to 100 mA). The temperature uctuation inuence on measurement uncertainty is negligible when compared to the rest of the uncertainty sources in laboratory conditions. The inuence of the manufacturing tolerances (like 5% of capacitance) of key passive components could be reduced by inlaboratory calibration using the ordinary equipment. Otherwise, charging circuit resistance and capacitance manufacturing scattering would dominate the current measurement uncertainty. The current measurement uncertainty is mainly inuenced by the external components like CSA, RC circuit, and comparator. Therefore, the uncertainty analysis is not dependent on the type of FPGA. The results obtained are not specic to the particular FPGA used in prototype development.

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ilvinas Nakutis (M11) received the B.S. degree in electronics engineering, the M.S. degree in metrology and measurement engineering, and the Ph.D. degree in measurement engineering from the Kaunas University of Technology, Kaunas, Lithuania, in 1995, 1997, and 2001, respectively. Since 2001, he has been an Associate Professor with the Department of Electronic and Measurement Systems, Kaunas University of Technology. His major research interest is electrical measurements, designing with eld-programmable gate array, embedded-system power consumption, low-power systems, and digital signal processing. He is the author or coauthor of over 25 scientic papers.