Scientific Journal of Control Engineering

June 2013, Volume 3 Issue 3, PP.213-217

An Improved Algorithm for the Technology

Mapping Re-connection Based on Divide Set
Hai Zhu 1, 2# , Hongfeng Wang 1, Xiaoguang Wang 2
1. Computer Science and Technology, Zhoukou Normal University, Zhoukou 466001, China
2. Computer Science and Technology, Xidian University, Xian 710071, China
#

Email: zhuhai @mail.xjtu.edu.cn

Abstract
This paper proposes an improved algorithm for the technology mapping re-connection based on divided set. Through establishing
a two-dimensional plot, the algorithm prevents consolidated operating constraints from being affected by divide set computing,
and designs a heuristic algorithm to optimize area and delay. Therefore, an improved algorithm for the technology mapping reconnection is proposed. Experimental results show the algorithm can greatly increase the capability of re-connection compared
with the available local and global optimization method, in such a case that the running times required are the same.
Keywords: Divide Set; Re-Connection; Technology Mapping; Optimization Method

*
1, 2 1 2
1. 466001
2. 710071

[1][2]
(ATPG, Automatic Test Pattern Generation)(SPFD, Set of Pairs of Functions to be Distinguished)
[3][4] ATPG

[5]

[6]
(dominator) 1
SPFD [7] PLA [8][9]
*

(61103143)(2012M512008)
(2012HASTIT032
(zksyqn201309B)
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[10]
p0
GD

Dominator of wr

p1

Alternative wire

p2

wa

G2

Alternative wire

wa

G4

Target wire

G1

p1 p2 ... wr

G2

wr

S={(g11,g10),(g21,g20),...}

Target wire

(a)

(b)

1 SPFD (a)(b)

P0 K (P1,P2,,Pn, nK) n 2
p1->p2G2 G4 pi pi (POs)
pi
G6 p1 G4 G6
p2
(g1, g0)g10g00g1g00 f f (g1, g0)
1 g11 f1 g01 f=0
2 g11 f0 g01 f=1
3 f (g1a, g1b) 1 f (g2a, g2b)
G1
O1

G5
PIs

G2 P1

G6

P2

POs

G4
O2
G3

x3
x1 x2 0
1
1
0
0

1 x1xx23
1
0
1
1

0
1
1
0
0

g1a
1 x1xx23
1
0
0
0

g1b
0 1 x1xx23
0 0
0 1
0 0
0 0

g2a
0 1 x1xx23
0 0
0 0
1 0
1 0

0
0
0
0
0

g2b
1
0
0
1
0

SPFDP={(g11, g10), (g21, g20),, (gm1, gm0)} f SPFD

f SPFD 3 f SPFD P={(g1a, g1b), (g2a, g2b) }
SPFD 2
(PIs)(POs)(
)
SPFD 3
Oi SPFD P={(g1, g0)} g1 Oi
g1fOig0g1'
SPFD SPFD
SPFD SPFD SPFD
SPFD
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1.1

SPFD SPFD
SPFD SPFD P={(g11, g10), (g21, g20),, (gm1,
gm0)} f P P gi11 f1gi01 f
0 g1

i1

i 1

g0

i0

(g1, g0) SPFD

i 1

SPFD SPFD
SPFD {(g11, g10), (g21, g20),, (gm1, gm0)} G
SPFD g1

i1

i 1

g0

i0

SPFD

i 1

(g11, g20)(gm1, g10) G SPFD

G SPFD P={(g11, g10), (g21, g20),, (gm1, gm0)}

f1,f2,,fn f1,f2,,fn g=F(f1,f2,,fn) P

gg11+g10+g21+ g20+gm1gm0

(1)

000 = f1'f2'fn'g
001 = f1f2'fn'g

(2)

111=f1f2fng
S S 2n (2)
i agi1 bgi0 a b
S g=F(f1,f2,,fn){(g11, g10), (g21, g20),, (gm1, gm0)}
SPFD

[7] SPFD SPFD

SPFD 2 SPFD SPFD
SPFD[7] SPFD[5][6] SPFD
f1,f2,,fn

G1 wr wr GD
G1 wr G1
G1 GD
GD SD SD LUT
wr
3 SD wa GD SD
wa wr wa
1) 3 4 wr wr G1

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1.2
SD GD
GD

0=f1'f2'fn'
1=f1'f2'fn

(3)

2n-1=f1f2fn
GD SPFD P={(g1, g0)} GD (4)
2n -1

G=F(f1 ,f 2 ,...,f n )= k ii

(4)

i=0

ig1 ki=1 ig0 ki=0

GD
GD

1.3
SPFD SPFD SPFD SPFD

SPFD pi
SPFD SPFD
SPFD SPFD

p p

CUDD[11] ROBDD SPFD

SIS[12] 4 MCNC
1 1
13.6%
58.9%
1 4

C1908
C432
alu4
dalu
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423
538
939
1338
244

78
154
277
468
71

99
183
419
704
99

113
202
512
731
109

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44.9%
31.2%
84.8%
56.2%
53.5%

14.1%
10.4%
22.2%
3.8%
10.1%

 1 4

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alu2
alu2
example2

557
510
510
433

164
179
179
85

222
253
253
136

258
297
297
160

57.3%
65.9%
65.9%
88.2%

16.2%
17.4%
17.4%
17.6%

58.9%

13.6%

SPFD

SPFD

REFERENCES
[1]

S.-C. Chang, M Marek-Sadowska, and K-T Cheng. Perturb and Simplify: Multilevel Boolean Network Optimizer. IEEE Trans
CAD of ICAS, Vol. 15, No. 12, Dec 1996, pp. 1494-1504

[2]

,,. FPGA [J]. ,2012,24(8):10271037

[3]

Alastair M S,George A C,Peter Y K, et al.An Automated Flow for Arithmetic Component Generation in Field Programmable Gate
Arrays. ACM Transactions on Reconfigurable Technology and Systems. 2008

[4]

R.Huang, Y.Wang, and K.-T.Cheng. LIBRA-a Library Independent Framework for Post-Layout Performance Optimization. In
International Symposium on Physical Design, p.135-140, 1998

[5]

S.Yamashita, H.Sawada and A.Nagoya. A New Method to Express Functional Permissibilities for LUT based FPGAs and Its
Applications. In International Conference on Computer Aided Design, p. 254-261, 1996

[6]

J.Cong, Y.Lin and W.Long. SPFD-based Global Rewiring. FPGA 02, Feb 24-26, 2002, Monterey, California, USA

[7]

S.Sinha and R.K. Brayton. Implementation and Use of SPFDs in Optimizing Boolean Networks. In International Conference on
Computer Aided Design, p. 103-110, 1998

[8]

, , . FPGA [J]. ,2011,39(11):2507-2512

[9]

J. -M. Hwang, F. - Y. Chiang, and T.- T. Hwang. A Re-engineering Approach to Low Power FPGA Design Using SPFD. In
Design Automation Conference, p. 722-725, 1998

[10] Jamieson P, Kent K B, Gharibian F, et al. Odin II-Anopen-Source Verilog HDL Synthesis Tool for CAD Research. 18th IEEE
Annual International Symposium on Field-programmable Custom Computing Machines. 2010
[11] Fabio Somenzi. CUDD: CU Decision Diagram Package Technique Report, Dept. of ECE, Univ. of Colorado at Boulder, 1998
[12] E. Sentovich, et al. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Dept. EECS, UC
Berkeley, 1992

1978-

1981-

Email: whfwlj202868@163.com

Email: zhuhai@mail.xjtu.edu.cn

1981-

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