Scientific Journal of Control Engineering

August 2013, Volume 3, Issue 4, PP.282-287

Design of Multi-Processor Loading System Based

on the FPGA and DSP Signal Processing Board
Junshan Gao, Shan Lu, Xiao Xiao
School of Automation, Harbin University of Science and Technology, Harbin 150080, China
Email:

junshangao@hrbust.edu.cn

Abstract
Underwater acoustic signal processing system mostly adopts multi-processor structures due to its requirement for real-time data
processing and large amount of data processing. The way of the multi-processor loads and time series are carefully designed
concerning the loading stability and configuration of loading data storage while power is on. This paper describes a multiprocessor loading method based on FPGA associated with DSP architecture to deal with systems electrified sequence loading,
loading method of each processor, storage of loaded code, data flow mode and other aspects. Dynamic configuration on FPGA and
DSP has been realized, and the system stability is enhanced. It also omits configuration of specific FLASH chip under the
application of FPGA or other processors by coordinating system resources.
Keywords: Multi-Processor; Loading; FPGA, DSP; Memory Cyclical Multiplexing

FPGA+DSP

150080

FPGA+DSP

FPGADSP FPGA FLASH

FPGADSP

FPGA+DSP

FPGA DSP
EPROM FLASH
PCB
DSP
FPGA DSP DSP RAM
FLASH DSP FLASH FLASH 0x0
DSP FPGA Flash FPGA
FPGA FPGA DSP DSP DSP FPGA DSP
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 FLASH DSP EPROM

1 VC DSP(ADSP BF547)

FPGA(xilinx XC6SLX75) DSP(ADSP TS101)(W5300)NOR FLASH DDR SDRAM

DSP FLASH.dpj DSP BF547.dpjFPGA FPGA.ise DSP
TS101.dpj Panel.exe
DSP

BF547.dpj

W5300

BF547.ldr

VC

FPGA.hex Panel.exe

FLASH

FPGA
FPGA.ISE

DSP
TS101.dpj

TS101.ldr

BF547 FLASH

BF547

TS101

DSP
TS101.dpj

BF547 FPGA TS101

BF547
BF547.dpj
FPGA
TS101

FPGA
FPGA.ISE

W5300

DDR
SDRAM

TS101

NORFLASH

BRAM

TS101
DSP
TS101.dpj

FPGA

DDRSDRAM

BF547

FPGA
TS101

BRAM

2 TS101

1 W5300 VC BF547 FLASH

DSP BF547.ldrFPGA FPGA.bin DSP TS101.ldr
BF547 DDR SDRAM FLASH
FLASH
BF547 0x20000000 BF547 0x20000000
FLASH BF547.ldr
2 DSP BF547 BOOT ROM BOOT 0x20000000
BF547 FLASH BF547
3 DSP BF547 FPGA BF547 FLASH FPGA
slave selectMAP FPGA DONE FPGA

4 TS101 FLASH

FPGA 64K RAM TS101 BF547

TS101 2 FPGA BF547 TS101
FLASH TS101 BF547 TS101
FPGA TS101 BF547
RAM BF547 TS101 TS101

FPGA Xlinx ISE FPGA.bin DSP VisualDSP++ BF547.ldr

TS101.ldr VC
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BF547 socket TCP socket
socket VC socket BF547
VC

3 BF547 FLASH
DDR SDRAM FLASH
Block 0 header

0x55aa

OFFSET 0x0000

OFFSET 0x0002

OFFSET 0x0004

OFFSET 0x0006

OFFSET 0x0008

Block 0 data
Block 1 header
Block 1 data

OFFSET 0x000a

3 FLASH

FLASH BF547
BF547 4 BMODE03 16 FLASH

BMOD13 BMOD0 3.3V

BMOD[3:0] 0001 FLASH BF547 AMS0 NORFLASH CE
FLASH BF547 0x20000000
BF547.ldr FLASH
0xEF000000 BOOT ROM BOOT ROM BOOT
BOOT 0x20000000 FLASH
8 8 DMACODE DMA
DMA

0xFFA00000

FPGA
Xilinx spartan6 FPGA (master serial)(master

selectMAP)(slave serial)(slave selectMAP)(JTAG) FPGA

CCLK PROG INIT DONE

CSI WRITE D150
DSP CCLK DSP AWE CSI DSP
AMS1 AMS1 FPGA GPIO FPGA M1
M0 4
1
FPGA PROG 40us INIT
FPGA PROG INIT
2
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 WRITE DSP FLASH FPGA FPGA

BF547 FPGACSI AWE AWE
AWE CCLK CCLK FPGA
FPGA CRC FPGA CRC
INIT FPGA INIT

3
0 CCLK DONE DONE
WRITE FPGA FPGA CCLK
FPGA 5

PROGRAM

3.3V 3.3V 3.3V 3.3V 3.3V

40us

20K 20K 20K 20K 20K

PROGRAM

GPIO1
GPIO2
GPIO3
BF547 GPIO4

PROGRAM
INIT
WRITE

AWE
D15-0

INIT=1

DONE FPGA
3.3V
CSI
M1
CCLK
M0
DIN

AMS1

DONE=1
WRITE

WRITE

FPGA

INIT=0

5 FPGA

TS101
TS101 EPROM(FLASH)

BF547 FPGA BF547 IO 1.2V TS101

BF547 IO 3.3V TS101 BF547 IO
RESERT BMS BF547 DMA FLASH TS101
DDR SDRAM FPGA RAM DSP DSP
64K A, B, C, D4 16K 6
DMA DDR SDRAM TS101 16K
4
BF547 TS101 RESET TS101
BMS BMS EPROM EPROM
BF547 RESET BMS FLASH
TS101
TS101 32K C FPGA BF547
BF547 TS101 DMA 16K
A 6 A C, D TS101
D FPGA BF547BF547 16K
B TS101 BF547 16K
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 BF547 TS101
TS101 TS101 7
BF547

TS101
TS101
RESERT
BMS

TS101

BF547

64K
RAM

BF547

RESERT

N
RAM

BMS=0

TS101
CFPGA
BF547

BF547FLASH
TS101
DDR

TS101
RAM

BF547
16k
RAM

FPGA
BF547

N TS1011

7 TS101

1 IO FPGA

DSP LED 8

8 LED

2FPGA DONE FPGA

FPGA BF547 DONE DONE

TS101 IOBF547
FPGA 9 5V
FPGA DONE TS101 5V
DONE FPGA TS101
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 TS101 FPGA DSP

VC DSP

FLASH DSP FLASH

PCB

REFERENCES
[1]

Analog Devices Inc. ADSP-BF54x Blackfin Processor Hardware Reference.Revision 1.0, August 2010

[2]

Analog Devices Inc. ADSP-TS101S TigerSHARC. 200341

[3]

Analog Devices Inc. ADSP-TS101 TigerSHARC Processor Hardware Reference. Revision 1.1, May 2004

[4]

Xilinx Inc. Spartan-6 FPGA Configuration User Guide. UG380 (v2.4) June 27, 2012

[5]

, , . TS101 DSP Flash[J]. . 2006, 32(21): 270-272

1962-

1987-
1987-

Email: junshangao@hrbust.edu.cn

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