VLSI projects: VLSI IMAGE PROCESSING PROJECT TITLES

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform An Efficient denoising Architecture for Removal of Impulse Noise in Images Chaos-Based Security Solution for Fingerprint Data During Communication and Transmission Cognition and Removal of Impulse Noise With Uncertainty Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA Fast Higher-Order MR Image Reconstruction Using Singular-Vector Separation Interference Removal Operation for Spread Spectrum Fingerprinting Scheme New Families of Fourier Eigen functions for Steerable Filtering Robust Watermarking of Compressed and Encrypted JPEG2000 Images VLSI COMMUNICATION SYSTEMS PROJECT TITLES A Novel Filter-Bank Multicarrier Scheme to Mitigate the Intrinsic Interference Application to MIMO Systems A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX Cooperative Beamforming for Cognitive Radio Networks-A Cross-Layer Design Curvature Based ECG Signal Compression for Effective Communication on WPAN Distributed Coordination Protocol for Ad Hoc Cognitive Radio Networks Dynamic Resource Allocation in MIMO-OFDMA Systems with Full-Duplex and Hybrid Relaying Good Synchronization Sequences for Permutation Codes High-Throughput Soft-Output MIMO Detector Based on Path-Preserving TrellisSearch Algorithm Low Complexity Transmitter Architectures for SFBC MIMO-OFDM Systems Low-Complexity Iterative Channel Estimation for Turbo Receivers Novel Interpolation and Polynomial Selection for Low-Complexity Chase SoftDecision Reed-Solomon Decoding Power Management of MIMO Network Interfaces on Mobile Systems Reconfigurable Adaptive Singular Value Decomposition Engine Design for HighThroughput MIMO-OFDM Systems

 Spectrum Sensing in the Presence of Multiple Primary Users Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications The Design of Hybrid Asymmetric-FIR_Analog Pulse-Shaping Filters Against Receiver Timing Jitter Transmission of 4-ASK Optical Fast OFDM With Chromatic Dispersion Compensation VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter VLSI AUDIO/SPEECH SIGNAL PROCESSING PROJECT TITLES A Low-Complexity Design for an MP3 Multi-Channel A Wiener Filter Approach to Microphone Leakage Reduction in CloseMicrophone Applications Enhancement of Single-Channel Periodic Signals in the Time-Domain Musical-Noise-Free Speech Enhancement Based on Optimized Iterative Spectral Subtraction Speaker and Noise Factorization for Robust Speech Recognition State-Space Frequency-Domain Adaptive Filtering for Nonlinear Acoustic Echo Cancellation Telephone Channel Compensation in Speaker Verification Using a Polynomial Approximation in the Log-Filter-Bank Energy Domain VLSI CRYPTOGRAPHY PROJECT TITLES A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL A Formal Approach to Designing Cryptographic Processors Based on GF(2^m) Arithmetic Circuits A Novel Architecture for VLSI Implementation of RSA Cryptosystem An efficient FPGA implementation of the Advanced Encryption Standard algorithm Construction of Optimum Composite Field Architecture for Compact HighThroughput AES S-Boxes Efficient FPGA Implementations of Point Mult on Binary Edwards & Generalized Hessian Curves Using FPGA Hardware of the LSB Steganography Method Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes

 VHDL Implementation of a Flexible and Synthesizable FFT Processor VLSI SIGNAL PROCESSING PROJECT TITLES A Highly-Digital VCO-Based ADC Using Phase Interpolator & Digital Calibration A Low-Power Low-Cost Design of Primary Synchronization Signal Detection A Novel Approach for Motion Artifact Reduction in PPG Signals Based on AS-LMS Adaptive Filter A Single-Pass-Based Localized Adaptive Interpolation Filter for Video Coding Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation Design of Digit-Serial FIR Filters Algorithms, Architectures, and a CAD Tool Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic Implementation of PSK and QAM demodulators on FPGA On the BIBO Stability Condition of Adaptive Recursive FLANN Filters With Application to Nonlinear Active Noise Control Pipelined Parallel FFT Architectures via Folding Transformation Platform-Independent Customizable UART Soft-Core Real Time Hardware Co-simulation of Edge Detection for Video Processing System Resource-Efficient FPGA Architecture and Implementation of Hough Transform VLSI Architecture of Arithmetic Coder Used in SPIHT VLSI POWER ELECTRONICS CONTROL PROJECT TITLES Design and Implementation of a New Multilevel Inverter Topology Digital Filters for Fast Harmonic Sequence Component Separation 3Ph Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic A Filter Bank and a Self-Tuning Adaptive Filter for the Harmonic and Inter harmonic Estimation in Power Signals Fully FPGA-Based Sensorless Control for Synchronous AC Drive Using an Extended Kalman Filter

 Synchronous FPGA-Based High-Resolution Implementations of Digital PulseWidth Modulators VLSI LOW POWER DESIGN PROJECT TITLES Design of Low Voltage Low Power Operational Amplifier Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep Submicron Circuits Low-Power Pulse-Triggered Flip-Flop Design With Conditional PulseEnhancement Scheme Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits Single Phase Clocked Quasi Static Adiabatic Tree Adder Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design VLSI SECURITY & SYSTEM GENERATOR PROJECT TITLES A Novel Non-payment Vehicle Searching Method for Multilane-Free-Flow Electronic-Toll-Collection Systems Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE Implementation of a Home Automation System through a Central FPGA Controller New Clock Generation Techniques for Synchronous Sampling of 16-QAM RF Signals Real Time Smart Car Lock Security System Using Face Detection and Recognition Simulation and Implementation of a BPSK Modulator on FPGA

Interfaces
RS-232,JTAG,I2C,EPP,SPI,PCI,PCI Express,10BASE-T LED displays,R/C servos,Text LCD module,Quadrature decoder PWM and one-bit DAC,Debouncer,Crossing clock domains The art of counting External contributions Advanced Digital oscilloscope Graphic LCD panel,Direct Digital Synthesis,CNC steppers Spoc CPU core