Electronic Devices and Circuits 2-1 N-D-12

QP.1 Electronic Devices and Circuits (Nov./Dec.
-2012, R09) JNTU-Hyderabad

( JNTU-Hyderabad ) B.Tech. II-Year I-Sem.
R09
Solutions
Code No: A109210203
Jawaharlal Nehru Technology University, Hyderabad
B.Tech. II Year I Semester Examinations
November/December - 2012
ELECTRONIC DEVICES AND CIRCUITS
( Common to BME, CSE, EEE, ECE, E.COMP.E, EIE, ETM, IT, ICE, MCT )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. (a) Sketch V-I characteristics of a PN diode for the following conditions:
(i) R
f
= 0, V
= 0, R
r
=
(ii) R
f
= 0, V
= 0.6 V, R
r
=
(iii) R
f
= Non-zero, fixed value, V
= 0, R
r
=
(iv) R
f
= 0.6 V, R
r
=
Where V
is the cut-in voltage, R

f
is the forward dynamic resistance and R
r
is the reverse dynamic resistance of
the diode. (Unit-I, Topic No. 1.3)
(b) Find the voltage drop across each of the silicon diodes shown in figure at room temperature. Assume that
reverse saturation current flows in the circuit and the magnitude of the reverse breakdown voltage is greater
than 5 V. (Unit-I, Topic No. 1.3)
+
5 V
D
1
D
2
I
1
I
2
+
5 V
D
1
D
2
I
1
I
2
Figure
2. (a) In a full-wave rectifier with capacitor filter, show that the ripple voltage is inversely proportional to the capacitance
of the capacitor and is proportional to the load current. Calculate the ripple voltage, when C = 100 F and
I
D.C
= 10 mA. The A.C input voltage to the rectifier is V
m

sin 314t. (Unit-II, Topic No. 2.3)
(b) Draw the circuit of zener voltage regulator. Explain its operation with neat characteristics and also derive
expressions for minimum and maximum values of source resistor for the zener diode to work as a voltage
regulator. (Unit-II, Topic No. 2.5)
3. (a) Explain early effect and its consequences in a BJT. Also draw the Ebers Moll model of a PNP transistor.
(Unit-III, Topic No. 3.2)
(b) In the circuit shown in figure, a silicon transistor with = 100, V
BE
= 0.7 V and V
CEsat
= 0.2 V is used. Determine
whether the transistor is operated in active region or in saturation region. (Unit-III, Topic No. 3.2)
QP.2 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year I-Sem. ( JNTU-Hyderabad )
2 k
3 k
50 k
5 V
10 V
Q
2 k
3 k
50 k
5 V
10 V
Q
Figure
4. (a) With neat diagram and necessary equations, explain how the variations in V
BE
compensated with the variations
in temperature. (Unit-IV, Topic No. 4.3)
(b) Design a self bias circuit using silicon transistor to achieve a stability factor of 10, with the following specifications:
V
CC
= 16 V, V
BE
= 0.7 V, V
CEQ
= 8 V, I
CQ
= 4 mA and = 50. (Unit-IV, Topic No. 4.2)
5. (a) With neat diagrams and necessary equations, explain the effect of coupling capacitor and bypass capacitor on
the performance of an amplifier at low-frequencies. (Unit-V, Topic No. 5.1)
(b) In a single stage CE amplifier circuit with unbypassed emitter resistor, R
C
= 10 k, R
E
= 1 k and R
S
= 0.5 k. The
h-parameters of the transistor used are h
ie
= 1.1 k, h
fe
= 50, h
oe
= 25 A/V and h
re
= 2.5 10
4
. Find R
i
and A
V
.
(Unit-V, Topic No. 5.2)
6. (a) Draw the basic structure and circuit arrangement of a P-channel metal oxide semiconductor field effect transistor
in enhancement mode. Explain the drain and transfer characteristics. (Unit-VI, Topic No. 6.2)
(b) Explain the procedure to obtain the small-signal equivalent circuit of a field effect transistor with necessary
equations. Also draw the small-signal model. (Unit-VI, Topic No. 6.1)
7. (a) What are the requirements of FET biasing? Verify these requirements in source self-bias circuit.
(Unit-VII, Topic No. 7.2)
(b) A common source FET amplifier circuit shown in figure with unbypassed R
s
has the following circuit parameters:
R
d
= 15 k, R
S
= 2.5 k, R
g
= 1 M, r
d
= 100 k, I
DSS
= 10 mA, VP = 5 V and V
DD
= 20 V. Calculate g
m
and A
V
.
(Unit-VII, Topic No. 7.1)
R
g
R
s
R
d
V
DD
V
0
+
V
i R
g
R
s
R
d
V
DD
V
0
+
V
i
Figure
8. (a) Draw the structure and two-transistor model of SCR, explain various methods of triggering an SCR.
(Unit-VIII, Topic No. 8.3)
(b) With neat sketches, explain the principle of operation of Schottky barrier diode. (Unit-VIII, Topic No. 8.2)
QP.3 Electronic Devices and Circuits (Nov./Dec.-2012, R09) JNTU-Hyderabad
Q1. (a) Sketch V-I characteristics of a PN diode for the following conditions:
(i) R
f
= 0, V

= 0, R
r
=
(ii) R
f
= 0, V

= 0.6 V, R
r
=
(iii) R
f

= 0, R
r
=
(iv) R
f

= 0.6 V, R
r
=
Where V

is the cut-in voltage, R
f
is the forward dynamic resistance and R
r
is the reverse
dynamic resistance of the diode.
Answer : Nov./Dec.-12, (R09), Q1(a)
For answer refer Dec.-11, Set-1, Q1(b).
(b) Find the voltage drop across each of the silicon diodes shown in figure at room temperature.
Assume that reverse saturation current flows in the circuit and the magnitude of the reverse
breakdown voltage is greater than 5 V.
+
5 V
D
1
D
2
I
1
I
2
+
5 V
D
1
D
2
I
1
I
2
Figure
Answer : Nov./Dec.-12, (R09), Q1(b)
Given that,
For a circuit with two diodes shown in figure,
Reverse saturation current, I
0
> 5 V
Room temperature, T = 300 K
Voltage drop across each diode, V = ?
The given circuit arrangement is shown in below figure,
+
5 V
D
1
D
2
I
1
I
2
+
5 V
D
1
D
2
I
1
I
2
Figure
SOLUTIONS TO NOV./DEC.-2012, R09, QP
The general current equation (I) is given by,
I = ) 1 (
/
0
T
V V
e I
Where,
= 2 for silicon
V
T
= Volt-equivalent of temperature =
600 , 11
T
=
600 , 11
300
= 0.0259 V
Since reverse saturation current is flowing through
the diode, I = I
0
I
0
= I
0
(e
V/20.0259)
1)
I
0
= I
0
(e
V/0.0518
1)
1 = e
V/0.0518
1
2 = e
V/0.0518

2
log
e
=
0518 . 0
V
(0.693)(0.0518) = V
V = 0.0359 Volts
Volts 0359 . 0 diodes, each across drop Voltage V
Q2. (a) In a full-wave rectifier with capacitor
filter, show that the ripple voltage is
inversely proportional to the capaci-
tance of the capacitor and is propor-
tional to the load current. Calculate the
ripple voltage, when C = 100 F and
I
DC
= 10 mA. The A.C input voltage to
the rectifier is V
m
sin 314 t.
For answer refer Unit-II, Q16.
Calculation of Ripple Voltage (V
r
)
Given that,
For a full-wave rectifier with capacitor filter,
Capacitor, C= 100 F
I
DC
= 10 mA
A.C input voltage, V
i
= V
m
sin 314t
Ripple voltage, V
r
= ?
The expression for calculating ripple voltage is given
as,
fC
I
V
DC
r
2
... (1)
Substituting the given values in equation (1), we get,
V
r
=
6
3
10 100 975 . 49 2
10 10
[Q = 314, 2f = 314, f =
2
314
= 49.975]
=
975 . 49 20
10
6 3
+
=
975 . 49 20
10
3
V 001 . 1
r
V
(b) Draw the circuit of zener voltage regula-
tor. Explain its operation with neat char-
acteristics and also derive expressions for
minimum and maximum values of source
resistor for the zener diode to work as a
voltage regulator.
For answer refer Unit-II, Q26.
Expressions for Minimum and Maximum Values of Source
Resistor
The voltage regulator circuit using a zener diode is
shown in below figure.
I
2
I
L
+
V
Z
R
S
V
S
+
R
L
I
2
I
L
+
V
Z
R
S
V
S
+
I
2
I
L
+
V
Z
R
S
V
S
+
R
L
Figure
From the circuit, we get,
I
S
= I
L
+ I
Z
And,
I
S
=
S
Z S
R
V V
=
S
Z S
R
V V
= I
L
+ I
Z
I
Z
= L
S
Z S
I
R
V V
,
_

The maximum zener current allowed by the zener
diode is given by,
I
Z(max)
=
(min)
(max)
L
S
Z S
I
R
V V
... (1)
The minimum zener current applied to the zener
diode is given by,
I
Z(min)
=
(max)
(min)
L
S
Z S
I
R
V V
... (2)
The maximum source resistance required to limit the
zener current is obtained as,
From equation (1),
I
Z(max)
= (min)
(max)
(max)
L
S
Z S
I
R
V V

(max)
(max)
S
Z S
R
V V
= I
Z(max)
+ I
L(min)

(min) (max)
(max)
(max)
L Z
Z S
S
I I
V V
R
+

The minimum source resistance require to limit the
zener current is obtained as,
From equation (2),
I
Z(min)
= (max)
(min)
(min)
L
S
Z S
I
R
V V

(min)
(min)
S
Z S
R
V V
= I
Z(min)
+ I
L(max)

(max) (min)
(min)
(min)
L Z
Z S
S
I I
V V
R
+

Therefore, the zener diode operates as a perfect
voltage regulator when,
R
S(min)
< R
S
< R
S(max)
Q3. (a) Explain early effect and its conse-
quences in a BJT. Also draw the Ebers
Moll model of a PNP transistor.
For answer refer Unit-III, Q13, Q14.
(b) In the circuit shown in figure, a silicon
transistor with = 100, V
BE
= 0.7 V and
V
CEsat
= 0.2 V is used. Determine whether
the transistor is operated in active
region or in saturation region.
2 k
3 k
50 k
5 V
10 V
Q
2 k
3 k
50 k
5 V
10 V
Q
Figure
Given that,
For a silicon transistor connected in CE
configuration,
= 100
V
BE
= 0.7 V
V
CE(sat)
= 0.2 V
Region of operation of transistor = ?
The given circuit arrangement is shown in figure
below,
2 k
3 k
50 k
5 V
10 V
Q
2 k
3 k
50 k
5 V
10 V
Q
Figure
From figure,
V
BB
= 5 V
V
CC
= 10 V
R
B
= 50 k
R
C
= 3 k
R
E
= 2 k
As the base is forward biased, the transistor is not in
cut-off region.
For a transistor to be in active region, V
CE
(which is
equal to V
C
, as the emitter is grounded) must be positive.
The expression for collector voltage is,
V
C
= V
CC
I
C
R
C
... (1)
Where, I
C
= I
B
... (2)
And, I
B
=
B
on BE BB
R
V V
) (
=
3
10 50
7 . 0 5
(Q V
BE
for Si = 0.7 V)
=
3
10
50
3 . 4
= 0.086 10
3
A
mA 086 . 0
B
I
On substituting I
B
value in equation (2), we get,
I
C
= I
B
I
C
= 100 0.086 10
3
I
C
= 0.086 10
1
A
A 0086 . 0
C
I
On substituting corresponding values of equation
(1), we get,
V
C
= 10 (0.0086)(3 10
3
)
= 10 25.8
= 15.8 V
V 8 . 15
CE C
V V
As the collector-to-emitter voltage (V
CE
) is negative,
the transistor is operated in saturation region.
Q4. (a) With neat diagram and necessary
equations, explain how the variations
in V
BE
compensated with the variations
in temperature.
For answer refer Unit-IV, Q23, Topic: Diode Compen-
sation for V
BE
.
(b) Design a self bias circuit using silicon
transistor to achieve a stability factor of
10, with the following specifications: V
CC
= 16 V, V
BE
= 0.7 V, V
CEQ
= 8 V, I
CQ
= 4 mA
and = 50.
Given that,
For a self bias circuit,
Stability factor, S = 10
V
CC
= 16 V
V
BE
= 0.7 V
V
CEQ
= 8 V
I
CQ
= 4 mA
= 50
The self bias circuit is as shown in figure (1).
R
1
R
2
R
E
V
BE
I
E
= (I
B
+ I
C
)
I
B
V
CC
I
C
R
C
V
o
R
1
R
2
R
E
V
BE
I
E
= (I
B
+ I
C
)
I
B
V
CC
I
C
R
C
V
o
Figure (1): Self Bias Circuit
To design a self bias circuit, we need to find,
(i) V
E
and I
BQ
(ii) R
E
, R
C
, R
2
and R
1
Step-1
To Determine V
E
To design self bias circuit with stability, it should
satisfy the following conditions,
V
E
0.1V
CC
... (1)
And R
2

10
E
R
.... (2)
Considering equation (1), we get,
V
E
= 0.1 V
CC
=
16
10
1
= 1.6 V
V 6 . 1
E
V
Step-2
To Determine I
BQ
The relation between I
BQ
and I
CQ
is given by,
I
BQ
=
CQ
I
(Q I
CQ
= I
B
)
=
50
10 4
3
= 0.08 mA
mA 08 . 0
BQ
I
Step-3
To Determine R
E
The emitter resistance (R
E
) is given by,
R
E
=
E
E
I
V
Where,
I
E
= I
B
+ I
C
R
E
=
C B
E
I I
V
+
=
CQ BQ
E
I I
V
+
=
) 10 4 10 08 . 0 (
6 . 1
3 3
+
=
3
10 08 . 4
6 . 1
= 0.392 10
3
R
E
= 0.4 10
3
k 4 . 0
E
R
Step-4
To Determine R
C
The expression for R
C
in a self-bias circuit is given by,
R
C
=
C
E CE CC
I
V V V
=
CQ
E CEQ CC
I
V V V
=
3
10 4
6 . 1 8 16

= 1.6 10
3
k 6 . 1
C
R
Step-5
To Determine R
2
2
in self bias circuit is given by,
R
2
=
C
E
I
V
10
=
CQ
E
I
V
10
=
3
10 4 10
6 . 1 50
= 2 10
3
k 2
2
R
Step-6
To Determine R
1
1
in self-bias circuit is given by,
R
1
=
,
_
+
1
2
BE E
CC
V V
V
R
=
1
]
1
+
1
7 . 0 6 . 1
16
10 2
3
= 11.913 10
3
12 10
3
k 12
1
R
Therefore, the self-bias circuit is now given as shown
in figure (2),
R
1
= 12 k
R
2
= 2 k R
E
= 0.4 k
V
CC
= 16 V
R
C
= 1.6 k
V
o
Q
R
1
= 12 k
R
2
= 2 k R
E
= 0.4 k
V
CC
= 16 V
R
C
= 1.6 k
V
o
Q
Figure (2)
Q5. (a) With neat diagrams and necessary
equations, explain the effect of
coupling capacitor and bypass capacitor
on the performance of an amplifier at
low-frequencies.
Effect of Coupling Capacitor on Low Frequency Response
The performance of an amplifier operating at low
frequency is highly effected by the coupling capacitors.
Whenever the frequency of operation increases, the
reactance (X
C
) of the coupling capacitor also increases. As a
result, an A.C drop is observed in the amplitude of the signal
operating at low frequencies.
The low frequency model for CE amplifier with coupling capacitor is as shown in figure (1).
V
i
h
fe
I
b
C
C
B
I
b
+
+
V
S
R
S
E
R
i
R
1
||R
2
R
L
C
V
o
+
V
i
h
fe
I
b
C
C
B
I
b
+
+
V
S
R
S
E
R
i
R
1
||R
2
R
L
C
V
o
+
Figure (1): Low Frequency Model for CE Amplifier with Coupling Capacitor
For large values of C
E
, the low frequency gain experiences no reduction in its value.
The lower 3-dB frequency is given as,
f
L
=
C i S
C R R ) ( 2
1
+
... (1)
Where,
C
C
= Coupling capacitor
R'
i
= R
1
|| R
2
|| R
1
R
i
=
'
+ + . considered is resistance series s capacitor' when ; ) 1 (

capacitor bypass emitter ideal for ;
CE fe ie
ie
R h h
h
Therefore, to achieve good low frequency response the value of C
C
must be large.
Effect of Bypass Capacitor on Low Frequency Response
C
E
is the emitter bypass capacitor which causes frequency response of an amplifier to break at a cut-off frequency,
f
c
and prevents the reduction of A.C gain by passing A.C signal current through it.
If C
E
would not have been there, A.C signal current would flow into R
E
making A.C signal gainless.
The gain falls at low frequency region because of coupling capacitors C
1
, C
2
, C
3
... and emitter bypass capacitor C
E1
,
C
E2
, C
E3
, C
E
.
~
R
o
C
E
~
R
o
C
E
f
A
m
A
m
0.707
f
A
m
A
m
0.707
Figure (2): Frequency Response
The bypass capacitor C
E
also effects the circuit performance at low frequency. The effect of C
E
is voltage drop
across C
C
will reduce V
i
with a drop in V
o
.
The C
E
avoids the loss in A.C signal gain of the stages.
The A.C voltage drop across R
E
reduces the gain. So, C
E
capacitor is connected across R
E
so that, all the A.C current
is passed through C
E
and decrease A.C voltage drop across R
E
, thus increasing overall gain.
The frequency at which the gain drops by a factor of
2
1
is lower 3 dB frequency, f
1
=
C R R
i s
) ( 2
1
+
.
(b) In a single stage CE amplifier circuit with unbypassed emitter resistor, R
C
= 10 k, R
E
= 1 k and
R
S
= 0.5 k. The h-parameters of the transistor used are h
ie
= 1.1 k, h
fe
= 50, h
oe
= 25 A/V and
h
re
= 2.5 10
4
. Find R
i
and A
V
.
Given that,
For a single stage CE amplifier with unbypassed emitter resistor,
R
c
= 10 k
R
E
= 1 k
R
S
= 0.5 k
h
ie
= 1.1 k
h
fe
= 50
h
oe
= 25 A/v
h
re
= 2.5 10
4
R
i
= ?
A
v
= ?
The circuit arrangement of common emitter amplifier with emitter resistor is shown in figure (1).
~
R
s
V
s
B
E
R
E
R
C
V
CC
+
+
V
o
V
i
C
+
~
R
s
V
s
B
E
R
E
R
C
V
CC
+
+
V
o
V
i
C
+
Figure (1)
The A.C equivalent circuit for CE amplifier with unbypassed emitter resistor is shown in figure (2),
~
V
s
E (1 A
I
) I
b
R
E
C
+
R
C
R
S
I
c
A
i
I
b
B
I
B
~
V
s
E (1 A
I
) I
b
R
E
C
+
R
C
R
S
I
c
A
i
I
b
B
I
B
iFigure (2))
The h-parameter equivalent circuit for the above circuit is shown in figure (3).
h
ie
(1 + h
fe
) I
b
Vs
+
R
S
B
I
b
I
c
h
fe
I
b
R
E
V
o
V
i
C
R
C
h
ie
(1 + h
fe
) I
b
Vs
+
R
S
B
I
b
I
c
h
fe
I
b
R
E
V
o
V
i
C
R
C
Figure (3)
Approximate Analysis
The expression for input resistance (R
i
) of a CE amplifier with unbypassed emitter resistor is given by,
R
i
=
b
i
I
V
= h
ie
+ (1 + h
fe
) R
E
= 1.1 10
3
+ (1 + 50) 1 10
3
= 1.1 10
3
+ 51 10
3
= 52.1 10
3

k 1 . 52
i
R
The expression for voltage gain is,
A
v
=
i
L i
R
R A
A
v
=
E fe ie
L fe
R h h
R h
) 1 ( + +
=
3 3
3
10 1 ) 50 1 ( 10 1 . 1
) 10 10 ( 50
+ +

(Q R
L
= R
C
)
=
51 ) 1 . 1 (
500
+
=
1 . 52
500
= 9.597
597 . 9
v
A
Q6. (a) Draw the basic structure and circuit arrangement of a P-channel metal oxide semiconductor
field effect transistor in enhancement mode. Explain the drain and transfer characteristics.
For answer refer Dec.-11, Set-1, Q6(a).
(b) Explain the procedure to obtain the small-signal equivalent circuit of a field effect transistor
with necessary equations. Also draw the small-signal model.
The circuit diagram of N-channel JFET is shown in figure (1).
V
DS
+ I
D
I
S
V
DD
+
D
+
V
GS
V
GG
+
I
G
G
S
V
DS
+ I
D
I
S
V
DD
+
D
+
V
GS
V
GG
+
I
G
G
S
Figure (1): Circuit Diagram of N-channel JFET
Small signal equivalent circuit of FET can be drawn in two models. The two models are current source and voltage
source. These models are analysed in common source configuration, as shown in figure (2) and figure (3) respectively.
V
ds
r
d
+
G
V
gs
S
g
m
V
gs
i
d
D
+
V
ds
r
d
+
G
V
gs
S
g
m
V
gs
i
d
D
+
Figure (2): Small Signal Current Source Model of FET

V
ds
r
d
+
G
V
gs
S
V
gs
i
d
D
+
V
ds
r
d
+
G
V
gs
S
V
gs
i
d
D
+
Figure (3): Small Signal Voltage Source Model of FET

The drain current (i
d
) of FET is a function of gate to source voltage (
gs
) and drain to source voltage (
ds
).
Considering varying currents and voltages for FET, i
d
is given as,
i
D
= f(
gs
,
ds
) ... (1)
The drain current (i
d
) is dependent on drain and gate voltages. Any changes in drain and gate voltages also changes
drain current. The corresponding change in drain current due to variations in gate and drain voltages is obtained by
expanding equation (1) using Taylors series.
i
d
=
ds
V
gs
d
i
1
1
]
1

gs
+
gs
V
ds
d
i
1
]
1

ds
... (2)
In the small signal notation, the incremental values are A.C quantities.
So,
i
d
= i
d
,
gs
=
gs
and
ds
=
ds
The equation (2) can be re-written as,
i
d
= g
m

gs
+
d
r
1

ds
... (3)
Where,
g
m
= Mutual conductance or transconductance
r
d
= Drain to source resistance.
The mutual conductance of FET is defined as,
g
m
=
ds
V
gs
d
i
1
1
]
1

ds
V
gs
d
i
1
1
]
1
=
ds
V
gs
d
i
,
_

ds
V
gs
d
m
i
g
1
1
]
1

The drain to source (output) resistance of FET can be defined as,
r
d
=
gs
V
d
ds
i
1
]
1

gs
V
d
ds
i
1
]
1

=
gs
V
d
ds
i
1
]
1

gs
V
d
ds
d
i
r
1
]
1

Amplification factor of FET can be defined as,
=
D
I
gs
ds
1
1
]
1

D
I
gs
ds
1
1
]
1

=
0
1
1
]
1

d
i
gs
ds

0
1
1
]
1

d
i
gs
ds
A relation between , r
d
and g
m
can be established
by making the drain current i
d
= 0 in equation (3).
i
d
= g
m

gs
+
d
r
1

ds
0 = g
m

gs
+
d
r
1

ds
g
m

gs
=
d
r
1

ds

gs
ds

= g
m
r
d

d m
r g
1
1
]
1
,
_

0 d
i
gs
ds
Q
Q7. (a) What are the requirements of FET
biasing? Verify these requirements in
source self-bias circuit.
Requirements of FET Biasing
The process of obtaining desired Q-point by giving
proper supply voltages and resistances is known as biasing.
The set of D.C voltage V
CEQ
and current I
CQ
are established
by properly choosing supply voltages and resistances,
which are responsible to produce distortion-free output by
operating transistor in active region.
Transistors have to be properly biased in order to
function as amplification stage. A transistor is biased by
setting the amount of D.C current that flows in the tube
when there is no signal present at the transistor base. This
D.C bias current can be set in a number of ways. The bias
point determines several things about a transistor
amplification stage. It determines the power output, amount
of distortion, the size of input signal that can be applied
before the output signal clips (head room), efficiency of the
stage, gain of the stage, noise of the stage and class of
operation (class A, AB etc.,). The proper bias point is a
trade-off between all of these factors and selecting the
optimum bias point can sometimes be difficult, and it will
vary depending on the amplification stage requirements.
Source Self Bias (Self bias)
The self-bias scheme is a biasing technique mostly
used in FETS. This configuration provides more assistance
in stabilizing the operating point even for the changes in
FET parameters.
The self-bias configuration of N-channel JFET is
shown in figure (1).
A.C input
signal
C
i
R
G R
S
C
C
A.C output
signal
R
D
V
DD
A.C input
signal
C
i
R
G R
S
C
C
A.C output
signal
R
D
V
DD
Figure (1)
Analysis of the Self-bias Circuit
The D.C equivalent of the self-bias circuit is shown
in figure (2).
+
+
R
S
I
S
= I
D
R
G
I
G
= 0
V
GS
V
DS
R
D
I
D
V
DD
+
+
R
S
I
S
= I
D
R
G
I
G
= 0
V
GS
V
DS
R
D
I
D
V
DD
Figure (2)
Applying Kirchoffs voltage law at the input side of
the circuit, we get,
V
GS
I
D
R
S
R
G
I
G
= 0
V
GS
= I
D
R
S
(
Q
I
G
= 0) ... (1)
Voltage at the source terminal is given by,
V
S
= V
G
V
GS
... (2)
V
S
= V
GS
(Q V
G
= 0)
V
S
= V
GS
= I
D
R
S
... (3)
(Q From equation (1))
Then, the expression for drain current (I
D
) of a JFET
is given by,
I
D
= I
DSS
2
1
1
]
1
P
GS
V
V
From equation (1), we get,
I
D
= I
DSS

2
1
1
]
1
+
P
S D
V
R I
... (4)
By applying Kirchoffs voltage law at the output side
of the circuit shown in figure (2), we get,
V
DD
I
D
R
D
V
DS
I
S
R
S
= 0
V
DS
= V
DD
I
D
(R
D
+ R
S
) [
Q
I
S
= I
D
] ... (5)
The graphical analysis can be obtained as shown in
figure (3).
V
GS
(V)
2
R I
S DSS

V
GSQ
I
DQ
2
I
DSS
I
D
(mA)
V
GS
(V)
2
R I
S DSS

V
GSQ
I
DQ
2
I
DSS
I
D
(mA)
Figure (3)
The operating point can be determined by drawing a
straight-line corresponds to equation (3) (i.e., V
GS
= I
D
R
S
)
on the transfer characteristics curve of JFET.
(b) A common source FET amplifier circuit
shown in figure with unbypassed R
s
has
the following circuit parameters:
R
d
= 15 k, R
S
= 2.5 k, R
g
= 1 M, r
d
= 100 k,
I
DSS
= 10 mA, V
P
= 5 V and V
DD
= 20 V.
Calculate g
m
and A
V
.
R
g
R
s
R
d
V
DD
V
0
+
V
i R
g
R
s
R
d
V
DD
V
0
+
V
i
Figure
Nov./Dec.-12, (R09), Q7(b)
Answer :
Given that,
For a common source FET amplifier,
R
d
= 15 k
R
s
= 2.5 k
R
g
= 1M
r
d
= 100 k
I
DSS
= 10 mA
V
p
= 5 V
V
DD
= 20 V
g
m
= ?
A
v
= ?
Then, the expression for transconductance of a
common source FET amplifier is given by,
g
m
=
DSS D
p
I I
V | |
2
... (1)
Where,
I
D
=
d
DD
R
V
I
D
=
3
10 15
20
I
D
= 1.333 10
3
On substituting the value of I
D
in equation (1), we
get,
g
m
=
) 10 10 )( 10 333 . 1 (
5
2
3 3

=
) 10 651 . 3 (
5
2
3
= 1.46 10
3
mho 10 46 . 1
3

m
g
And the expression for the voltage gain is given by,
d d
d
v
r R
R
A
+

... (2)
Where,
= r
d
.g
m
= 100 10
3
1.46 10
3
= 146
On substituting the value of in equation (2), we
get,
A
v
=
) 10 100 ( ) 10 15 (
10 15 146
3 3
3
+

=
115000
2190000
= 19.043
19.043
v
A
Q8. (a) Draw the structure and two-transistor
model of SCR, explain various methods
of triggering an SCR.
For answer refer Unit-VIII, Q5.
The triggering of SCR mainly classified into five
methods, they are,
1. Thermal triggering
2. Radiation triggering
3. Voltage triggering
4. dv/dt triggering
5. Gate triggering.
1. Thermal Triggering
In this triggering method, when the input voltage
level is very close to the breakdown voltage level, the SCR
gets turned ON with increase in temperature.
2. Radiation Triggering
The triggering method in which SCR is triggered by
the bombarding of photons, which forms an electron-hole
pair is referred as Radiation triggering.
The SCR which is turned ON by this triggering
method is referred as Light Activated SCR (LASCR).
3. Voltage Triggering
In this triggering method, the increase in forward
biased voltage level results in accumulation of electrons
and holes at the reversed biased junction which in turn
causes increase in blocking current. Therefore, SCR is turned
ON.
4. dv/dt Triggering
In this triggering method, SCR is turned ON when
the rate of rise of voltage increases above the critical rate of
rise of voltage.
5. Gate Triggering
This is one of the most easiest, simplest and useful
triggering technique of SCR.
The following are the important points to be
considered during the design of gate control circuit.
(a) An appropriate gate signal should be applied
to trigger SCR, when it is in forward biased
condition.
(b) Once the SCR is turned ON, gate signal should
be removed for reducing losses and higher
junction temperatures.
(c) During the reverse biased condition of SCR,
gate signal should not be applied.
(d) The characteristics of SCR can be improved by
applying negative voltage between gate and
cathode during OFF state of SCR.
There are three methods of triggering SCR by using
gate control, they are,
By D.C gate signal
By A.C gate signal
By pulsed gate signal.
By D.C Gate Signal
In this technique, SCR is triggered by applying D.C
gate signal of appropriate polarity and magnitude
between the gate and cathode.
By A.C Gate Signal
In this technique, SCR is triggered by applying A.C
gate signal between gate and cathode.
By Pulsed Gate Signal
By applying pulsed gate signal between the gate and
cathode SCR is triggered.
This technique has less losses when compare to other
techniques.
(b) With neat sketches, explain the principle
of operation of Schottky barrier diode.
For answer refer Unit-VIII, Q3.

Electronic Devices and Circuits 2-1 N-D-12

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Electronic Devices and Circuits 2-1 N-D-12

Uploaded by

Copyright:

Available Formats

QP.1 Electronic Devices and Circuits (Nov./Dec.

-2012, R09) JNTU-Hyderabad

is the cut-in voltage, R

+ + . considered is resistance series s capacitor' when ; ) 1 (

Figure (2): Small Signal Current Source Model of FET

Figure (3): Small Signal Voltage Source Model of FET

You might also like