UNIT-5 SUBSYSTEM DESIGN QUIZ QUESTIONS

1. For the 4X4 bit barrel shifter, the regularity factor is given by a. b. c. d. 8 4 2 16

2. The level of any particular design can be measured by a. b. c. d. SNR Ratio of amplitudes regularity quality

3. In tackling the design of system the more significant property is a. b. c. d. logical operations test ability topological properties nature of architecture

4. Any bit shifted out at one end of data word will be shifted in at the other end of the word is called a. b. c. d. end-around end-off end-less end-on

5. In the VLSI design the data and control signals of a shift register flow in a. horizontally and vertically

b. c. d.

vertically and horizontally both horizontally both vertically

6. The subsystem design is classified as a. b. c. d. first level top level bottom level leaf-cell level

7. The larger system design must be partition into a sub systems design such that a. b. c. d. minimum interdependence and inter connection complexity of interconnection maximum interdependence arbitarily chosen

8. To simplify the subsystem design, we generally used the a. b. c. d. interdependence complex interconnections regular structures standard cells

9. System design is generally in the manner of a. b. c. d. down-top top-down bottom level only top level only

10. a. b. c. d.

Structured design begins with the concept of hierarchy down-top design bottom level design complex function design

11. Any general purpose n-bit shifter should be able to shift incoming data by up to number of places are a. b. c. d. 12. a. b. c. d. 13. a. b. c. d. n 2n n-1 2n-1 For a four bit word, a one-bit shift right is equivalent to a two bit shift left three-bit shift left one bit shift left four-bit shift left The type of switch used in shifters is line switch transistor type switch crossbar switch gate switch

14. a. b.

The carry chain in adder is consist with cross-bar swith transmission gate

c. d.

bus interconncection pass transistors

15. a. b. c. d.

VLSI design of adder element basically requires EX-OR gate, Not and OR gates multiplexers, inverter circuit and communication paths multiplexers, EX-OR and NAND gates inverter circuits and communication paths

16. The number of basic cells required for an n-bit X n-bit multiplier is a. b. c. d. 17. a. b. c. d. The heart of the ALU is Register adder control bus I/O port (3n+1) (3n+1)2n

18. Carry line in adder must be buffered after or before each adder element because a. b. c. d. slow response of series pass transistors slow response of parallel line fast response of parallel pass transistors fast response of series line

19. The ALU logical functions can be obtained by a suitable switching of the a. b. c. d. carry line between adder elements sum line between adder elements carry line between shifter & buffer sum line between shifter & buffer

20. To fast an arithmetic operations, the multipliers and dividers is to use architecture of a. b. c. d. 21. a. b. c. d. parallel serial pipelined switched The number of bits increases in comparator then the height increases width grows linearly width reduces linearly height reduces

22. a. b. c. d.

The standard cell for an n-bit parity generator is n-1 bit cell one bit cell two bit cell n+1 bit cell

23. The parity information is passed from one cell to the next and is modified or not by a cell depending on the state of the

a. b. c. d.

previous information output line input lines next information

24. The parity information (pi) passed from one cell to the next is modified when the input line (Ai) is at the state of a. b. c. d. zero overline{A}i one independent of input line state

25. When cells of parity generator are butted together (indicate false statement) a. b. c. d. design rule errors are not present wastage of area is avoided inlet and outlet points of cells must be match up layer and position match is not necessary

26. The two output signals of comparator remain at zero as long as the two bits being compared are a. b. c. d. 27. a. b. c. same zero one different In the comparator the two inputs if A>B then the outputs are Ci=0 & Di=1 Ci=1 & Di=0 Ci=1 & Di=1

d. 28. a. b. c. d.

Ci=0 & Di=0 In the comparator the two inputs if A<B then the outputs are Ci=0 & Di=0 Ci=1 & Di=1 Ci=0 & Di=1 Ci=1 & Di=0

29. The width of n Where w is the width of leaf cell a. b. c. d. nw w (n-1) w n

bit

comparator

is

30. The main draw back of asynchronous counter with respect to VLSI is a. b. c. d. The output change with respect to clock edge counter stages are cacaded the last counter stage to settle can be quite large clocking of each stage is carried out by the previous stage

31. ONE/ZERO detection circuits for word width of less than 32 bits is the a. b. c. d. pseduo-nMOS OR gate pseduo-nMOS NOT gate pseduo-nMOS NOR gate nmos OR gate

32. The delay from the last changing output to the ripple zero/one detector is a a. b. c. d. constant one gate delay variable delay greater than two gate delays constantly increasing delay

33. The speed that sychronous up/down counter can operate is determined by the a. b. c. d. 34. a. b. c. d. ripple-carry time from the LSB to MSB substantially the clock time delay of registers settling time of counter Detecting all ones or all zeros on wide words require large fanout AND or OR gates large fanin AND or OR gates large fan in EX-NOR or EX-OR gates large fanout NOR or NAND gates

35. In zero/one detector, the delay to the output is porportional to (N is bit width of the word) a. b. c. d. N N2 -log N log N

36. Self-loading of large word widths in ONE/ZERO detectors is avoided by a. split into 8 or 16 bit chunks

b. c. d. 37. a. b. c. d. 38. a. b. c. d. 39. the a. b. c. d.

use large fan in gates use large word width pseudo-nMOS NOR gates use large fanout gates Binary counters are used to cycle through a sequence of Decimal numbers binary numbers hexa decimal numbers octal numbers An asynchronous counter has outputs that change at varying times with respect to the clock edge substantially the same clock time twice that of the clock edge time half time of the clock The clocking of each stage of ripple counter is carried out by common clock previous counter stage connected positive and negative cycles alternately master-slave flip-flop

1.

proper placement of memory elements makes maximum use of the a. b. c. d. available clock period cost of area power dessipation parasitics

2. a. b. c. d. 3. a. b. c. d. 4.

A design that requires high density memory is usually a single ship on chip partitioned into several chips DRAMS Random access memory at the chip level is classed as memory that has an access time dependent of the physical location of the data an access time independent of the physical loction of the data reading or writing of a particular datum with address examines a data word and compares this data with internally stored data The following memory examines data word and compares this data with internally stored data serial access memory random access memory content addressable memory shift registers memory The main characteristics of on chip memory is

a. b. c. d. 5.

a. b. c. d. 6. a. b. c. d. 7. a. b. c. d. 8. a. b. c. d. 9. a. b. c. d.

small and slow large and slow small and faster large and faster DRAM has a smaller layout and uses large power smaller layout and uses less power more power and slower more power and faster SRAM has a faster, more power and larger slower, more power and larger faster, less power and smaller faster less power and larger On chip memory is comes under the category of high density memory medium density memory low density memory large density memory On chip memory usually in the order of 10k bytes 50k bytes 1k bytes 100 k bytes

10. The simplest and safest way to use memory in a system is to treat it as a a. b. c. sequential component combinational component decoders

d.

NOR gates

11. Serial access memory at the chip level is classed as memory that has a. b. c. d. shift registers counters accesstime is independent of location of data internally stored data is used

12. The PLA provides a systematic and regular way of implementing multiple output functions of n variables in a. b. c. d. POS form SOP form complex form simple form

13. V(input variables) X P(product terms) PLA is to maintain generality within the constraints of its dimensions then for a. b. c. d. AND gate have n inputs and output OR gate must have P inputs AND gate have P inputs and output OR gate must have n inputs Both AND gate and OR gate have n inputs both AND and or gates have P inputs

14. A MOS PLA is realized by using the gate of a. b. c. d. AND OR AND-OR NOR

15. A CMOS PLA is realized by a. b. c. d. pseudo nmos NOR gate CMOS NOR gate pseudo nmos NAND gate CMOS NAND gate

16. The mapping of irregular combinational logic functions into regular structures is provided by the

a. b. c. d.

FPGA CPCD standard cells PLA

17. The general arrangement of PLA is a. b. c. d. AND/OR structure OR/AND structure NAND/NOR structure EX-OR/OR structure

18. V XP X Z PLA represents as a. V-no.of P-no.of Z-no.of gates V-no.of P-no.of Z- no.of AND gates V-no.of P-no.of Z-no.of output functions V-no.of P-no.of Z-no.of output functions input output variables functions

b.

gates OR gates

c.

input product

variables terms

d.

gates AND gates

19. To realize any finite state machine requirements, the PLA along with a. b. c. d. NOR gate is used feed back links is used NAND gate is used NOT gate is used

20. To reduce the PLA dimensions, the simplification must be done on a a. b. c. d. individual output basis multi-output basis individual product term individual input basis

21. The regularity of the PLA sturcture shows that both the AND and OR planes are constructed from

a. b. c. d.

different standard cells standard cells are not used same standard cells feed back control links

22. The behavior AND/OR structure of a system may be capured in a. b. c. d. hardware description language software language tabulation method state design model

23. VHDL differs from other software languages by including a. b. c. d. behaviour of system compilers, debuggers and simulatois syntax machine understanding language

24. The advantage of fuse-based FPGAS compared to other FPGAs is a. b. c. d. allows large number of interconnections complex fabrication process larger in size modified without changing hardware

25. Where the design is of moderate complexity and time to silicon is of paramount importance then the probably suitable approach is a. b. c. d. FPGA PLA standard cell PAL

26. A single time programmable FPGA is the type of a. b. c. fuse-based FPGA SRAM-FPGA EPROM-FPGA

d.

Flash based FPGA

27. The SRAM-FPGA's consists of a large array of programmable logic cells known as a. b. c. d. Erasable programmable logic devices-EPLD configurable logic blocks-CLB micro cells AND/OR array

28. The fabrication process of EPROM-FPGA is a. b. c. d. easy and high integration density easy and low integration density complex and high integration density complex and low integration density

29. The following is a chip whose final logic sturcture is directly configured by the end user a. b. c. d. gate array design field programmable logic standard cell design full custom design

30. FPGA can be programmed as per the a. b. c. d. positive logic negative logic users logic fixed logic

31. The logic cells in FPGA contains a. b. c. d. only combinational circuits only sequential circuits both combinational & sequential circuits only Flip-Flop circuits

32. The individual cells of FPGA are interconnected by a. AND gates and switches

b. c. d.

matrix of wires and programmable switches OR gates and non programmable switches AND & OR gates

33. The programming in fuse-based FPGAS is done by a. b. c. d. configurable logic blocks memory cell multiplexer closing antifuse switches

34. A slow rate control is used in the I/O block of CPLD because of a. b. c. d. matching with other parts suppressing the occurrence of the noise grounding the I/O pin global tree state control

35. Which part of the CPLD is programmed to pass the latched or unlatched, true or complement output to the external output a. b. c. d. AND gates of array OR gates of array I/O cell standard cell

36. A slow rate control in the I/O block of CPLD is used to make the rising and falling of the output pulse a. b. c. d. zero one faster slow

37. A macro cell in CPLD is composed of a. b. c. d. J-K flip-Flop R-S Flip-Flop T-Flip-Flop D-Flip-Flop

38. CPLD devices are used for design modification because these are a. b. c. d. reprogrammable non programmable always a fixed program design modificaions are not possible

39. CPLD is a devices of numeorus integrated SPLDs and interconnections between them is a. b. c. d. non programmable programmable used single SPLD permanent connections are used

40. To compose a circuit in case of CPLD, it has wiring among a. b. c. d. the pins the logic connection on printed board the function

41. CPLD is possible to rewrite it many times because a. b. c. d. it is records the contents of the circuit to the flash memory a standard cell is used it is a plastic loaded chip it is AND/OR array

42. The CPLD can be rewritable in about a. b. c. d. < 10times < 100 times < 1000times > 1000times

43. During programming of CPLD, the I/O pin is at the state of a. b. logic O logic 1

c. d.

high impedance open

44. The function block of CPLD consists of a. b. c. d. AND array, OR array and macro cell OR array, product term allocator and macrocell AND array, product term allocator and marcocell AND array, product term and OR array

45. In the standard cell, all the cells should have a. b. c. d. identical heights and widths identical heights and the widths of the cells may vary identical widths and the variable heights variable heights and widths

46. Cells in different rows of standard cells can be connected by using a. b. c. d. internal wires feed through cells intra wires route around a complete row

47. When a design is implemented in the standard cell design style a. b. c. d. only signal routing has to be done replacement of library cells change of the design fucntion change of placement of blocks

48. Standard cell designs are less area efficient than a full custom design due to a. b. c. d. feed through cells multiple cell rows fixed size of the cells lower clock rates

49. Where the design is of a reduced cost and include size memories the preferable approach is

a. b. c. d.

FPGA gate array logic standard cell full custom

50. Logic gates are placed in rows of standard cells of a. b. c. d. equal height equal width variable height constant width

51. Logic gate are placed in rows of standard cells are interconnected using a. b. c. d. internal wires intra wire routing channel switch box

52. Semicustom design using standard cells enable the designes to use a. b. c. d. a functional modules (available in library) a layout automatically generated an interconnections between cells only basic logic functions

53. In the standard cell design methodology a. b. c. d. each transistor is manually designed predefined logic and function blocks are available final logic structure is directly configured an array of unconnected logic gates

54. Standard cell designs are operate at a. b. c. higher clock rates and less area efficient lower clock rates and less area efficient lower clock rates and high area efficient

d.

higher clock rates and high area efficient

55. PAL16R8, here R denotes the a. b. c. d. number of inputs number of outputs active high presence of flip-flop

56. PAL10L8, here L denotes the a. b. c. d. active high active low number of inputs number of outputs

57. If one function depend on other functions in PAL then a. b. c. d. OR gate is used feed back is used ex-OR gate is used realization is not possible

58. One approach that is becoming more popular and feasible is to model chips as collections of a. b. c. d. standard cells no.of gates reprogrammable gate arrays semicustom design sub systems

59. Programmable array logic provide a convinient way of realizing a. b. c. d. combinational networks only sequential networks only both combinational and sequential network not used for realization

60. Programmable array logic is made up of a. programmable AND and OR array

b. c. d.

programmable AND and fixed OR array Fixed AND and programmable OR array Fixed AND and OR array

61. The number of product terms in PAL depends on a. b. c. d. number of AND gates number of OR gates number of addition of both AND and OR gate independent of number of gates

62. To realise the sequential networks in PAL, the type of flip-flop used is a. b. c. d. D flip-flop T flip-flop J-K flip-flop R-S flip-flop

63. The combination PAL devices with active-low outputs mean a. b. c. d. AND-OR logic AND-NOR logic AND-NAND logic NAND-OR logic

64. In order to realize a Boolean function with a combinational PAL device, the function must be expressed in a. b. c. d. POS form SOP form Standard form complex form

65. When the PAL sequential device has a tristate buffer at the output stage then the type of circuit implemented is a. b. c. d. sequential circuit product terms pos form combinational circuit

66. An interface description of design entity in VHDL must define the a. b. c. d. logical interface to the outside world internal operations organization of hardware logical definition

67. VHDL was developed for the VHSIC components to a. b. c. d. design and interchange format simulation and fault analysis only design description and simulation certification and architectural evaluation

68. The primary abstraction in VHDL is called a. b. c. d. interface description body description structural description design entity

69. Each port declaration of design entity in VHDL includes a a. b. c. d. hardware description port name, associated mode and type internal operations logical functions

70. The component declarations in VHDL include aninface description for each of the a. b. c. d. signals input port output/port logic gates

71. VHDL provides high-level definition and simulation of a. b. simple digital systems complex digital systems

c. d.

standall cell design systems analog systems

72. The design is commenced with a a. b. c. d. RTL description behavioral description logic description functional description

73. Generally logic optimization systems divide the problem into a. b. c. d. technology dependent phase and technology mapping phase technology independent phase and technology mapping phase combinational circuits and sequential circuits registers and logic gates

74. Logic optimization is used to improve the logic to meat a. b. c. d. logic constraints timing or area constraints power constraints parasitic constraints

75. In the case of state-machines RTL compilers need to provide for a. b. c. d. automatic state assignment and minimization trigger the registers onthe rising edge of clock set of logic gates set of registers

76. Logic optinmization scheme convertsthe logic into a a. b. c. d. two level PLA POS form standard form two level PLA SOP form combinational and Register circuits

77. Logic synthesis systems are very useful for

a. b. c. d.

transforming between technologies very good silicon implementation to create control logic to create micro code

78. Behavioral synthesis is a. b. c. d. technology dependent and specify the implementation technology independent and specify the implementation technology independent and without specify the implementation technology dependent and without specify the implementation

79. Which of the following synthesis converts RTL description to a set of registers and combinational logic a. b. c. d. behavioral synthesis RTL synthesis logic level synthesis layout synthesis

80. RTL description are captured using a. b. c. d. hardware description language (HDL) software description language cathedral series micro controllers

81. The wait statement of VHDL indicates the presence of a. b. c. d. counters logic gate multiplexer clocked register

82. The case operator of VHDL indicates the a. b. c. counters logic gate multiplexer

d.

clocked register

83. Standard cell and memory are simulated at the level of a. b. c. d. both at logic level both at functional level logic level and functional level fuctional & logic level

84. RTL simulations may be done with the actual clock timing by estimating the a. b. c. d. layout loading capacitancess required speed of design size of tansistor power dessipation iin the circuit

85. The enccution time of timing simulator compared to circuit simulators is a. b. c. d. more less equal not comparable

86. The layout is a faithfull reproduction of the structure of the RTL description means a. b. c. d. all the components are placed correctly all signals are routed correctly functionality is correct system performs as rquired

87. Simulator of software tools is used to a. b. c. d. compile the program synthesize the given circuit predict and verify the performance transfer structureal description to physical form

88. The most detailed and accurate simulation technique is a. gate level

b. c. d.

timing logic level circuit-level

89. Circuit level simulators are characterized by a. b. c. d. high accuracy and long simulation time less accuracy and long simulation time high accuracy and short simulation time less accuracy and short simulation time

90. Circuit level & timing simulations evaluated on a timing sub step basis, where as logic-level simulation is a. b. c. d. appled voltage basis applied current basis event driven basis logic - level basis

91. Switch level simulators merge logic simulators techniques with some circuit simulation techniques by modeling transistors as a. b. c. d. gates open circuits short circuits switches

92. Switch - level simulators are combination of a. b. c. d. circuit level and timing simulators Circuit level and logic level simulators logic level & timing simulators gate and logic level simulators

93. YACR2 router is used to route the a. b. c. d. switch box maze rectangular channel global routing

94. The min-cut alogrithm minimizes the area by a. b. c. d. spliting the conceptual layout until the leaf cells are reached minimize the SOP form of given function minimize the POS form of given function uses standard cells and proper floor planning

95. Maze routers can route any configuration but have comparatively a. b. c. d. short running time small area long running time large area

96. Interactive graphic editors are used to capature the a. b. c. d. RTL circuit behaviour of system layout structure of system

97. In layout systhesis generally two phases are required they are a. b. c. d. designing and minimizing placement and routing optimization of logic and functioning testing and verification

98. The traditional method of capturing a digital system design is a. b. c. d. schematic editor flow table ASIC design compiler

99. Many design systems allow a diagrams because these are a. b. more easy quickly understood

c. d. 100. a. b. c. d. 101. a. b. c. d.

samll in size small area Many design systems generally used HDL because of easy quickly understood small in size easily modified Schematic editors in digital design systems provids a means to draw and connect components compilation of code simulation of system synthesis of system

102. A layout editor might interface to a design rule checking program to allow interactive checking of a. b. c. d. 103. a. b. c. d. 104. a. b. c. d. layout minimization DRC errors design errors possibility of transistor sizing Floor plan editors provide graphical feed back about size and placement of modules internal layout details connectivity of components input / output port details Pearl program analyzer is used to calculate node voltages loop urrents DRC errors delays in circuit operation

105. The timing analyzer does not recognize some paths for some reasons these paths are called

a. b. c. d. 106. a. b. c. d. 107. a. b. c. d. 108. a. b. c. d. 109. a. b. c. d. 110. a. b. c.

critical paths crossed paths sneak paths long paths Simulations with delays are used to check the timiing problems DRC errors functionality speed of system Pearl program analyzer is used to calculate node voltages loop currents DRC errors delays in circuit oeration Network isomorphism is used to prove that a layout is equivalent to a network extracted from a schematic optimum layout optimized placement and routing fabrication mask Electron Beam exposure system is used to create a data used for mask making make a layout from net list check the design rules verify the timing analysis A timing analyzer implemented at the transistor level can provide a designer rapid global functional simulation rapid feed back about critical paths detailed module verification

d. 111. a. b. c. d. 112. a. b. c. d. 113. a. b. c. d. 114. a. b. c. d. 115. a. b. c. d. 116. a.

details of DRC errors Network isomorphism is used to prove that two network are equivalent and therefore should function equivalently the critical path in the system isthe longest path the layout satisfies the design rules the design is optimum The process of comparing two network is commonly called (indicate incorrect answer) Layout versus schematic network analysis network isomorphism netlist compoarison A design-rule-checker is used to find DRC errors conforms the layout to the geometric design rules verify the functionality of the geometric design rules verify the functionality of the design The last step in the design process is layout extraction back annotation pattern generation design -rule verification For MOS circuits the dominent faults are due to short circuits in diffusion layers open circuits in diffusion laye short circuits in interconnections open circuits in interconnections Very effective aid to testing and testbility of a design is a reset facility

b. c. d. 117. a. b. c. d. 118. a. b. c. d. 119. a. b. c. d. 120. a. b. c. d.

facility to probe the circuit nodes provide circuit modification sealed in over glass Correct operation of a design must not be dependent on Rise times or fall times short circuits in diffussion layer Layout short and open circuits in metal layer Generally functional tests are impractical due to fast simulation times and short verification sequences fast simulation times and long verification sequences slow simulation times and very long verification sequences slow simulation times and short verification sequences During testing of VLSI system (Indicate the false statement) The chip is sealed by an overglass layer circuits nodes cannot be probed for monitoring circuits can be modified circuits cannot be modified The advantage of a reset facility in the design is testing always from fixed position testing proceed from known enditions testing proceed from unknown conditions It is not related to testing A 20 bit counter is split into four five bit section, them the required steps for testing

121. are a. b. c. d. 25

four sets of 25 five sets of 24 five sets of 25

122. a. b. c. d. 123. a. b. c. d. 124. a. b. c. d. 125. a. b. c. d. 126. a. b. c. d. 127. a. b.

Manufacturing tests are used to verify that function of a chip as a whole every gate operates as expected function in the field the clock response of the chip VHDL, verilog hardware description languages are used for testing of manufacturing tests fanctionality test Design testing chip testing Functionality tests seek to verify the function of a chip as a whole every gate operates as expected function in the field the clock response of the chip Adhoc testbility means testability arrangements configured with the architecture changes testbility with structure changes testbility arrangements configured without changing the archtecture testbility without structure changes A measure of goodness of a test programm is the amount of fault coverage time cost degree of performance At the prototype state it is possible to provide special test points by providing extra pads for probing It is not possible to test

c. d.

modifing the circuit link connections

128. A finite state machine with 'n' possible inputs to the conbinational logic and 'm' memory elemens then the required test vectors are a. b. c. m+n 2m 2n

d. 129. a. b. c. d. 130. a. b. c. d. 131. a. b. c. d. Generally the system is partitioned for testing because reducing the chip area reducing the no. of pads reducing the number of test vectors reduce the required power The two key concepts underlying all considerations for testabiloity are set and reset controllability and observability intial and final conditions pads and links Controllability in testing means being able to set known internal states being able to generate all states being able to generate all combinations of circuit states read out the result of the state changes

132. Being able to generate all states to fully excise all combinations of circuit states is called a. b. c. d. controllability observability combinationatorial testbility reset facility

133. a. b. c. d. 134. a. b. c. d. 135. a. b. c. d. 136. a. b. c. d. 137. a. b. c. d.

Being able to read out the result of the state changes as they occur is called controllability reset facility combinational testability observality The facults occure due to thin-oxide shorts or metal-to metal shorts are called stuck at zero facults short-circuit faults open-circuit faults bridge faults Radom logic is probably best tested via self testing full serial scan or parallel scan boundary scan LFSR method Self-test circuitry approach is based on linear feed back shift registers only linear feed back shift registers, exclusive-OR and clock system or gate clock system only enclusive OR gates only The combination of LSSD scan path and linear feed back shift register is called self test circuitry signature analysis technique structured testbility built-in logic block observation

138. In the following which one is corrcet with respect to BILBO testing for control inputs C0=1, C1=1 a. b. linear shift mode signature analysis mode

c. d.

data latch reset mode

139.
a. b. c. d. 140. a. b. c. d. 141. a. b. c. d. 142. a. b. c. d. 143. a. b. c. d. 144.

The control inputs

in BILBO testing the coresponding mode is

linear shift mode signature analysis mode datalatch reset mode In the BILBO arrangements, when C0=0, C1=1 then the corresponding mode is linear shift mode signature analysis mode data latch reset mode The following the mode when C0=1, and C1=0 in the BILBO arrangement linear shift mode signature analysis mode data latch reset mode On chip testing is obtained by using self - test circuitry adhoc testability structured testability LSSD approach Signature analysis techniques are on chip testing structured testing LSSD testing adhoc testability The manufacturing cost is low by detecting the malfunctioning of chip at a level of

a. b. c. d. 145. a. b. c. d. 146. a. b. c. d.

wafer level packaged-chip system level field The tests that are usually carried after chip is manufactured are called functionality test design verification manufacturing test technology test Generally memories are tested by self-test full serial scan parallel scan LFSR method

147. In order to reconfogure flip - flops appropriately, it is necessary to be able to include a double throw switch in the a. b. c. d. 148. a. b. c. d. 149. a. b. c. simple scan path address path control singnal path data path The test access port or TAP controller in a boundry - scan system level testing is a 16 - state FSM 8 - state register 8 - state interface pins 16 - state NAND gates The following path is used to reduce testing time in the LSSD simple scan path parallel path single path

d.

complex path

150. The test access port or TAP controller in a boundary - scan system - level testing has connections of a. b. c. d. 151. a. b. c. d. 152. a. b. c. d. 153. a. b. c. d. 154. a. b. c. d. 155. a. one single bit one multiple bits www.studentmoments.com four or five single bit one or two multiple bits The insuction register (IR) in boundry-scan system level testing has to be at least one bit long two bit long www.studentmoments.com there bit long four bit long Subsystems can be checked out individually by providing the appropriate additional inlet/outlet pads additional circuit nodes additional links It is not possible to check The essence of the LSSD approach is to design all circuity in a transistor to transistor transistor to registor register to register register to transistor In the structured testing technique, LSSD means level scan sensistive default www.studentmoments.com level simple scan design level scan simple default level sensitive scan design In the LSSD approach the resisters behaves like a shift register in operation mode and latch in testmode

b. c. d. 156. a. b. c. d. 157. a. b. c. d. 158. a. b. c. d. 159. a. b. c. d. 160. a. b. c. d.

shift register in test mode and latch in operation mode shift registers in both test and operation mode latch in both test and operation mode The IEEE 1149 boundary scan is used for chip level testing design test system level testing circuit level testing To increase the immunity to open - circuit faults usually involve incorporating misaligned connection redundancy nature of defects frequency of defects To find the bridging faults, the following popular testing method is used scan testing ILA IDDQ self testing The layout is tested by using Design rule checker www.studentmoments.com simulator PROBE BILBO The layout modifications improves the performance typically 10 % - 20 % greatethan 50 % typically 100 % typically 30 % to 50 %

161. a. b.

NET is used to verify its compliance with the design rules extract the circuit from the mask layout

c.
d. 162. a. b. c. d. 163. a. b. c. d.

test for the number of simulate the leaf cell PROBE is used to verify the design rules

contacts

extract the circuit from the mask layout layout testing simulate the cell To reduce parasitics, the changes are made in circuit transstor size layout logic

164. The steady state response to any allowed input state change is independent of the circuit and wire delays within the system then this logic system is called a. b. c. d. 165. a. b. c. d. 166. a. level-sensitive finite state machine stable - state combinational logic circuit Long counters are tested by scan - based approaches self test buit - in testing ad-hoc testing The following type of a fault should not distrub the functionality of the circuit Delay fault

b. c. d.

bridge fault open circuit stuck at faults www.studentmoments.com