EE114 Autumn 08/09 R. Dutton, B.

Murmann

Handout #2 Page 1 of 4

Entry Quiz If you are unsure if EE114 is the right class for you, please try to work the problems below. If you cannot solve these, you should most certainly take our course before engaging in more advanced graduate-level coursework. 1. CS-CD Cascade In the amplifier circuit below, ignore finite output resistance, extrinsic device capacitances and back-gate effect. Both transistors operate in the saturation region. Parameters: gm=5mS, fT=5GHz, R=1k.

R R
Vin Vout

Calculate: a) The amplifiers small signal gain vout/vin at low frequencies (ignore all capacitances). Be sure to include the appropriate sign. b) The amplifiers 3-dB bandwidth using the zero-value time constant method.

2. Large Signal Analysis of Differential Pairs In the circuit below, ignore back-gate effect and finite output resistance; assume ideal MOS long-channel I-V characteristics. Sketch Vout versus Vin (03V) in the diagram provided below. Calculate and annotate pertinent saturation points. Parameters: Itail=1mA, R=500, CoxW/L=50mA/V2.

Last modified 9/17/2008 6:16:00 PM

EE114 Autumn 08/09 R. Dutton, B. Murmann

Handout #2 Page 2 of 4

VDD=3V R Vout

1V

Itail

Vin

Itail

2V

Vout

1V Vin

2V

3V

3. Current mirror biasing In the circuit below, determine the aspect ratio K3=W3/L3 such that VDS1=M*VOV1, where M is a positive number and VOV1 is the gate overdrive of transistor M1, which is operating in the forward active region. Express your result in terms of M and the aspect ratios K1=W1/L1 and K2=W2/L2. Assume square law model, and neglect finite output resistance and back-gate effect.

Last modified 9/17/2008 6:16:00 PM

EE114 Autumn 08/09 R. Dutton, B. Murmann

Handout #2 Page 3 of 4

Iref

Iref

Iref

Iout=Iref

W1/L1

W2/L2

W2/L2

W2/L2 M1 W1/L1

W3/L3

W1/L1

4. VGS Bias Circuit In the circuit below, all devices operate in the active region and obey ideal long-channel I-V laws. Ignore finite output resistance and all capacitances except the explicitly shown Cx. Parameters: R=500, gm3=gmx=8mS, Cx=10pF; channel lengths: L4=L3, L2=L1.

VDD M4 4W3 M3 W3 v1 v2 gmx(v1-v2) R M1 W1 M2 KW1 Cx

a) Assuming K=4, calculate the transconductance of M1 (gm1). b) Assuming K=1 and gm1=8mS [not the correct answer for part (a)], what is the unity gain frequency (fc) of the feedback loop in this circuit? Hint: analyze the circuit by evaluating the return ratio of the transconductance element gmx. c) What is the phase margin (PM) of the loop under the conditions given part (b)?

Last modified 9/17/2008 6:16:00 PM

EE114 Autumn 08/09 R. Dutton, B. Murmann

Handout #2 Page 4 of 4

5. Small signal, low frequency port impedances In all of the circuits below, ignore back-gate effect and all device capacitances. Assume that the transistors are operating in the saturation region. Assume gm/ID = 10V-1 where needed. a) In the circuit below, {M1, M2} and {M3, M4} have identical widths and lengths, respectively. Neglecting the finite output resistance of the transistors, what is the resistance looking into the source of M1 (Rx)?

M3

M4

M2

M1 Rx 1mA

b) In the circuit below, do not neglect finite output resistance, and assume that gmro=50. Simplify your calculations using the fact that gmro>>1. What is the port resistance Ry?

1mA VBIAS

M1

Ry

M2

Last modified 9/17/2008 6:16:00 PM