Electrical and Computer Engineering Digital Logic Design ECE112

Lecture 34 [Monday 11/30/09]

Assignment for the next few weeks Homework assignment is posted on the website. Reading assignment is to finish Chapter 8 Labs to be performed for the next 2 weeks are Lab #7, ECE112_Final Project. Your assignment on the final project is to design the project, implement it, demonstrate it to the instructor, and write a project report.

Final Project Description (Was due on Monday 11/23/089 by COB)

For those of you who turned it in, thank you and continue on your projects. For those of you who didnt turn in a description, youve lost a few points off the project. And I have no idea if the project you are doing is adequate or not. It should be some type of FSM (Finite State machine). It can be one from the list I posted, or one that you would like to build. But whatever it is, I would like to know what is is and what its going to demonstrate

Today
Continue our discussion of Synchronous Sequential Networks or as they are commonly referred to Finite State Machines (chapter 8)

Note new specification: Output Z=1 if Input w =1 for two clock ticks and is currently 1. Specification looks like this table: Clock cycle: w: z: t0 0 0 t1 1 0 t2 0 0 t3 1 0 t4 1 1 t5 0 0 t6 1 0 t7 1 1 t8 1 1 t9 0 0 t10 1 0

Since output depends on both Present State Variables and the Input it is a Mealy machine.

Figure 8.22. Sequences of input and output signals.

Output can change Asynchronously

Since the memory can only change on clock synchronously, in the Moore machine the output could only change synchronously with the clock In the Mealy machine since the input signal is also used in creating the output via the OFL, and since the input can change asynchronously, the output of the circuit could change asynchronously

Input Forming Logic IFL

Output Forming Logic OFL

Combinational circuit

Flip-flops

Combinational circuit

Clock

Mealy Machine
Input signals are applied to both the input circuits and the output circuits.

Note in the Mealy machine, the output is not shown in the state (circle), but rather on the transition along with the input since the output Z is dependent on both the Memory and Input.

Reset w = 1z= 0 w = 0z= 0 A w = 0z= 0 B w = 1z= 1

Note the number of states

Figure 8.23. State diagram of an FSM that realizes the task in Figure 8.22.

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END mealy ; ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ; PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= '0' ; WHEN B => z <= w ; END CASE ; END PROCESS ; END Behavior ;

Note: in the Mealy machine, the code for Z is placed in a separate CASE statement. This is necessary because if the code for Z was placed in the first CASE statement, the value of Z could only change as a result of a clock edge, which does not meet the requirement of the Mealy type FSM.

Figure 8.36. VHDL code for the Mealy machine of Figure 8.23.

A a Shift register Adder FSM Shift register b Sum = A + B B Clock s Shift register

Figure 8.39. Block diagram for the synchronous serial adder. ( Mealy-Type FSM)

Reset

( ab s )

11 0 00 0 01 1 10 1 01 0 10 0 11 1

G 00 1 G: carry-in = 0 H: carry-in = 1

Figure 8.40. State diagram for the serial adder FSM.

Present state G H

Next state ab =00 G G 01 G H 10 G H 11 H H 00 0 1

Output s 01 1 0 10 1 0 11 0 1

Figure 8.41. State table for the serial adder FSM.

Present state y 0 1

Next state ab =00 01 Y 0 0 0 1 0 1 1 1 0 1 10 11 00

Output 01 s 1 0 1 0 0 1 10 11

Figure 8.42. State-assigned table for Figure 8.41.

a b

s Full adder Y carry-out Clock Reset D Q Q y

Figure 8.43. Circuit for the adder FSM in Figure 8.39.

A a Shift register Adder FSM Shift register b Sum = A + B B Clock s Shift register

Figure 8.39. Block diagram for the serial adder. ( Mealy-Type FSM)

Reset

00

G0 s = 0 00 00

11

H0 s = 0

01 10

01 10

11

11

01 10

01 10

G1 s = 1

00

H1 s = 1

11

Figure 8.44. State diagram for the Moore-type serial adder FSM.

Present state G0 G1 H0 H1

Nextstate ab =00 G0 G0 G1 G1 01 G1 G1 H0 H0 10 G1 G1 H0 H0 11 H0 H0 H1 H1

Output s 0 1 0 1

Figure 8.45. State table for the Moore-type serial adder FSM.

Present state y2 y1 00 01 10 11

Nextstate ab =00 01 Y2 Y1 00 00 01 01 01 01 10 10 01 01 10 10 10 10 11 11 10 11 Output s 0 1 0 1

Figure 8.46. State-assigned table for Figure 8.45.

Sum bit a b Full adder Carry-out

Y1

Q Q

y1

Y2

Q Q

y2

Clock Reset

Figure 8.47. Circuit for the Moore-type serial adder FSM.

LIBRARY ieee ; USE ieee.std_logic_1164.all ; -- left-to-right shift register with parallel load and enable ENTITY shiftrne IS GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftrne ; ARCHITECTURE Behavior OF shiftrne IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF E = '1' THEN IF L = '1' THEN Q <= R ; ELSE Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= w ; END IF ; END IF ; END PROCESS ; END Behavior ;

Figure 8.48. Code for a left-to-right shift register with an enable input.

1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY serial IS 4 GENERIC ( length : INTEGER := 8 ) ; 5 PORT ( Clock : IN STD_LOGIC ; 6 Reset : IN STD_LOGIC ; 7 A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; 8 Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) ); 9 END serial ; 10 ARCHITECTURE Behavior OF serial IS 11 COMPONENT shiftrne 12 GENERIC ( N : INTEGER := 4 ) ; 13 PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; 14 L, E, w : IN STD_LOGIC ; 15 Clock : IN STD_LOGIC ; 16 Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; 17 END COMPONENT ; 18 19 20 21 22 SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; SIGNAL s, Low, High, Run : STD_LOGIC ; SIGNAL Count : INTEGER RANGE 0 TO length ; TYPE State_type IS (G, H) ; SIGNAL y : State_type ;

continued in Part b

Figure 8.49.a VHDL code for the serial adder (Part a).

23 BEGIN 24 Low <= '0' ; High <= '1' ; 25 ShiftA: shiftrne GENERIC MAP (N => length) 26 PORT MAP ( A, Reset, High, Low, Clock, QA ) ; 27 ShiftB: shiftrne GENERIC MAP (N => length) 28 PORT MAP ( B, Reset, High, Low, Clock, QB ) ; 29 AdderFSM: PROCESS ( Reset, Clock ) 30 BEGIN 31 IF Reset = '1' THEN 32 y <= G ; 33 ELSIF Clock'EVENT AND Clock = '1' THEN 34 CASE y IS 35 WHEN G => 36 IF QA(0) = '1' AND QB(0) = '1' THEN y <= H ; 37 ELSE y <= G ; 38 END IF ; 39 WHEN H => 40 IF QA(0) = '0' AND QB(0) = '0' THEN y <= G ; 41 ELSE y <= H ; 42 END IF ; 43 END CASE ; 44 END IF ; 45 END PROCESS AdderFSM ; 46 WITH y SELECT 47 s <= QA(0) XOR QB(0) WHEN G, 48 NOT ( QA(0) XOR QB(0) ) WHEN H ; 49 Null_in <= (OTHERS => '0') ; 50 ShiftSum: shiftrne GENERIC MAP ( N => length ) 51 PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ; 52 Stop: PROCESS 53 BEGIN 54 WAIT UNTIL (Clock'EVENT AND Clock = '1') ; 55 IF Reset = '1' THEN 56 Count <= length ; 57 ELSIF Run = '1' THEN 58 Count <= Count -1 ; 59 END IF ; 60 END PROCESS ; 61 Run <= '0' WHEN Count = 0 ELSE '1' ; -- stops counter and ShiftSum 62 END Behavior ;

Figure 8.49.b VHDL code for the serial adder (Part b).

Example on board

Now lets look at another example

It is a sequence detector We will compare Moore and Mealy implementations.

First: A Moore FSM that detects the sequence 1011

This State machine outputs a 1 if the sequence 1011 is detected

Note that output is 1 after 1011 is detected and output stays 1 for a full clock cycle.

Sequence Detector that detects 1011 and outputs a logic 1 after sequence is detected. (3 flip-flops are required for implementation)

1 clock 0

1
1 Input 0

Moore Output

1 0

Rising edge of clock shown

Now: A Mealy FSM that detects the sequence 1011

Note that output is 1 on last bit in the detected sequence. And depending on how long input is 1 determines how long output will remain as a logic 1.

Sequence Detector that detects 1011 and outputs a logic 1 when sequence is detected. (Only 2 flip-flops are required to implement this.)

1 clock 0

1
1 Input 0

Mealy Output

1 0

Rising edge of clock shown

The rest of the design is left to the student

But, you can see that the reduction in states does make the design simpler.

Bottom Line is: Everything has its price

As we said before, there are always tradeoffs Weve seen this in a couple of examples

What are the +s and s

Only the application can determine if the attribute is a + or a - . For example Consider the attributes of each:
Mealy??? Moore??

What are the +s and s

Mealy???
Simpler structure

Moore??

What are the +s and s

Mealy???
Simpler structure Asynchronous operation

Moore??

What are the +s and s

Mealy???
Simpler structure Asynchronous operation Output only valid at transition of clock

Moore??

What are the +s and s

Mealy???
Simpler structure Asynchronous operation Output only valid at transition of clock

Moore??
Synchronous operation

What are the +s and s

Mealy?
Simpler structure Asynchronous operation Output only valid at transition of clock

Moore??
Synchronous operation Output stable for entire cycle

1 clock 0

1
1 Input 0

Moore Output

1 0

Mealy Output

1 0

Rising edge of clock shown

1 clock 0

1
1 Input 0

Moore Output

1 0

Mealy Output

1 0

Rising edge of clock shown

Another example A little more complex - Not that I expect you to be able implement this, but just to show the scope of FSMs
Lets look at a simple computer with a two bit word.

Computer Inputs
The computer is a two bit computer, that is, it has a 2 bit instruction word x1 and x2 Bit x1 indicates if an instruction is to be executed
x1 = 1 means execute an instruction x1 = 0 means no execution

Bit x2 indicates specifically what the instruction is:

x2 = 1 means input a number and send it to output x2 = 0 means input a number, multiply it by 2 and send it to the output.

Computer (Hardware)
Program

X1,X2 0 1 1 0 1 1 0 0

FSM

Heres a state diagram of the computer.

Now, on to Minimization

1 a7 L w E Adder FSM a0 L E

D3 D2 D1 D0 Counter Q3 Q2 Q1 Q0

0 1

b7 L w E

b0

Run 0 L w E Sum Sum 0

0 1 Clock Reset

Figure 8.50. Synthesized serial adder.

Present state A B C D E F G

Next state w= 0 B D F B F E F w= 1 C F E G C D G

Output z 1 1 0 1 0 0 0

Figure 8.51. State table for Example 8.5.

Present state A B C F

Nextstate w= 0 B A F C w= 1 C F C A

Output z 1 1 0 0

Figure 8.52. Minimized state table for Example 8.5.

Clock sense N sense D N D

(a) Timing diagram

N sense N Clock D Q Q D Q Q

(b) Circuit that generates N

Figure 8.53. Signals for the vending machine.

DN Reset DN DN DN D S4 1 S2 0 D DN S5 1 N S8 1 S6 0 D S9 1 DN DN N S3 0 N D S7 1 S1 0 DN DN

Figure 8.54. State diagram for Example 8.6.

Present state S1 S2 S3 S4 S5 S6 S7 S8 S9

Next state DN =00 S1 S2 S3 S1 S3 S6 S1 S1 S3 01 S3 S4 S6 S8 10 S2 S5 S7 S9 11

Output z 0 0 0 1 1 0 1 1 1

Figure 8.55. State table for Example 8.6.

Present state S1 S2 S3 S4 S5

Next state DN =00 S1 S2 S3 S1 S3 01 S3 S4 S2 10 S2 S5 S4 11

Output z 0 0 0 1 1

Figure 8.56. Minimized state table for Example 8.6.