RANGANATHAN ENGINEERING COLLEGE, (Approved by AICTE and Affiliated to Anna University)

COIMBATORE 641 109.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING (PG) M.E. VLSI DESIGN (I YEAR I SEMESTER) VLSI DESIGN LABORATORY I (VL9217)
LABORATORY MANUAL (Prepared according to the Regulations 2009 of Anna University, Chennai)

LIST OF EXPERIMENTS
1.

Modeling of Sequential Digital system using VHDL.

2.

Modeling of Sequential Digital system using Verilog.

3.

Design and Implementation of ALU using FPGA.

4.

Simulation of NMOS and CMOS circuits using SPICE.

5.

Modeling of MOSFET using C.

6.

Implementation of FFT, Digital Filters in DSP Processor.

7.

Implementation of DSP algorithms using software package.

8.

Implementation of MAC Unit using FPGA.

EX.NO:1.a DATE:

DESIGN OF HALF ADDER USING VHDL

AIM: To design a Half adder using VHDL. SOFTWARE REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b. Step 3: Declare output ports s, c. Step 4: Begin the process using behavioral architecture. Step 5:.Assign s=a b. Step 6: Assign c=a.b. Step 7: End the process. THEORY: The half adder operation needs two binary inputs, augends and addend bits and two binary outputs are sum and carry. Sum= a b. Carry=ab. In multi-digit addition, we have to add two bytes along with the carry of the previous digit addition. Effectively such addition requires addition of three bits. This is not possible with the half adder.

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ha is Port ( a,b : in STD_LOGIC; s,c : out STD_LOGIC); end ha; architecture Behavioral of ha is begin s<=a XOR b; c<=a AND b; end Behavioral; RESULT: Thus the Half adder was designed using VHDL.

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EX.NO:1.b DATE:

DESIGN OF FULL ADDER USING VHDL

AIM: To design a full adder using VHDL. SOFTWARES REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b, cin. Step 3: Declare the output ports s, cy. Step 4: Begin the process using behavioral architecture. Step 5: Assign s= a cin. Assign cy= (a.b) + (b.cin) + (cin.a). Step 6: End the process. THEORY: Full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables denoted by A and B, represent the two significant bits to be added. The third input Cin represents the carry from the previous lower significant position. _ _ _ _ _ _ _ Sum= A.B. Cin+ A.B. Cin+ A.B. Cin+ A.B. Cin. Cin= Cin b B) Cout=A.B+A.Cin+B.Cin. (A

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full is Port ( a,b,cin : in STD_LOGIC; s,cy : out STD_LOGIC); end full; architecture Behavioral of full is begin s<=a xor b xor cin; cy<=(a and b)or(b and cin)or(cin and a); end Behavioral; RESULT: Thus the full adder was designed using VHDL

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