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6.002 ELECTRONICS
Recall
R +
vI +
– C vC
–
v I = VI for t ≥0 vC (0 )
−t
vC = VI + (vC (0)− VI ) e RC 1
t
t ≥0 0
vC
VI
−t
vC = VI + (vC (0)− VI ) e RC
vC (0 )
t
0
Notice that the capacitor voltage for t ≥ 0 is
independent of the form of the input voltage
before t = 0 . Instead, it depends only on the
capacitor voltage at t = 0 , and the input voltage
for t ≥ 0 .
6.002 Fall 2000 Lecture 14 3
State
q=CV
Correspondingly,
zero state response or ZSR
−t
vC = VI − VI e RC 2
DIGITAL MEMORY
Why memory?
Or, why is combinational logic insufficient?
Examples
Consider adding 6 numbers on your
calculator
2+9+6+5+3+8
M+
store M The
NEC
d OUT View ¥
☺
d IN
store
dIN dOUT
* storage
C node
store
store = 1
C
dIN vC d
* OUT
store = 0
C
vC RL
5V
Stored value leaks away VOH
t
−t
T
from 2
RL C
vC = 5 ⋅ e
VOH
T = − RLC ln
5
store pulse width >> RON C
dIN dOUT
*
RIN
C buffer
store
Input resistance RIN
VOH
T = − RIN C ln
5
RIN >> RL
Better, but still not perfect.
Demo
dIN dOUT
*
C
store
Does this work?
store
dIN dOUT
*
C
store
Works!
Decoder
A d IN
00 S M
d OUT
B d IN A
01 S M
d OUT
a0 a1
2
Address d IN
C B
10 S M
d OUT
D d IN C
11 S M
d OUT
IN store
OUT
D
a0 a1 A B C D
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1