Modelling and Model Based Compensation of Non-Ideal Characteristics of Two-Level Voltage Source Inverters for Drive Control Application

Markus Seilmeier, Christoph Wolz and Bernhard Piepenbreier, Senior Member, IEEE

AbstractIn order to be able to optimize the performance of sophisticated model based AC machine control, precise models of the overall drive system are needed. This way compensation schemes for non-ideal characteristics can be derived based on the model inversion technique. Power electronic converters show the following non-ideal effects which have to be considered: turn-on delay time of the gate drive to prevent dc-link short-circuiting, non-ideal switching characteristics and forward voltages of the power electronic devices. In this paper models for these disturbances are derived and the respective compensation schemes are deduced. In constrast to conventional approaches for converter linearization, an analytic compensation law which allows considering different forward voltage-current characteristics of the diode and transistor is proposed. The effectiveness of this method is proven by means of experimental results. Index TermsVSI modelling, compensation of voltage errors, model inversion technique, inverter nonlinearity, non-ideal switching characteristic, forward voltage drop

characteristics or it is assumed that the duty cycles are 0.5, that is the duty cycle dependency of the volt seconds lost is not considered [1] [7] [8] [9]. Therefore in this paper a model and compensation scheme are proposed to be able to compensate even for different current-voltage characteristics of the semiconducting devices without any limitations as concerns different current voltage characteristics of diode and transistor. Thereby the model inversion technique is employed to compensate for the nonideal characteristics. The paper is organised as follows: Section II presents the model of the voltage source inverter that is used to deduce the compensation scheme in Section III. Section IV deals with the experiment based identication of the parameters for the compensation law. Afterwards the efcacy of the proposed methods is proven by means of test bench measurements in Section V. Section VI completes the paper with a conclusion. II. M ODELLING OF THE VOLTAGE S OURCE I NVERTER The topology of the two-level voltage source inverter (VSI) is shown in Fig. 1. The inverter generates the volt seconds commanded for machine control by suitable high frequent switching of six active and two zero switching states provided by the VSI. Conventional modulation strategies like the space vector modulation [10] assume that the switches and the gate drive unit are ideal. Real inverters show nonideal characteristics that have to be compensated to achieve the characteristics of an ideal inverter. The VSI model SV SI , which can be split up into the subsystems S1 , S2 and S3 (Fig. 2), provides a relationship between the inputs (duty cycles) and the outputs (line-to-line voltages). S1 models the switching-on delay time td,on introduced by the gate drive unit to prevent dc-link short circuiting. Non-ideal switching characteristics of the power electronic devices are considered in the subsystem S2 . The forward voltage drops of the diodes and transistors are modelled in S3 . A. Characteristics of the Ideal Inverter For modeling of the ideal VSI the PWM control signals for the upper transistors characterized by the duty cycles i,P W M (i {a, b, c}), whereby i denotes the respective half bridge: thigh,i,P W M (1) i,P W M = TP W M are used. Thereby thigh,i,P W M denotes the high level time of the pulse pattern and TP W M is the cycle duration. One can

I. I NTRODUCTION Nowadays two-level DC-link inverters are the common converters used for AC machine drive control. These converters, however, show non-ideal characteristics that deteriorate the control performance, if not compensated adequately. The disturbances occur due to the fact that there is a nonlinear relationship between the commanded converter output voltages and the real output voltages. This leads to strong fth and seventh harmonic components in the output voltage [1] [2]. These harmonics cannot be compensated by the conventional eld-oriented control schemes for induction and synchronous machine drive control due to the fact that the internal model principle is not fullled [3]. Therefore either an extension of the control scheme is needed to deal with these harmonics [4] or the effects have to be compensated by means of a converter linearization. Moreover, if not compensated, the nonlinear characteristic of the inverter leads to errors in the identication of the machine parameters because the volt seconds supplied by the converter do not match the commanded values. This typically results in a biased parameter estimate [5]. In some applications mainly the delay times are signicant and therefore the forward voltage drops of the power electronic devices are neglected [6]. If the forward characteristics are considered, many authors assume that the power diodes and transistors have either identical forward current-voltage
Manuscript received June 10, 2011. The authors are with the Chair of Electrical Drives and Machines, University of Erlangen-Nuremberg, Cauerstrasse 9, 91058 Erlangen, Germany (Corresponding author: seilmeier@eam.eei.uni-erlangen.de).

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b 3 ia ib ic m=2 R S T 4 m=3 U Uabs = |U | m=1 u 7, 8 m=4 m=6 1 a 2

UDC

Fig. 1. Topology of the ideal voltage source inverter consisting of the dc link capacitor and three half bridges with two power transistors (here IGBTs) and antiparallel power diodes each.

m=5 5 c

a,P W M b,P W M c,P W M

S1

a b c

S2

a b c

S3

uab ubc uca

Fig. 3. Space Vector Diagram with the commanded space vector U , also characterized by the absolute value Uabs and the angle u with respect to the a-axis. is the sector angle with respect to the space vector m, whereby m is the current sector number.

SV SI
Fig. 2. Inverter model SV SI and subsystems S1 (on-delay time), S2 (nonideal commutation), S3 (forward voltage drop)

Using u j = i,P W M UDC one can nd the following relationship, whereby {i, j } {a, R} {b, S } {c, T }: a,P W M 1 1 0 u ab u 1 1 b,P W M UDC bc = 0 (3) 1 0 1 c,P W M u ca
T V SI

nd an equation for the mean values of the output voltages u RS , u ST and u T R over one switching period by use of the voltages u j from the output terminals j {R, S, T } with respect to the negative dc link potential: u RS 1 1 0 u R u ST = 0 1 1 u S (2) u T R 1 0 1 u T

freedom can be chosen freely to nd a modulation law because n rank (T V SI ) = 1. An easy linear modulation strategy could be derived based on the pseudo inverse of TV SI but it lacks of a reduced maximum output voltage. Therefore it is very common to use the Space Vector Modulation (SVM) instead, which is a nonlinear modulation strategy, to achieve higher voltage utilization [10]. Moreover the SVM features low harmonic content and a minimum number of switchings during one period, thus switching losses are minimized [12]. The input for the space vector modulation is the space vector U commanded by the drive control, consisting of the absolute value Uabs and angle u (Fig. 3). To generate the commanded volt seconds over one switching period with a minimum number of switching cycles only the adjacent active vectors and both zero states 7 and 8 are used. The sector transformation = u (m 1) (4) 3 with the constraint [0, [ 3 (5)

Assuming that UDC is constant within one switching period, one can conclude from (3) that the average line-to-line output voltages u ab , u bc and u ca of the ideal inverter are uniquely determined by the duty cycles i,P W M and do not depend on whether the pulse patterns are symmetric or not. The transformation matrix T V SI will be needed in the next step for discussion of the modulation strategy. B. Space Vector Modulation The aim of the modulation strategy is to provide the duty cycles needed to generate the commanded values of the converter output voltages. Therefore an inverse model of (3) is needed. Analyzing the transformation matrix T V SI one can nd that this transformation is singular and therefore not uniquely invertible because det(T V SI ) = 0 and rank (T V SI ) = 2 < n = 3 whereby n is the number of rows and columns of the quadratic matrix T V SI [11]. Thus an additional degree of

provides the current sector number m {1, 2, .., 6} for the SVM. Moreover the variable q = mod(m + 1, 6) is dened. The well known equations for the on times tm and tq of the adjacent active and t7 and t8 of the zero states can be calculated as follows: Uabs 3sin( ) (6) tm = T P W M UDC 3 Uabs tq = T P W M 3sin( ) (7) UDC t0 = 2t7 = 2t8 = TP W M tm tq (8) The on times of the remaining active states are zero. For practical implementation the on times (6)-(8) have to be transformed into the duty cycles i,P W M . The transformation

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i,P W M

on-delay time td,on on-delay time td,on

i,top

R
i,bottom

ua ub uc

a b c

load ua ub uc

ia UDC S ib T ic

i,top

td,on

ii > 0 t
i,top

td,on

ii < 0 t
Fig. 4. Non-ideal characteristics of the gate drive unit: ideal pulse patterns (blue) and non-ideal current sign dependent (distorted) pulse patterns (red).

Fig. 5. Voltage Source Inverter model consisting of ideal power transistors and diodes. Forward losses of the power electronic devices are modelled by the voltage sources ui (i {a, b, c}). The dc link voltage is UDC and the three phase load is modelled by the voltage drops ui .

whereby Am denotes the transformation matrix for sector m: 2 2 1 2 0 1 0 0 1 A1 = 0 2 1 A2 = 2 2 1 A3 = 2 2 1 0 0 1 0 0 1 0 2 1 (10) 0 0 1 0 2 1 2 2 1 A4 = 2 0 1 A5 = 0 0 1 A6 = 0 0 1 2 2 1 2 2 1 2 0 1 C. On Delay Time to prevent DC-link short-circuiting

depends on the sector m of the commanded space vector and is given as follows: tm a 1 b = A m tq (9) TP W M t0 c

volt seconds due to the non-ideal commutation. The equivalent duty cycles i generated by the inverter are as follows: ti,T ti,D S2 : i = i sgn(ii ) (12) TP W M E. Forward Voltage Drop of the Power Electronic Devices The nonlinear forward voltage-current characteristic of the power diodes and transistors lead to additional distortion of the converter output voltages. To account for this effect the inverter is split up into an ideal part and nonlinear voltage sources ui (Fig. 5), which consider the duty cycle and load current dependant mean forward voltage drop in one switching cycle: ui =
f i u f T,i + (1 i )uD,i f (1 i )uf T,i + i uD,i

if if

ii > 0 ii < 0

(13)

To prevent a half-bridge shoot through (DC-link short circuiting) a constant on-delay time td,on is introduced by the gate drive unit. Therefore the real duty cycle i = i,top generated by the gate drive unit for one half bridge i {a, b, c} deviates from the commanded duty cycle i,P W M , as depicted in Fig. 4: S1 :
i = i,P W M sgn(ii )

Thereby uf T,i = f (|ii |) denotes the load current dependant forward voltage drop of the power transistor and uf D,i = f (|ii |) the respective forward voltage of the diode. The real mean output voltages u i with respect to the negative dc link potential can be calculated based on Fig. 5 as follows: u a u R ua u b = u S ub (14) u c u T uc The system description for S3 in Fig. 2 is given by the equations (13), (14) and: u ab 1 1 0 u a u bc = 0 1 1 u b (15) u ca 1 0 1 u c

td,on TP W M

(11)

Thereby td,on is the constant on delay time of the gate drive unit. D. Non-ideal switching characteristics of the Power Electronic Devices Non-ideal load current dependant switching characteristics of the power transistors and diodes lead to an additional deviation from the commanded volt seconds. Therefore the load current dependant equivalent delay times tk,D (ii ) and tk,T (ii ) are introduced, which consider the deviation in the

III. C OMPENSATION OF N ON - IDEAL C HARACTERISTICS BASED ON THE M ODEL I NVERSION T ECHNIQUE The aim of the compensation is to nd an inverse model 1 SV SI of the inverter model SV SI that way that the following ! ! condition is fullled: Uabs,real = Uabs and u,real = u , whereby Uabs,real and u,real represent the real output voltages of the inverter in terms of a space vector. The basic structure of the model inversion technique based compensation scheme is depicted in Fig. 6.

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 Uabs u

a SVM b c

forward b loss compen c sation

1 SV SI

a,P W M compensation of b,P W M td,on , ti,D c,P W M and ti,T

Fig. 6. Structure of the compensation scheme based on the model inversion technique, consisting of Space Vector Modulation (SVM), forward loss compensation and compensation of delay times due to non-ideal switching (ti,D and ti,T ) and on-delay time td,on .

A. Forward Loss Compensation The aim of the compensation is to ensure that the real mean output voltages u i equal the commanded voltages u i : u i =
!

identical gate drive units for all transistors identical characteristics of all diodes and transistors If these conditions were not fullled, all switches and gate drives would have to be identied separately. For identication of the parameters test bench measurements were carried out. Thereby the load machine was operated in position control mode and the test machine was operated in current control mode with a eld oriented control. The commanded position value was chosen that way that the d-axis current equals the current in phase i {a, b, c}. Therefore the current ii can be varied easily by changing the commanded d-axis current. Measuring the respective voltage Ui and the pwm signal i,P W M provides the data needed for identication.

u i

i UDC =

(16)

A. Identication of the parameters to account for non-ideal switching characteristics The compensation law (21) includes three parameters: on delay time td,on = const caused by the gate drive unit, the equivalent load current dependant switching delay times of the transistor ti,T = f (ii ) and diode ti,D = f (ii ). Dening the effective load current dependant on delay time of the transistor ti,T,on = td,on + ti,T = f (ii ) and diode ti,D,on = ti,D = f (ii ) with respect to either the falling or the rising edge of the PWM pulse pattern reduces the number of parameters that have to be identied and stored in look up tables. Without loss of generality the falling edge of the pwm pulse pattern is chosen for the identication. The measurement data in Fig. 7 show that the switching characteristic of the diode strongly depends on the load current while the switching time of the IGBT is nearly constant. The principle for the identication is depicted in Fig. 8. The error due to the forward voltage drop of the power electronic devices can be neglected because the identication interval Td,ident is small in comparison to the cycle duration TP W M , thus not being signicant. The equivalent on delay times ti,T,on and ti,D,on for ideal switching behaviour are computed that way that the green and the red areas are equal. For the falling edge of the pulse pattern the parameters ti,T,on (ii ) for the transistor and ti,D,on (ii ) for the diode can be computed as follows: UDC 1 ti,D,on (ii ) = UDC ti,T,on (ii ) = 1
t2

Expressing u j (j {R, S, T }) in terms of the resulting duty cycles i requested by the forward loss compensation yields:
u j = i UDC

(17)

B. Compensation of the on-delay time and non-ideal switching With regard to the implementation effort one combines the subsystems S1 and S2 given by (11) and (12) yielding S12 : S12 : i = i,P W M sgn(ii ) td,on + ti,T ti,D TP W M (19)

Replacing the duty cycles i in (13) by i provides the real mean forward losses after compensation. Using the aforementioned equation and (14) - (17) provides the novel compensation law for the forward losses: i UDC +uf D,i if ii > 0 f f U DC uT ,i +uD,i i = (18) f +uT ,i i UDC if i < 0 i f f U +u u
DC T ,i D,i

To achieve compensation of these effects the following condition needs to be hold:

i = i !

(20)

This results in the compensation law for the on-delay time and non-ideal switching:
1 S12 : i,P W M = i + sgn(ii )

ui,real d
t1 t2

if if

ii < 0 ii > 0

(22) (23)

td,on + ti,T ti,D TP W M

(21)

ui,real d
t1

IV. I DENTIFICATION OF THE M ODEL PARAMETERS For the implementation of the compensation laws (18) and (21) the following model parameters need to be known: voltage-current characteristics of the power transistor and diode switching on delay time of the transistor and diode delay time to prevent dc link short-circuiting. To account for the load current dependancy of the parameters look up tables are used. Prerequisites for the identication presented here are:

Like this the equivalent voltage curve Ui,eq for an ideal inverter and the real voltage curve Ui,real of the real inverter generate equal volt seconds. If the top and bottom transistors or diodes have identical switching characteristics, the parameter curves are axially symmetric: ti,D,on (ii ) = ti,D,on (ii ) ti,T,on (ii ) = ti,T,on (ii ) (24) (25)

This is typically fullled and therefore one can compute the complete look up tables using (22)-(25) with no need for additional measurements for the rising edge.

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x 10 3

x 10 3

P W Mi

2.5

2.5

ti,D,on [s]

0 -0.5 0 0.5 1 1.5

ti,T,on [s]
0 10 20 30

t[s]

2.5

3.5

4 x 10

4.5
-6

1.5

1.5

Ui,diode [V ]

600

400 200 0 -0.5 0 0.5 1

if t[s]
1.5 2 2.5 3 x 10 3.5
-6

if,D [A]

10

20

30

if,T [A]

Fig. 9. Look-up tables for load current dependant commutation times for diode ti,D,on (left) and transistor ti,T,on (right).

ui

ui,real

Ui,IGBT [V ]

600 400 200 0 -0.5 0 0.5 1

ui,ideal

ui,real

if

t[s]

1.5

2.5

3 x 10

3.5
-6

uf T,i uf D,i t1 TP W M
Fig. 10. Method for identication of the load current dependant forward voltage drop of diode and IGBT.

Fig. 7. Graphs for the ideal pwm-control signal for half bridge i (top), non-ideal load current dependant commutation characteristics of the diode (middle) and IGBT (bottom). Thereby Ui,diode is the voltage curve, if the current commutates from the upper IGBT of the half bridge to the bottom diode. Ui,IGBT represents the commutation characteristic, if the current commutates from the top diode to the bottom IGBT.

t t2

Tf,ident

Ui

ti,T,on /ti,D,on Ui,eq Ui,ideal Ui,real

t Td,ident t1 t2

Fig. 8. Principle for identication of the effective on delay times for transistor ti,T,on and diode ti,D,on . Ui,ideal (blue) is the ideal voltage that would be provided, if the VSI was ideal, whereas Ui,real (red) denotes the real output voltage and Ui,eq (green) is the equivalent output voltage with ideal rectangular output waveform that generates the same volt seconds as Ui,real . Td,ident = t2 t1 denotes the identication interval.

to be identied in order to be able to store these data in look up tables for the compensation (18). For identication of the forward voltage drop characteristics the time interval Tf,ident is analyzed, as depicted in Fig. 10. If the inverter was ideal ui,real would equal ui,ideal . Due to the load current dependant forward voltage drop over the power electronic devices, however, a discrepancy, which is caused by the forward voltage drop of either power transistor or diode, is observed. The output voltage ui,real is measured and compared to the ideal output voltage ui,ideal of the converter for the respective state. If the load current fullls ii < 0 the bottom transistor and the top diode of the respective half bridge conduct temporarily during one switching cycle, otherwise the top transistor and the bottom diode. Within Tf,ident = t2 t1 the ideal output voltage is ui,ideal = 0V . Therefore one can calculate the forward voltages of diode and transistor as follows: uf T,i (if = ii ) = uf D,i (if = ii ) = 1 Tf,ident 1 Tf,ident
t2

The results of the identication are given in Fig. 9. One can see that the commutation time of the transistor ti,T,on shows just a very slight increase with increasing forward current. The commutation characteristic of the diode represented by the parameter ti,D,on , however, shows a signicant dependency of the commutation time on the forward current. B. Identication of the voltage-current characteristics of diode and IGBT The voltage current characteristics of semiconducting devices are nonlinear. Therefore these characteristic curves have

ui,real d
t1 t2

if

ii < 0 (26)

ui,real d
t1

if

ii > 0 (27)

The forward characteristics of the diode and the IGBT identied by using this method is given in Fig. 11. One nds that for the employed converter the characteristics of the IGBT and the diode just slightly differ from each other.

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30 25 IGBT diode

20 15 10 5 0 0 0.5 1

ideal inverter nearly vanish, as can be seen in the FFT results. Moreover the current ripple is reduced, thus reducing harmonic losses. In the graph for uq one can see that there even occur signicant deviations in the DC-parts of the control signals, thus causing biased parameter estimates, if the compensation is not employed. Moreover the jump discontinuity observed in id disappears, if the compensation is active. VI. C ONCLUSION In this paper a novel output voltage error compensation scheme for two-level voltage source inverters is proposed, which can, in contrast to conventional approaches, also deal with different voltage-current characteristics of the power electronic devices. The typical approach is either assuming the diodes and the transistors have an identical voltagecurrent characteristic curve or the duty cycles are all 0.5. This limitation is cancelled out by the deduction and use of an analytic compensation law which compensates for the inverter errors based on look-up tables. This way the compensation laws remain linear while the nonlinearities are taken into consideration in the look-up tables. It is shown that the characteristic 6nth harmonics in the eld oriented coordinates are signicantly reduced, if the compensation scheme is used, thus proong the efcacy of the proposed identication and compensation methods. Due the inverter model is physically motivated, the inverter switching frequency can be changed arbitrarily without need to reidentify any of the model parameters, as it would be needed for a black box identication of the inverter. For the identication just easy measurements using a conventional eld oriented control and a position controlled load machine are needed. Thereby just the voltages from the inverter output clamps with respect to the negative dc link potential and the respective pwm signal have to be measured. R EFERENCES
[1] J. Holtz and J. Quan, Sensorless vector control of induction motors at very low speed using a nonlinear inverter model and parameter identication, in IEEE Transactions on Industry Applications, Vol. 38, No. 4, 2002. [2] N. Hur, K. Nam, and S. Won, A two-degrees-of-freedom current control scheme for deadtime compensation, in IEEE Transactions on Industrial Electronics, Vol. 47, No. 3, 2000. [3] J. Lunze, Regelungstechnik 2. Springer Verlag, Berlin, Germany, 2010. [4] M. Seilmeier, S. Arenz, B. Piepenbreier, and I. Hahn, Model based closed loop control scheme for compensation of harmonic currents in PM-synchronous machines, in International Symposium on Power Electronics Electrical Drives Automation and Motion (SPEEDAM), 2010. [5] A. Gelb, Ed., Applied Optimal Estimation. The M.I.T. Press, 1974. [6] L. Idkhajine, E. Monmasson, and A. Maalouf, Ac drive system on chip controller with non-linearity errors compensation, in IECON 2008, 2008. [7] E. Holl, H. Schierling, and A. Walter, EP Patent 0 711 471 B1, 1993. [8] K. Wiedmann, F. Wallrapp, and A. Mertens, Analysis of inverter nonlinearity effects on sensorless control for permanent magnet machine drives based on high-frequency signal injection, in EPE 2009, 2009. [9] K. Liu, Z. Q. Zhu, Q. Zhang, J. Zhang, and A. W. Shen, Inuence of inverter nonlinearity on parameter estimation in permanent magnet synchronous machines, in ICEM 2010, 2010. [10] M. Kazmierkowski, R. Krishnan, and F. Blaabjerg, Control in Power Electronics. Academic Press, 2002. [11] I. N. Bronstein and K. A. Semendjajew, Eds., Taschenbuch der Mathematik. Verlag Harry Deutsch, Germany, 2000. [12] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Converters. IEEE Press Series on Power Electronics, 2003.

i f [ A]

uf [V ]

1.5

Fig. 11. Forward Characteristic of diode and IGBT identied based on method depicted in Fig. 10.
2

amp(ud,AC )[V ]

0.8 0.6 0.4 0.2 0 0 0.4 0.3 0.2 0.1 0 0 4 8 12 4 8 12

u d [V ]

1 0 1 0 8 0.5 1 1.5

t[sec] uq [V ]
6 4 2 0 0 0.5 0.5 1 1.5

f [Hz ] amp(uq,AC )[V ]

t[sec] amp(id,AC )[V ]

0.08 0.06 0.04 0.02 0 0 0.03 0.02 0.01 0 0 4 4

f [Hz ]

id [A]

0 0.5 1 0 20.5 0.5 1 1.5

12

t[sec] amp(iq,AC )[V ] iq [A]

f [Hz ]

20

19.5 0 0.5 1 1.5

12

t[sec]

f [Hz ]

Fig. 12. Experimental results for n = 10rpm and iq = 20A with (blue) and without compensation (red). Evaluation of the time domain curves (left) and FFT amplitudes of the AC parts of eld oriented variables relevant for control (right). The 6nth (n {1, 2, 3, ...}) harmonics, which are characteristics for the non-ideal inverter, correspond to the frequencies 4Hz , 8Hz , 12Hz , ...

V. E XPERIMENTAL V ERIFICATION OF THE PROPOSED M ETHODS The results in Fig. 12 prove the efcacy of the proposed identication and compensation methods. If the compensation is not used, signicant 6nth harmonics n {1, 2, 3, ...} (4Hz , 8Hz , 12Hz , ...) occur in the control input signals ud and uq . Anyway these harmonics cannot be eliminated in the control outputs id and iq due to the internal model principle as previously discussed. Using the compensation scheme, one can see that the characteristic 6nth harmonics caused by the non-

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