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SURFACE MOUNT
SOLDERING TECHNIQUES
AND THERMAL SHOCK IN
MULTILAYER CERAMIC CAPACITORS
John Maxwell
AVX Corporation
Abstract:
All components used in surface mount
assemblies have temperature processing
limitations that must be adhered to for
maximum reliability. This paper discusses
multilayer ceramic capacitors in detail and
soldering process considerations that are
valid for all SMT components.
SURFACE MOUNT
SOLDERING TECHNIQUES
AND THERMAL SHOCK IN
MULTILAYER CERAMIC CAPACITORS
John Maxwell
AVX Corporation
Figure 1. MLC Structure with CTE and T Listed Vapor phase reflow (VPR) soldering uses latent heat of
vaporization of the condensing vapor as the heat
The termination and electrodes heat up more quickly transfer method. Thermal shock of components is not
than the ceramic body, exerting forces on the ceramic obvious when VPR soldering is used but it can still be
which cause cracking if the temperature rate of rise is present. Hot belt reflow and infrared (IR) reflow have
too rapid. This is due to a large difference in CTEs and lower heat transfer rates because conduction, convection
T between the ceramic and termination. As the and radiation are the heat transfer methods used.
termination heats up, it is an expanding rectangular
Wave soldering has the highest heat transfer rates
annulus pulling on the ceramic while the expanding
and puts the greatest thermal shock stress on
electrodes act as wedges forcing the ceramic apart at
components. When extreme thermal shock is present, it
the electrode/termination interface as shown in Figures
is very obvious with visible cracks on the surface and
2 and 3.
sides of the MLC. These cracks start at or near the
Different soldering techniques impact temperature termination and ceramic interface extending from the
rates of rise by the heat transfer mechanisms that are termination down along the MLC edge. This surface
used. Wave soldering uses liquid metal which has the crack can become elliptical or circular shaped in the
highest heat transfer rate and is the hardest soldering larger MLC sizes (1812 or larger). It is even seen in the
method to use without shocking any SM component. 1210 size (120 mils x 100 mils) in very severe cases.
Thermal shock has two manifestations, obvious
visible cracks and the more insidious, invisible micro
crack. Micro cracks are formed at or just under the
termination and ceramic interface along isothermal lines
(constant temperature lines) at slower temperature
rates of rise. Maximum shear occurs along these lines at
the termination and ceramic interface during the fastest
temperature increases of soldering.
Hot belt reflow is used mainly for hybrids or Table 2. CTEs and Ts of Component Materials
assemblies on alumina substrates and can cause
problems if high temperature solders such as especially tantalum capacitors. Table 2 lists CTEs and T
goldgermanium are used because of very high for common materials used to make chip resistors, SOTs
temperature rates of rise due to short heat zones. (small outline transistors), SOICs (small outline
A micro crack will form and propagate through the integrated circuits) and other epoxy resin molded
capacitor very quickly during rapid heat up and cool components.
down and can actually pull the termination right off of
All surface mount components are built with different
the component. Temperature rates of rise should be
materials that expand and conduct heat at different
limited to 4ºC/sec maximum for hot belt reflow. Most
rates. If a part is heated up too rapidly, it will crack or
surface mount assemblies use 63/37 eutectic solder or
internal seals are lost so the part will fail more quickly
low silver bearing solder such as 62/36/2 which
because the stress cannot spread throughout the
minimizes solder migration and termination leaching.
component body. Proper processing eliminates these
These solders have melting points near 186ºC. An ideal
problems but users and vendors must understand the
profile for IR or hot belt reflow with these solders will
component limitations and not exceed those limits.
have a peak temperature of 215-219ºC with 45-60
seconds above the melting point.
These guidelines allow reliable assemblies to be built. Reference
The multilayer ceramic capacitor is sensitive to thermal 1. B.S. Rawal, etc., “Factors Responsible for Thermal
shock but all electronic components share this problem Shock Behavior of Chip Capacitors.”
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