FirststepswithUVMWebinarFridayAugust2nd20139amPDTQ&ALog

Audience Question: Q: what exactly parent is here A: The parent of the given component in the UVM component hierarchy Audience Question: Q: Will the slides be emailed along with the audio? A: You can review the slides by watching the video recording of the webinar. I'm afraid we do not release the powerpoint presentation file for copyright reasons. Audience Question: Q: what is type_id? A: The name of a proxy class. You do not need to understand exactly what it is doing. Suffice to say that it is a piece of internal machinery in UVM that makes things easier. Audience Question: Q: is there a way to output the name of "this" component to know the name of it? A: Yes. Call get_full_name(), that is, this.get_full_name() Audience Question: Q: Can generics be set during build_phase? A: Yes. Not literally generics, but parameters stored in the configuration database. We will show some examples later .... Audience Question: Q: what if my DUT is written in Verilog instead of SystemVerilog. Do i need a special interface in order to bring it to the class based SystemVerilog environment ? A: You do not need to do anything special if your DUT is in Verilog (Well, Verilog is now just a subset of SystemVerilog, so if it's Verilog, it is SystemVerilog!). The DUT could even by in VHDL - again you would not need to do anything special. Audience Question: Q: what happens if we do not add uvm_test.raise_objection and simply start to consume time in the run task? A: The test will end when there are no objections raised, so that would not be very useful. A common begininers' error is forgetting to raise any objections. (Strictly, an objection must be raised before the first non-blocking assignment region of the UVM phase) Audience Question: Q: What is the use of my_env in this example? A: An "env" is just a hierarchical component in the test bench ... it does not have any special significance. The idea is to use "envs" as containers for other UVM components. Audience Question: Q: what is the hierarcy of this libraries A: The UVM library does not contain any hierarchy, as such. Audience Question: Q: when i use in function new parente = null? A: Then you would have a component with no parent. This is not a good idea unless the component really does not have a parent, but all the components you create should have a parent. Audience Question: Q: what is the difference between raising and dropping objections and using stop_request(). A: stop_request() is a relic from OVM and is deprecated in UVM. Unless you are having to work with legacy OVM code, you should forget stop_request() and global_stop_request() and use objections instead. Audience Question: Q: what is does config_db do A: The configuration database is a place to put parameters (or "resources") that are going to be used in the verification environment. You can think of it either as a way to parameterize the components in the verification environment or as a database for shared resources. Audience Question: Q: what is factory A: The mechanism used in UVM to give flexibility when instantiating components, transactions, and sequences. The idea is that you can override the type of object being manufactured by the factory at run-time, which gives you a lot of flexibility when customizing the behavior of existing verification code

Page1

FirststepswithUVMWebinarFridayAugust2nd20139amPDTQ&ALog
Audience Question: Q: Is using uvm_config_db a better way to pass interface definition to the driver from the test? or using the connect phase using assign_vi? A: assign_vi is not part of the UVM standard, just a user-defined function. However you set the virtual interface, the connect_phase would be a good place to do it. The config_db is one of the most flexible ways of passing information around the UVM component hierarchy before starting the run-time phases. Audience Question: Q: My understanding is that UVM is based on C++. Is that right? A: No, UVM is implemented using the class-based features of SystemVerilog, which themselves have a lot in common with the C++ language, but also a lot of differences. Audience Question: Q: Does the Power-On-Reset have the same restriction as the clock (in terms of not using a class) ? A: It would be best practice to generate the power-on reset using the same kind of coding style as the clock, that is, in module-based code. However, since the power-on reset usually only executes once, asynchronously, the synchronization issues are not as severe as for the clock. Audience Question: Q: Does uvm_config_db handle a_class differently than extension_of_a_class? A: They are very different. When you extend a class, you are creating a new class, which is itself a new data type. The configuration database is a place you can store values and objects.

Audience Question: Q: if we don't want the verbose method to output on every clock edge, instead output info on packet transfers, what does one do? A: Execute some code on every packet transfer instead of on every clock edge. Since you are writing procedural code (not RTL code), this is very straightforward. (It would not be such a good idea to generate a message on every clock edge and then try to disable it in some way after-the-fact, because that would be less efficient.) Audience Question: Q: What is the advantage of having a "virtual" interface instead of a regular interface? A: They are very different things. An interface is a structural language construct very similar to a module. A virtual interface is, in effect, a fancy variable that can hold a reference to an interface instance. Audience Question: Q: on transaction completion i meant. A: You would write some code to execute as the transaction completes, probably in the sequence or the driver. Audience Question: Q: Does the uvm_config_db handle a_class differently than the uvm_config_db handles extension_of_a_class? A: They are very different. When you extend a class, you are creating a new class, which is itself a new data type. The configuration database is a place you can store values and objects. Audience Question: Q: what is the function of monitor A: A monitor is a passive component that monitors activity on some interface to the DUT and then passes that information on (using a transaction) to other components for analysis of various kinds, such as checking, logging, or coverage collection. Audience Question: Q: Do we have to use all the phases in our code (including clean up phases)? A: No, you can just use the phases that you need. Audience Question: Q: So for the question of uvm_config_db handling a class differently than extension of the class, can factory override be done before this uvm_config_db for it to handle the base class object as extended class object? A: No. A factory override is only relevant to the creation of a new object (component/transaction/sequence). Setting and getting values from the config_db does not need to involve the creation of any new objects, so does not invoke the factory. There is very little to be gained by trying to combine the action of the factory with the configuration database. Think of them as two separate but complementary mechanisms. Audience Question: Q: difference between checker tracker and monitor A: This is just semantics. In UVM, the term monitor is commonly used to refer to a component that is connected to some pin-level interface, but there is nothing to stop you from having a monitor connected to some more abstract interface. A checker is just a component that does some checking.

Page2

FirststepswithUVMWebinarFridayAugust2nd20139amPDTQ&ALog
Audience Question: Q: What is the difference between `uvm_component_utils and `uvm_object_utils? A: You use `uvm_component_utils to register UVM components and use `uvm_object_utils to register everything else. Only components are linked into the component hierarchy, so only components take a reference to their parent component as a constructor argument. Audience Question: Q: if asked to explain the sequencer and driver communication in few short ?? A: The driver pulls down transactions from the sequence one-by-one. The sequence runs on the sequencer that the driver is connected to. Audience Question: Q: where do we set starting_phase? Doesn't the entire sequence processing happen on the run_phase? A: You set the starting_phase member of the sequence object just before starting the sequence, which could be done from a test or from another sequence. Audience Question: Q: let know the communication of sequencer and drivers using UVM syntax in short A: The sequence calls create-start_item-randomize-finish_item. The driver calls get()...put() or get_next_item()...item_done() Audience Question: Q: Why are you creating the sequence on the run_phase and not in the build_phse ? A: It makes sense to create sequences in the run phase because sequences represent dynamic stimulus. Audience Question: Q: what is the difference between uvm_config_db and uvm_resource_db? A: The uvm_config_db is layered on top of the uvm_resource_db, that is, when you use the uvm_config_db you are actually using the uvm_resource_db underneath. With the resource database, scopes are just uninterpreted text strings. With the config db, the scopes are interpreted as paths in the UVM component hierarchy. Audience Question: Q: in your example, the drop_objection is done within the sequencer while there is a forever loop within the driver. I am wondering once the drop_objection is perform, the driver will still try to fetch the next seq. Right ? Is there any problem ? A: Right. The sequence raises an objection when it starts, and drops that objection when it is finished. The driver does not object to the test ending while it is waiting for the next transaction, so if there are no further transactions, the test can just end. You could write the driver so that it raises an objection whenever it receives a new transaction and drop that objection before waiting for the next transaction. Audience Question: Q: UVM I guess. OVM does not have the concept for run time phases does it? In OVM the phase sequence is pretty much static right? build -> connect -> run A: Right. And starting_phase did not exist in OVM, as I remember. Audience Question: Q: will this webinar avaible at doulos website? A: Not on the website for a whle yet, but we will send you a copy of the recording on Monday evening for you to review it. Audience Question: Q: Is it possible to download the webinar slides? A: You can review the slides by watching the video recording of the webinar. A link to the recording will be sent to you on Monday evening next week. Audience Question: Q: Thank you so much, Very informative for someone starting with UVM A: You are welcome Audience Question: Q: Who should contact for further training? A: Please contact your local office - visit www.doulos.com/contacts Thanks for your interest!

Page3