332:479 Concepts in VLSI Design: CMOS Transistor Theory

332:479 Conc ept s i n VLSI
Desi gn
Lec t ur e 6
CMOS Tr ansi st or Theor y
David Harris and Michael Bushnell
Harvey Mudd College and Rutgers University
Spring 2004
Concepts in VLSI Des. Lec. 6 Slide 2 12/4/2009
Out l i ne
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
Adjustments for non-ideal 2
nd
-order effects
Small-signal MOSFET model
Material from: Material from: CMOS VLSI Design CMOS VLSI Design,,
by Weste and Harris, Addison by Weste and Harris, Addison--Wesley, 2005 Wesley, 2005
I nt r oduc t i on
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (AV/At) -> At = (C/I) AV
Capacitance and current determine speed
Also explore what a degraded level really means
MOS Char ac t er i st i c s
MOS majority carrier device
Carriers: e
--
in nMOS, holes in pMOS
V
t
channel threshold voltage (cuts off for
voltages < V
t
)
nMOS Enhanc ement
Tr ansi st or
Moderately doped p type Si substrate
2 Heavily doped n
+
regions
I vs. V Pl ot s
Enhancement and
depletion
transistors
CMOS uses
only
enhancement
transistors
nMOS uses
both
Mat er i al s and Dopant s
SiO
2
low loss, high dielectric strength
High gate fields are possible
n type impurities: P, As, Sb
p type impurities: B, Al, Ga, In
Bi pol ar vs. MOS
Bipolar p-n junction metallurgical
MOS
Inversion layer / substrate junction field-induced
Voltage-controlled switch, conducts when V
gs
V
t
e
--
swept along channel when V
ds
>0 by horizontal component of
E
Pinch-off conduction by e
-
drift mechanism caused by positive
drain voltage
Pinched-off channel voltage: V
gs
V
t
(saturated)
Reverse-biased p-n junction insulates from the substrate
>
J FET vs. FET Tr ansi st or s
Junction FET (J FET) channel is deep in
semiconductor
MOSFET For given V
ds
& V
gs
, I
ds
controlled by:
Distance between source & drain L
Channel width W
V
t
Gate oxide thickness t
ox
c gate oxide
Carrier mobility
J FET Tr ansi st or
MOS Capac i t or
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
<0
(b)
+
-
0 <V
g
<V
t
depletion region
(c)
+
-
V
g
>V
t
depletion region
inversion region
Ter mi nal Vol t ages
Mode of operation depends on V
g
, V
d
, V
s
V
gs
=V
g
V
s
V
gd
=V
g
V
d
V
ds
=V
d
V
s
=V
gs
- V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence V
ds
> 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
nMOS Cut of f
No channel
I
ds
= 0
+
-
V
gs
=0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
nMOS Li near
Channel forms
Current flows from d to
s
e
-
from s to d
I
ds
increases with V
ds
Similar to linear resistor
At drain end of channel,
only difference between
gate & drain voltages
effective for channel
creation
+
-
V
gs
>V
t
n+ n+
+
-
V
gd
=V
gs
+
-
V
gs
>V
t
n+ n+
+
-
V
gs
>V
gd
>V
t
V
ds
=0
0 <V
ds
<V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
nMOS Sat ur at i on
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
>V
t
n+ n+
+
-
V
gd
<V
t
V
ds
>V
gs
-V
t
p-type body
b
g
s
d
I
ds
I -V Char ac t er i st i c s
In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
Channel Char ge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
=
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
=3.9)
polysilicon
gate
Channel Char ge
Gate oxide channel
Q
channel
= CV
C =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
=3.9)
polysilicon
gate
Channel Char ge
Gate oxide channel
Q
channel
= CV
C = C
g
= c
ox
WL/t
ox
= C
ox
WL
V =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
=3.9)
polysilicon
gate
C
ox
= c
ox
/ t
ox
Channel Char ge
Gate oxide channel
Q
channel
= CV
C = C
g
= c
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
=3.9)
polysilicon
gate
C
ox
= c
ox
/ t
ox
Car r i er vel oc i t y
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v =
Car r i er Vel oc i t y
v = E called mobility
E =
E = V
ds
/L
Time for carrier to cross channel:
t =
E = V
ds
/L
Time for carrier to cross channel:
t = L / v
nMOS Li near I -V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
ds
I =
nMOS Li near I -V
Now we know
How much charge Q
channel
is in the channel
channel
ds
Q
I
t
=
=
nMOS Li near I -V
Now we know
How much charge Q
channel
is in the channel
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V
=
| |
=
|
\ .
| |
=
|
\ .
ox
=
W
C
L

nMOS Sat ur at i on I -V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
ds
I =
If V
gd
< V
t
When V
ds
> V
dsat
= V
gs
V
t
2
dsat
ds gs t dsat
V
I V V V
| |
=
|
\ .
If V
gd
< V
t
When V
ds
> V
dsat
= V
gs
V
t
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V
| |
=
|
\ .
=
nMOS I -V Summar y
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
<
| |
= <
|
\ .
>
Shockley 1
st
order transistor models
Ex ampl e
We will be using a 0.6 m process for your project
From AMI Semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L

| | -
| |
= = =
| |
\ .
\ .
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
=5
V
gs
=4
V
gs
=3
V
gs
=2
V
gs
=1
pMOS I -V
All dopings and voltages are inverted for pMOS
Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume
n
/
p
= 2
Summar y
Current Characteristics of MOSFET
Calculation of V
t
andImportant 2
nd
-Order Effects
Small-Signal MOSFET Model
Models in this lecture
For pedagogical purposes only
Obsolete for deep-submicron technology
Real transistor parameter differences:
Much higher transistor current leakage
Body effect less significant than predicted
V
t
is lower than predicted

332:479 Concepts in VLSI Design: CMOS Transistor Theory

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332:479 Conc ept s i n VLSI

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