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PROGRAMMABLE 6
ASIC I/O CELLS
Key concepts:
Input/output cell (I/O cell) • I/O requirements • DC output • AC output • DC input • AC input •
Clock input • Power input
6.1 DC Output
1
2 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
Keywords: totem-pole output buffer • similar to TTL totem-pole output • two n-channel
transistors in a stack • reduced output voltage swing
VDD VDD
M1 IO M1 IO
D1
I/O
pad I OL
IO VO IO VO I OL
M2 + M2 +
–IOH –IOH
D2
VDD VO VO
6.2 AC Output
Keywords: bus transceivers • bus transaction (a sequence of signals on a bus) • floating a bus
• bus keeper • trip points • three-stated (high-impedance or hi-Z) • time to float • disable time,
time to begin hi-Z, or time to turn off • slew • sustained three-state (s/t/s) • turnaround cycle
4 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
VOHmin VILmax
Three-state bus timing (Xilinx)
BUSA.B1
tfloat t active VOLmax
The on-chip delays, t2OE and t3OE, t slew
for the logic that generates signals CHIP2.OE 50%
(ACT2/3)
CHIP2.E1 and CHIP3.E1 are
derived from the timing models CHIP3.OE
(XC3000) 50%
(The minimum values for each chip
would be the clock-to-Q delay times)
50%
CLK
Vo1
VDD VDD VDD
VOHmin
M2 M4
RL
(b) 2.5V
I OL
IN1 OUT1 OUT2 1.4V
I1 O2 VOLmax
M3 Vo1 '1' M5 Vo2
TTL '1' Vo2 t
M1
Vi1 '0' to '1' false '1'
(c)
GND 1.4V
I OL VOLmax
VSS
RS Vi1 t
M1 switching VOLP
causes ground LS 1.4 V 3.0V
bounce 0V (d) false '0'
1.4V
t 0V
(a)
t
Supply bounce
A substantial current IOL may flow in the resistance, RS, and inductance, LS, that are be-
tween the on-chip GND net and the off-chip, external ground connection
(a) As the pull-down device, M1, switches, it causes the GND net (value VSS) to bounce
(b) The supply bounce is dependent on the output slew rate
(c) Ground bounce can cause other output buffers to generate a logic glitch
(d) Bounce can also cause errors on other inputs
Keywords: simultaneously-switching outputs (SSOs) • quiet I/O • slew-rate control • I/O
management • packaging • PCB layout • ground planes • inductance
6 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
V1 V2
R0 C in 2t f tf
5V 5V
Vin V1 V2
0 t 0 t V1 2tf
Z0
DR TX line RX VOHmin
V1 V2
Z0 Z0 Vin
2.5V
R0
5V +
tf Vin VOLmax
1ns per 15cm
0 t t
(a) (b) (c)
Transmission lines
(a) A printed-circuit board (PCB) trace is a transmission (TX) line (Z0 = 50Ω–100Ω)
(b) A driver launches an incident wave, which is reflected at the end of the line
(c) A connection starts to look like a TX line when the rise time is about 2 × line delay (2tf)
6.3 DC Input
ASICs... THE COURSE 6.3 DC Input 7
VDD
R1 ≈ 300 Ω
V1 Z0 V2 Z0 Z0
≈ 100 Ω ≈ 100 Ω ≈ 100 Ω
TX line
Cin R0 ≈ 100 Ω R2 ≈ 100 Ω
Z0 Z0 Z0
≈100Ω ≈ 100 Ω ≈ 100 Ω
R1 R0 ≈ 100 Ω R0 ≈ 100 Ω
≈ 50 Ω +
VB C1 ≈ 100pF
A switch input
(a) A pushbutton switch Vi1 Switch closes,
connected to an input buffer VDD RPU 5V bounces, and
I/O closes again.
with a pull-up resistor pad
5–50k Ω
Vi1 Vi2
(b) As the switch bounces I1 I2 1.4V
several pulses may be input 0V
Cin t1 t4 t
generated buffer Vi 2
≈ 10pF
We might have to debounce t2 t3 t5
this signal using an SR flip-flop (a) (b)
or small state machine
8 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
DC input
(a) A Schmitt-trigger inverter • lower switching threshold • upper switching threshold •
difference between thresholds is the hysteresis
(b) A noisy input signal
(c) Output from an inverter with no hysteresis
(d) Hysteresis helps prevent glitches
(e) A typical FPGA input buffer with a hysteresis of 200mV and a threshold of 1.4V
ASICs... THE COURSE 6.3 DC Input 9
V1 V2 input output
buffer/inverter buffer
V2 V2 Vin Vout
5V 5V
slope=–1 Vin is here VDD Vout is
for logic '1' VIHmin VOHmin here for
slope logic '1'
bad
=–1
0V 0V Vin is here VOLmax Vout is
5V V1 5V V1 VILmax
here for
for logic '0' VSS
VILmax =1V VIHmin = 3.5V logic '0'
CMOS
inputs outputs CMOS CMOS CMOS
logic
Noise margins
(a) Transfer characteristics of a CMOS inverter with the lowest switching threshold
(b) The highest switching threshold
(c) A graphical representation of CMOS logic thresholds
(d) Logic thresholds at the inputs and outputs of a logic gate or an ASIC
(e) The switching thresholds viewed as a plug and socket
(f) CMOS plugs fit CMOS sockets and the clearances are the noise margins
10 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
VDDIO VDDINT
Mixed-voltage systems
TTL CMOS3V
(a) TTL levels 5.0V
3.3V
(b) Low-voltage CMOS 2.7V 2.4V
2.0V 2.0V
levels • JEDEC 8 • 0.8V 0.4V 0.8V 0.4V
3.3±0.3V 0.0V 0.0V
TTL CMOS3V core I/O
(c) Mixed-voltage ASIC •
(a) (b) (c)
5V-tolerant I/O • V DDint
and VDDI/O VDD1 +
CHIP1 + VDD 2
M1 D1 powers D3 M3
(d) A problem when con- 5.5V CHIP2 3.0V
necting two chips with '0' I2
different supply
M2 R in
voltages—caused by the OUT1 IN2
≈ 1k Ω
input clamp diodes D4 M4
(d) D2
CHIP1 CHIP2
12 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
6.4 AC Input
Keywords and concepts: input bus • sampled data • clock frequency of 100kHz • FPGA • sys-
tem clock • 10MHz • Data should be at the flip-flop input at least the flip-flop setup time before
the clock edge. Unfortunately there is no way to guarantee this; the data clock and the system
clock are completely independent
6.4.1 Metastability
tsu 1 tr t pd t su2
I/O asynchronous
Metastability pad input
D1 Q1 D2
(a) Data coming from one clocked (a) CL Q2
system is an asynchronous input fdata
fclk
to another
CLK2 CLK
(b) A flip-flop (or latch, a sampler)
has a very narrow decision window decision setup and hold window
bounded by the setup and hold window (limits of decision window)
times to resolve the input
CLK 50%
If the data input changes inside the
D1
decision window (a setup or hold-
time violation) the output may be (b) metastable output
Q1
metastable—neither '1' or '0'—an
upset D2
Q2
tr t pd
tsu2
ASICs... THE COURSE 6.4 AC Input 13
1 exp tr/τc
MTBU = –––––––––––––– = ––––––––––––––
pfclockfdata fclock fdata
where fclock is the clock frequency and fdata is the data frequency
A synchronizer is built from two flip-flops in cascade, and greatly reduces the effective val-
ues of τc and T0 over a single flip-flop. The penalty is an extra clock cycle of latency.
14 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
MTBF/s
104
100
resolution
2 3 4 5 time, t r /ns
CL tskew
clock-buffer cell skew
tPG
CLK latency
∆ = variable routing delay
CLK 50%
tPG CLB
CLKi
t skew
CLKi
CLKn
I/O cell
tPG
t skew
Dn t PGmax =8ns
tPICK = 7ns t PSUFmin =2ns
clock t PSUF
spine
CLKn (b) (c)
Clock input
(a) Timing model (Xilinx XC4005-6)
(b) A simplified view of clock distribution • clock skew • clock latency
(c) Timing diagram
(Xilinx eliminates the variable internal delay tPG, by specifying a pin-to-pin setup time,
t PSUFmin =2ns)
16 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
CLK D1
T = programmable delay (with delay) tPH (zero)
t PG (variable) t PSU
(a) (b)
t OKPOF =7.5ns
Registered output tICKOF =15.5ns CLK
Key concepts: Power-on reset sequence • Xilinx FPGAs configure all flip-flops (in either the
CLBs or IOBs) as either SET or RESET • after chip programming is complete, the global
SET/RESET signal forces all flip-flops on the chip to a known state • this may determine the ini-
tial state of a state machine, for example
18 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
The Xilinx LCA (Logic Cell Array) timing model (XC5210-6). (Source: Xilinx.)
20 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
Key concepts: IEEE boundary-scan standard 1149.1 • Many FPGAs contain a standard
boundary-scan test logic structure with a four-pin interface • in-system programming (ISP)
MAX 5000 and MAX 7000 series Logic Array Block I/O
(LAB) pad
The I/O pin feedback allows the I/O
pad to be isolated from the macrocell 6–12 IOCs
per LAB
It is thus possible to use a LAB without
using up an I/O pad (as you often fast input to macrocell (7000E only)
have to do using a PLD such as a I/O pin
22V10) feedback
FastTrack Interconnect
data in
A simplified block diagram of the Altera output enable
M
I/O Element (IOE), used in the FLEX I/O
8000 and 10k series pad
D Q IO
The MAX 9000 IOC (I/O Cell) is similar B1
3-state
The FastTrack Interconnect bus is the FF1 buffer
chipwide interconnect CLK
6.9 Summary
Key concepts:
Outputs can typically source or sink 5–10mA continuously into a DC load
Outputs can typically source or sink 50–200mA transiently into an AC load
Input buffers can be CMOS (threshold at 0.5VDD) or TTL (1.4V)
Input buffers normally have a small hysteresis (100–200mV)
CMOS inputs must never be left floating
Clamp diodes to GND and VDD are present on every pin
Inputs and outputs can be registered or direct
I/O registers can be in the I/O cell or in the core
Metastability is a problem when working with asynchronous inputs
22 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE