Spartan6 Verilog

OPENPUU
Spartan6 Verilog
Designed : www.openpuu.com
Sell : http://openpuu.taobao.com
-............................................................................................................................. 3
.............................................................................................................................. 3
.................................................................................................................................. 5
.......................................................................................................................................... 6
FLASH.........................................................................................................................7
JTAG ................................................................................................... 8
XC6SLX9-TQG144 BANK............................................................................................. 10
ADC And DAC.......................................................................................................................11
SDRAM..................................................................................................................................12
USB COM....................................................................................................................... 13
VGA PS2......................................................................................................................... 13
4LEDS 4 BUTTONS....................................................................................................... 14
24LC02.................................................................................................................................. 15
............................................................................................................................ 16
10M .......................................................................................................................... 17
IO...................................................................................................................................18
PCB Top View....................................................................................................................... 19
Verilog -.............................................................................................................. 20
RunLed1 1.......................................................................................................... 20
RunLed2 1.......................................................................................................... 29
Button 1............................................................................................................... 30
-........................................................................................................................... 33
UartLoop 3.......................................................................................................... 33
Uart Block Ram 4............................................................................................... 43
PS2 Uart 4.......................................................................................................... 51
VGA 3.................................................................................................................. 57
............................................................................................................................ 63
SHIFT8 1.............................................................................................................63
ExpandIO 3......................................................................................................... 67
SpiDisplay 3........................................................................................................ 77
SpiCounter 4.......................................................................................................83
ADC AD7478 4................................................................................................... 87
DAC AD5300 4................................................................................................... 93
1.....................................................................................................................................99
I2C24C02 5.........................................................................................................99
SDRAM 5.......................................................................................................... 118
IP-CORE ........................................................................................................................... 145
ROM 3..............................................................................................145
3............................................................................................... 152
3............................................................................................... 161
3........................................................................................... 170
RAM 3......................................................................... 179
FIFO 3................................................................................................................ 188
DCM.....................................................................................................................................194
2.................................................................................................................................. 202
2
SDRAM 100MHZ 5........................................................................................... 202

5.............................................................. 207

--
Designator
Description
U1
XC6SLX9-TQG144 Xilinx Spartan6 FPGA
U2
PL2303 USB TO UART
U3
64Mbit Independent SDRAM
U4
LDOO 3.3V A05
U7
LDOO 1.2V A03
U6
M25P16 16Mbits SPI Flash
U9
AD7478 SPI Serial 8bits ADC with 1MSPS
U10
AD5300 SPI Serial 8bits DAC with 1MSPS
U11
OP340 Op amp
U12
ENC28J60T/SS 10M Ethernet
U13
HR911105A Network transformer
U14,U15
74HC595
U16
24LC02
SG1
50MHZ Crystal
Y1
12MHZ Crystal
Y2
25MHZ Crystal
J1
PS2
J2
VGA
USB_MIN
USB Port
4
JP1
S1,S2,S3,S4
DC2.0 Power Input

Push Button
S5
Power Switch select Power source
P1
ADC input and DAC output
P2
User IO
P3
JTAG Program Port
D0,D1,D2,D3
4bits LED
D4
S14 Protector
D8
4Bits Seven Segment LED
D9
IN4148 P3
Done
Q1
alarm1
LED system state LED

NPN
Alarm
4bits
Seven
Segment Display
4bits Button
4bits
SDRAM
PS2
JTAG
VGA
USB TO
LAN
SWITCH
M25P16
ADC DAC
User IO
XC6SLX9X-TQG144
24LC02

Mini USB DC2.0 S5
500MA
LDO ASM117-3.3V 3.3V .
LDO ASM117-1.1V 1.2V .
FLASH
50MHZ 16Mbits SPI FLASH,
M0,M
JTAG
FPGA 0.1uf P3 .
XC6SLX9-TQG144 BANK
10
ADC And DAC

AD7478
1MSPS 8bits SPI ADC.
AD5300
1MSPS 8bits SPI DAC.
OP340 .
3.3V 5V,
11
SDRAM
12
USB COM
VGA PS2
13
4LEDS 4 BUTTONS
14
24LC02
15
16
10M
17
IO
:
IO
18
PCB Top View
19
--
Verilog
RunLed1 1
Figure 1: RunLed Module

Table 1: Module Function Description
Clk
Input System Clock
Rst
Input System Reset
Led
Input Drive 4 bits led
1 module RunLed(Clk,Rst,Led);
2
3 input Clk;
4 input Rst;
5 output [3:0] Led;
6
7 reg [3 :0] Led;
8 reg [1 :0] Ledn;
9 reg [24:0] C1;
10 wire C1_Clk;
11
12 assign C1_Clk = (C1 == 25'd24999999 ) ? 1 : 0;
13
14 always @( posedge Clk )
15
if( !Rst )C1 <= 25'd0;
16
else if(C1 < 25'd24999999 )C1 <= C1 + 1'b1; // C1 Time counter 0.5s
17
else C1 <= 25'd0;
18
20
20
if(!Rst) Ledn<= 2'd0;
21
else if( C1_Clk ) Ledn <= Ledn + 1'b1;
22
23 always @( posedge Clk )begin
24
if( !Rst )begin Led<=4'b1111; end
25
else begin
26
Led <= 4'b1111; Led[Ledn] <= 4'd0;
27
end
28 end
29
30 endmodule
L1 L30
module RunLed();
endmodule
Top Module Sub Module main
module, Top Module 4
Top ModuleTop module FPGA
module RunLed(Clk,Rst,Led); Clk,Rst,Led
Top Module FPGA

FPGA
module() endmodule
input input
Clk;
output output [3:0] Led;

21
C,C++,BASIC
verilog [a:b]C
Output wire ,output ,inout Inout
24LC02
reg reg [3 :0] Led;
wire wire C1_Clk; C1_Clk wire

input ,output ,inout ,wire.
always @( ) always @( posedge Clk )

posedge Clk negedge Clk
* *
begin end
assign output ,inout wire

assign
if () else()
if () else if()
22

; C
case case
<= always
= always
always @( posedge clk ) begin //

A <= B;
C <= A;
end
A B, C A
always @( posedge clk ) begin //
A = B;
C = A;
end
A B, C B
+-*/ % veriolg
C
/,% 2
23
C1 <= C1 + 1'b1;
<
A<B A B
A B TURE, FALSE,
L14-L17
<= A<=B A B A B TURE,

FALSE
> A>B A B A B TURE, FALSE
>= A>=B A B B TURE,

FALSE
== A==B A B A B TURE,
FALSE
!= A!=B A B A B TURE FALSE.
>> A>>2 A 2
<< A<<2 A 2
~ A=8b1111_0000; ~A 8b0000_1111;
24
&
A=8b1111_0000; B=8b1010_1111; A&B
8b1010_0000;
A=8b1111_0000; B=8b1010_1111; A^B
8b0101_1111;
&& A=1,B=2; A&&B TRUE; A=1,B=0, A&&B

FALSE.
A= B ? C : D B TRUE C A, D
A.
assign C1_Clk = (C1 == 25'd24999999 ) ? 1 : 0; C1_Clk,
wire C1 == 25'd24999999 1 0.
, verilog ,a,b,c
<={d,e,f}; wire a,b,c={d,e,f};
FALSH 0TRUE 1
170 verilog
8b1010_1010;
25
8d180;
16 8hAA;
50%
Figure 2: Path and delay time
FPGA always
@(posedge Clk) A<=B ,
50M
while for if() else if()

26

1 module RunLed_tb ;
2
3 // Inputs
4 reg Clk;
5 reg Rst;
6 // Outputs
7 wire [3:0] Led;
8 // Instantiate the Unit Under Test (UUT)
9 RunLed uut (
10
.Clk(Clk),
11
.Rst(Rst),
12
.Led(Led)
13
);
14
initial begin
15
// Initialize Inputs
16
Clk = 0;
17
Rst = 0;
18
#10 Clk = !Clk;
19
#10 Clk = !Clk;
20
#10 Clk = !Clk;
21
Rst = 1;
22
forever #10 Clk = !Clk;
23
end
24
25 endmodule
99%
FPGA
Top Module RunLed Sub Module RunLed
initial begin
end
#10 10ns #100 100ns.

27

L15-L21
forever #10 Clk = !Clk; 20ns forever
Figure 3:RunLed Simulation
28
RunLed2 1
1 module RunLed(Clk,Rst,Led);
2
3 input Clk;
4 input Rst;
5 output [3:0] Led;
6
7 reg [3 :0] Led;
8 reg [24:0] C1;
9 wire C1_Clk;
10
11 assign C1_Clk = (C1 == 25'd24999999 ) ? 1 : 0;
12
14
if( !Rst )C1 <= 24'd0;
15
else if(C1 < 25'd24999999 )C1 <= C1 + 1'b1;
16
else C1 <= 14'd0;
17
19
if( !Rst ) Led<=4'b1110;
20
else if(C1_Clk) Led <= {Led[2 : 0] , Led[3]};
21 end
22
23 endmodule
LED Led <= {Led[2 : 0] , Led[3]};
verilog
Led[2:0] Led[3]
a,b,c<={d,e,f}; wire
a,b,c={d,e,f};
29
Button 1
2 LED
Figure 1: Button Module

Clk
Input
System Clock
Rst
Input
System Reset
Led
Output Drive 4 bits led
Sw1
Input
Input button
Sw2
Input
Input button
Figure 2 : Button Simulation
30
Module:
1 module Button(Clk,Rst,Sw1,Sw2,Led);
2
input Clk;
3 input Rst;
4 input Sw1;
5 input Sw2;
6 output [3 : 0] Led;
7
8 reg [20 : 0]C1;
9 reg [20 : 0]C2;
10 reg [1 :0 ]Ledn;
11 reg [3 :0 ]Led;
12 reg Sw1D,Sw1D1,Sw2D,Sw2D1;
13 wire
Sw1Up,Sw2Up;
14
15 assign Sw1Up = Sw1D && !Sw1D1;
16
17 assign Sw2Up = Sw1D && !Sw2D1;
18
19 always @(posedge Clk ) begin
20
if( !Rst )begin
21
Sw1D1 <= 1'b0; Sw2D1 <= 1'b0;
22
end
23
else begin
24
Sw1D1 <= Sw1D; Sw2D1 <= Sw2D;
25
end
26 end
27
28 always @(posedge Clk )
29
if( !Rst )begin
30
Sw1D <= 1'b1; Sw2D <= 1'b1;
31
end
32
else begin
33
if( C1[ 20 ] ) Sw1D <= 1'b0;
34
else if( !Sw1D && C1==0 ) Sw1D <=1'b1;
35
36
if( C2[ 20 ] ) Sw2D <= 1'b0;
37
else if( !Sw2D && C2==0 ) Sw2D <=1'b1;
38
end
39
40 always @(posedge Clk )
41
if( !Rst )begin
42
C1 <= 21'd0; C2 <= 21'd0;
43
end
44
else begin
45
if( !Sw1 ) begin if( !C1[ 20 ] ) C1 <= C1 + 1'b1; end
46
else if( C1 > 0 ) C1 <= C1 - 1'b1;
47
31
48
if( !Sw2 ) begin if( !C2[ 20 ] ) C2 <= C2 + 1'b1; end
49
else if( C2 > 0 ) C2 <= C2 - 1'b1;
50
end
51
53
if(!Rst)begin
54
Ledn <= 4'd0;Led <= 4'h0;
55
end else begin
56
if( Sw1Up ) Ledn <= Ledn + 1'b1;
57
else if( Sw2Up ) Ledn <= Ledn - 1'b1;
58
Led <= 4'hF;
59
Led[Ledn] <= 1'b0;
60
end
61
62
63 endmodule
C1,C2
Led
32

--
UartLoop 3
Figure 1: UartLoop Module

Table 1:main Module Function Description
Clk
Input
System Clock
Rxd
Input
Uart serial in
Txd
Output
Uart serial out
Top module Sub module

Module main
1 module main(Clk,Rxd,Txd);
2 input Clk;
3 input Rxd;
4 output Txd;
5
6 wire IsRxdDone,IsTxdDone;
7 wire [7:0]Din;
8
9 UartRxd U1 (.Clk(Clk),.Dout(Din),.IsDone(IsRxdDone),.Rxd(Rxd));//recieve
10 UartTxd U2 (.Clk(Clk),.IsSta(IsRxdDone),.IsDone(IsTxdDone),.Din(Din),.Txd(Txd));
//send
11 endmodule
33
Top module UartRxd Uart_Txd.

UartRxd UartTxd U1,U2
U1 .IsDone(IsRxdDone), IsDone UartRxd

IsRxdDone UartRxd IsDone
Figure 3: UartTxd Module

Txd Module Function Description
Table 3:Uart
3:UartT
Clk
Input
System Clock
Txd
Output
Uart serial out
IsSta
IsDone
Output
Output
Start Send Data when from 0 to 1

Data have been sent when from 0 to 1
Din
Output
Data needed to been sent
IsDone 1 IsSta
IsSat 0 1 1
34
Figure 4: Uart Timing
Uart
A:
,
B: 8bits ,
C:
1 module UartTxd (Clk,IsSta,Din,IsDone,Txd);

2
3 input Clk;
4 input IsSta;
5 input [7:0] Din;
6 output IsDone;
7 output Txd;
8
9 reg [10:0] C1;
10 reg ClkEn;
11 reg Clkt;
12 always @ (posedge Clk ) //bound rate :38400 Clk : 50MHZ Clk divider : 1302
13
if( ClkEn ) begin
14
if( C1< 11'd1301 )begin Clkt <= 11'd0; C1 <= C1 + 1'b1; end
15
else begin Clkt <= 1'b1; C1 <= 11'd0; end
35
16
end
17
else begin Clkt <= 1'b0; C1 <= 11'd0; end
18
19
20 reg IsSta1,IsSta2;
21 always @ (posedge Clk) begin
22
IsSta1<=IsSta;IsSta2<=IsSta1;
23 end
24
25 parameter IDLE = 1'b0;
26 parameter SEND = 1'b1;
27
28 reg [0:0]s;
29 reg Txd;
30 reg IsDone;
31 reg [7:0] DBin [3:0] ;
32 reg [9:0] Dsin;
33 reg [2:0] C2;
34 wire TxdUp;
35 reg [3:0]i;
36
37 assign TxdUp = IsSta1 & (!IsSta2);
38
40
if( TxdUp )begin // 4bits fifo
41
DBin[0] <= Din;
42
DBin[1] <= DBin[0];
43
DBin[2] <= DBin[1];
44
DBin[3] <= DBin[2];
45
C2 <= C2 + 1'b1;
46
end
47
48
if(C2 < 3'd2) IsDone <= 1'b1; else IsDone <= 1'b0;
49
50
case(s)
51
IDLE:
52
begin
53
i <= 1'b0;Txd <= 1'b1;ClkEn <= 1'b0; Dsin[0] <= 1'b0; Dsin[9] <= 1'b1;
54
if(C2 > 0&&(!TxdUp) )begin Dsin[8:1] <= DBin[C2-1'b1];C2 <= C2 - 1'b1;s
<= SEND;ClkEn <= 1'b1; end
55
end
56
SEND:
57
if( Clkt )begin
58
if( i< 4'd10 )begin Txd <= Dsin[i];i <= i + 1'b1;end else s <= IDLE;
59
end
60
endcase
61 end
62 endmodule
36
verilog
IDLE , C2 0
TxdUp
FLASH 1byte
SEND SEND 10bits 1bit 8bits
1bit
case()
endcase
if()else if()
case
Figure 5: case module
38400 50MHZ,
50000000/38400-1=1031
parameter define
define
parameter IDLE = 1'b0; parameter Parameter chipscope
define.
37
.
DBin[C2-1'b1];
Dsin[8:1] <= DBin[C2-1'b1];
assign TxdUp = IsSta1 & (!IsSta2);

always @ (posedge Clk) begin
IsSta1<=IsSta;IsSta2<=IsSta1;
end
2 2
TxdUp
D Figure 6 D
Figure 6: Three registers synchronization
38
90%99%
Figure 7
Figure 7: Metastable Timing
Tmet
Tmet Tmet
Tmet
Figure 8
39
Figure 8: Metastable Timing
Module Uart Rxd

1 module UartRxd(Clk,Dout,IsDone,Rxd);
2
3 input Clk;
4 output [7:0] Dout;
5 output IsDone;
6 input Rxd;
7
8 reg Clk16;
9 reg [6 : 0]C1;
10 reg Clk16En;
11
12 always @ (posedge Clk ) // Clk : 50MHZ Clk divider : 80 16 times sample rates
of bound rate
13
if( Clk16En )begin
14
if( C1 < 7'd80 )begin Clk16 <= 7'd0;C1 <= C1 + 1'b1;end
15
else begin Clk16 <= 1'b1; C1 <= 7'd0; end
16
end else begin Clk16 <= 1'b0; C1 <= 7'd0; end
40
17
18 reg RxdD1,RxdD2;
19 always @ ( posedge Clk ) begin
20
RxdD1 <= Rxd; RxdD2 <= RxdD1;
21 end
22
23 parameter IDLE= 1'b0;
24 parameter SAMP= 1'b1;
25
26 reg IsDone;
27 reg [7:0] Dout;
28 reg [3:0] C2;
29 reg [3:0] C3;
30 reg [3:0] i;
31 reg IsSta= 1'b0;
32 reg [0:0]s= 1'b0;
33 always @(posedge Clk) begin
34
IsDone <= 1'b0;
35
case ( s )
36
IDLE:
37
begin
38
i <= 4'd0; C2 <= 4'd0; C3 <= 4'd0; IsSta<= 1'b0; Clk16En <= 1'b0;
39
if( RxdD2 && (!RxdD1) )begin Clk16En <= 1'b1; s <= SAMP; end
40
end
41
SAMP:
42
if(Clk16)begin
43
if(C2 < 4'd15) begin
44
C2 <= C2 + 1'b1;
45
if(!RxdD2) C3 <= C3+1; else C3 <= C3;
46
if( i==4'd8&&C2==4'd12 )begin
47
s <= IDLE; if( C3 <4'd6 )IsDone <= 1'b1;
48
end
49
end
50
else begin
51
C2 <= 4'd0; C3 <= 4'd0;
52
if( !IsSta )begin
53
i <= 4'd0; if( C3 > 4'd7) IsSta <= 1'b1; else begin IsSta <= 1'b0; s<=
IDLE; end
54
end
55
else if( i< 4'd8 )begin
56
if( C3 > 4'd7 ) Dout[i] <= 1'b0; else Dout[i] <= 1'b1; i <= i +
1'b1;
57
end
58
end
59
end
60
61
endcase
41
62 end
63 endmodule
IDLE SAMP
IDLE RXD SAMP

16
7
IsSta TRUE , IsSta TURE
8 bit 8bit
12 6
IsDone True
38400 16 50MHZ
50000000/38400/16-1=80
UartLoop ISE chipscope
42
Uart Block Ram 4
Block RAM Uart FPGA

FPGA
FPGA FPGA Block Ram ,
PC
Memory Types
The Block Memory Generator core uses embedded block RAM to generate five types of memories:
Single-port RAM
Simple Dual-port RAM
True Dual-port RAM
Single-port ROM
Dual-port ROM
RAM
Figure 1
43
Figure 2: Single-port RAM

RAM RAM Figure 2 .
Figure 3: Simple Dual-port RAM

RAM 2 A B, 3 A B
Figure 4: True Dual-port RAM

RAM A,B
Single Port RAM.
44
8bits, 256bytes
8bits,
Figure 5
45
Figure 6: Write First Mode Example

6
Figure 7: Read First Mode Example

7
Figure 8: No Change Mode Example

WEA WEA
8bits 256bytes , 5
46
Figure 10
Figure 11
11:: Spartan3 Block Memory: Register Port [A|B] Outputs of Memory Primitives and Memory
Core Options Enabled
Bock Ram
Block Ram IP 11
10.
47
Figure 12
0
.
Figure 13
13.
48
Module main
1 module main(Clk,Rst,Rxd,Txd);
2 input Clk;
3 input Rst;
4 input Rxd;
5 output Txd;
6
7 wire IsRxdDone,IsTxdDone;
8 wire Rsta;
9 reg IsSta , Wea ;
10
11 wire [7 : 0]Dout;
12 reg [7 : 0]Din;
13 wire [7 : 0]Douta;
14 reg [7 : 0]Addra;
15 reg [7 : 0]Dina;
16
18
if( !Rst )begin
19
Wea <= 1'b0; Addra <= 8'd255; Dina <= 8'd0; Din <= 8'd0;
20
end else begin
21
Wea<=0;IsSta<=0;
22
if( IsRxdDone )begin
23
Addra <= Addra + 1'b1;
24
Dina <= Dout;
25
Wea
<= 1'b1;
26
Din
<= Douta;
27
if( IsTxdDone ) IsSta <= 1'b1;
28
end
29
end
30
31
32
UartRxd
U1
(.Clk(Clk),.Dout(Dout),.IsDone(IsRxdDone),.Rxd(Rxd));//recieve
33 UartTxd
U2 (.Clk(Clk),.IsSta(IsSta),.IsDone(IsTxdDone),.Din(Din),.Txd(Txd));
//send
34
35 assign Rsta = !Rst;
36 BRAM U3(
37
.clka(Clk),
38
.rsta(Rsta),
39
.wea(Wea), // Bus [0 : 0]
40
.addra(Addra), // Bus [7 : 0]
41
.dina(Dina), // Bus [7 : 0]
42
.douta(Douta)); // Bus [7 : 0]
43
44 endmodule
49
Block Ram Block Ram

Block RAM
Uart
Block RAM iP
UartLoop Uart
50
PS2 Uart 4
PS2
Figure 1: PS2Uart Module

Clk
Input
System Clock
Rst
Input
System Rst
Txd
PSClk
Output
Input
Uart serial out

PS2 clock
PSData
Input
PS2 Serial Data
Figure 2: Uart Timing
Uart PS2 PS2
51
Figure 2 PSClk 8
PSClk
Uart
Uart
PS2
PC PS/2
(make code)(break code),
;,
W 10 8'h1dW
8'hF0 8'h1d
()W
X8'h1d
8'h22
8'h22........
X8'hf0 8'h22
W
W8'hf0 8'h1d
W
26
IsDown TRUE , Uart

PC
52
Figure 2 keyboard code map
53
Uart
Module main
1 module main(Clk,Rst,PSClk,PSData,Txd);
2
3 input Clk;
4 input Rst;
5 input PSClk;
6 input PSData;
7 output Txd;
8
9 wire [7:0]RdData;
10 wire IsDown;
11
12
PSScan
u1
(.Clk(Clk),.Rst(Rst),.PSClk(PSClk),.PSData(PSData),.RdData(RdData),.IsDown(IsDown))
;
13 UartTxd u2 (.Clk(Clk),.IsSta(IsDown),.Din(RdData),.Txd(Txd));
14
15 endmodule
Module PSScan
1 module PSScan(Clk,Rst,PSClk,PSData,RdData,IsDown);
2
3 input Clk;
4 input Rst;
5 input PSClk;
6 input PSData;
7 output[7 : 0] RdData;
8 output IsDown;
9
10 //-----------------------------------------11
12 reg IsDown; // Key is down
13 reg PSClk0,PSClk1;
14 reg[7:0] RdDataR1;
15 reg[7:0] RdDataR2;
16 reg[7:0] PSASCII;
17 reg[3:0] C1;
18
19 wire PSCLKNp;
20
21 always @ (posedge Clk or negedge Rst)
22
if(!Rst) begin
23
PSClk0 <= 1'b0; PSClk1 <= 1'b0;
24
end
54
25
else begin
26
PSClk0 <= PSClk;
27
PSClk1 <= PSClk0;
28
end
29
30 assign PSCLKNp = ~PSClk0 & PSClk1; // negedge of PSClk
31
32 //-----------------------------------------33
34 always @ (posedge Clk or negedge Rst) begin
35
if(!Rst) begin
36
C1 <= 4'd0;
37
RdDataR1 <= 8'd0;
38
end
39
else if(PSCLKNp) begin
40
case (C1)
41
4'd0:if( !PSData )C1 <= C1 + 1'b1; // if PSData is low detected start
42
4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8: //sample data
43
begin
44
C1 <= C1 + 1'b1;
45
RdDataR1[C1 -1] <= PSData; //bit0
46
end
47
4'd9: //parity
48
C1 <= C1 + 1'b1;
49
4'd10: // stop
50
C1 <= 4'd0;
51
default: ;
52
endcase
53
end
54 end
55
56
57 always @ (posedge Clk or negedge Rst)
58
if(!Rst) begin
59
IsDown <= 1'b0;
60
RdDataR2 <= 8'd0;
61
end
62
else if(C1==4'd10&&PSCLKNp) begin
63
if(RdDataR1 == 8'hf0) IsDown <= 1'b1; // 8'hf0 key from down to up
64
else begin // key down
65
IsDown <= 1'b0;
66
RdDataR2 <= RdDataR1;
67
end
68
end
69
70 always @ (posedge Clk) begin
71
case (RdDataR2)
72
8'h15: PSASCII <= 8'h51;
//Q
55
73
8'h1d: PSASCII <= 8'h57;
74
8'h24: PSASCII <= 8'h45;
75
76
8'h2c: PSASCII <= 8'h54;
77
8'h35: PSASCII <= 8'h59;
78
79
8'h43: PSASCII <= 8'h49;
80
8'h44: PSASCII <= 8'h4f;
81
82
83
8'h1b: PSASCII <= 8'h53;
84
8'h23: PSASCII <= 8'h44;
85
8'h2b: PSASCII <= 8'h46;
86
8'h34: PSASCII <= 8'h47;
87
8'h33: PSASCII <= 8'h48;
88
8'h3b: PSASCII <= 8'h4a;
89
8'h42: PSASCII <= 8'h4b;
90
8'h4b: PSASCII <= 8'h4c;
91
8'h1a: PSASCII <= 8'h5a;
92
8'h22: PSASCII <= 8'h58;
93
8'h21: PSASCII <= 8'h43;
94
8'h2a: PSASCII <= 8'h56;
95
8'h32: PSASCII <= 8'h42;
96
8'h31: PSASCII <= 8'h4e;
97
8'h3a: PSASCII <= 8'h4d;
98
default: ;
99
endcase
100 end
101
102 assign RdData = PSASCII;
103
104 endmodule
//W
//E
//R
//T
//Y
//U
//I
//O
//P
//A
//S
//D
//F
//G
//H
//J
//K
//L
//Z
//X
//C
//V
//B
//N
//M
56
VGA 3
VGA
Figure 1: VGA Module

VGA Module Function Description
Table 1:
1:VGA
Clk
Input
System Clock
RED
BLUE
Output
Output
Red
BLUE
GREEN
Output
GREEN
HS
VS
Output
Output
hsync
vsync
SW
Input
Button input
57
Figure 2: hsync signal
Figure 3: vsync signal

Table 2:VGA Timing table
800
X
600 a
X72Hz
hsync signal
120
2.4us
1202.4us
2.4us
800 X 600 X72 o
Hz
vsync signal
6(0.12us)
e(total point)
62(1.2us)
p
800(16us)
q
58(1.2us)
r
1040(20.5us)
s(total point)
11(0.24us)
600(12us)
39(0.78us)
666(13.3us)
VGA
1 25
50MHZ 1048x666=692640;
Fre=50000000/692640=72HZ , 1 25
58
else HS <= 1; if(638 <= VS_CNT&&VS_CNT <= 644)

VS <= 0; else VS <= 1;
Figure44 L29-L34, 0-266267-534535-799

Figure
L36-41 0-199200-399400-599.L44-L54,
00 Figure 5
01 Figure 6 1001
Figure 4
59
Figure 5
Figure 6
module VGA_DISPLAY
1 module VGA_DISPLAY(Clk,SW,RED,GREEN,BLUE,HS,VS);
2 input Clk;
3 input [1:0] SW;
4 output RED;
5 output GREEN;
6 output BLUE;
7 output HS,VS;
8
9 reg HS,VS;
10 reg [11:0] HS_CNT; // HS counter
60
11 reg [9 :0] VS_CNT; // VS counter

12 reg RED,GREEN;
13 reg BLUE;
14 reg RED_H,GREEN_H;
15 reg BLUE_H;
16 reg RED_V,GREEN_V;
17 reg BLUE_V;
18
19 always @(posedge Clk) begin //HS VS singal
20
if(857 <= HS_CNT&&HS_CNT <= 977) HS <= 0; else HS <= 1;
21
if(HS_CNT == 1039) begin
22
HS_CNT <= 0;
23
if(VS_CNT == 665) VS_CNT <= 0; else VS_CNT <= VS_CNT + 1;
24
end
25
else HS_CNT <= HS_CNT + 1;
26
if(638 <= VS_CNT&&VS_CNT <= 644) VS <= 0; else VS <= 1;
27 end
28
29 always @(posedge Clk) begin // H show range
30
if((
0 <= HS_CNT&&HS_CNT <= 266 )&&( 0 <=
VS_CNT&&VS_CNT <= 599 )) {RED_H,GREEN_H,BLUE_H} <=3'b001;
31
else if(( 267 <= HS_CNT&&HS_CNT <= 534 )&&( 0 <= VS_CNT&&VS_CNT
<= 599 )) {RED_H,GREEN_H,BLUE_H} <=3'b100;
32
<= 599 )) {RED_H,GREEN_H,BLUE_H} <=3'b010;
33
else {RED_H,GREEN_H,BLUE_H} <=3'b000;
34 end
35
36 always @(posedge Clk) begin // v show range
37
if(( 0 <= HS_CNT&&HS_CNT <= 799 )&&(
0 <=
VS_CNT&&VS_CNT <= 199 )) {RED_V,GREEN_V,BLUE_V} <=3'b001;
38
<= 399 )) {RED_V,GREEN_V,BLUE_V} <=3'b100;
39
<= 599 )) {RED_V,GREEN_V,BLUE_V} <=3'b010;
40
else {RED_V,GREEN_V,BLUE_V} <=3'b000;
41 end
42
43
44
always @(SW or RED_H or GREEN_H or BLUE_H or RED_V or GREEN_V or
BLUE_V) // vag output
45
begin
46
case(SW) //switch state
47
2'b00: begin {RED,GREEN,BLUE} = {RED_H,GREEN_H,BLUE_H} ; end
48
2'b01: begin {RED,GREEN,BLUE} = {RED_V,GREEN_V,BLUE_V} ; end
49
2'b10:
begin
{RED,GREEN,BLUE}
=
{RED_H,GREEN_H,BLUE_H}+{RED_V,GREEN_V,BLUE_V} ; end
50
2'b11:
begin
{RED,GREEN,BLUE}
=
61
{RED_H,GREEN_H,BLUE_H}-{RED_V,GREEN_V,BLUE_V} ; end
51
endcase
52
end
53
54 endmodule
62

SHIFT8 1
8bits
Figure 1: SHIFT8 Module

Clk
Input System Clock
Rst
Input System Reset
SlClk
Input Shift Clock : Data shift form low to high at each raising edge
IsLoad
Input Load data to shift register when high
DataIn
input When IsLoad high data will be loaded into shift register
SftIn
input Bit data shifted into shift register at each raising edge of SlClk
SftEn
input Enable shif
shiftter
SftOut
outp Bit data shifted out from shift register at each raising edge of SlClk
ut
DataOut outp shift register Output
ut
63
Figure 2 :SHIFT8 Module Simulation
IsLoad TRUE DataIn DataInt

IsLoad FALSE SftEn TRUE , SlClk TRUE
Module
1 module SHIFT8
2 (
3
input Clk,
4
input SlClk,
5
input Rst,
6
input IsLoad,
7
input [7:0] DataIn,
8
input SftIn,
9
input SftEn,
10
output SftOut,
11 output [7:0]DataOut
12
);
13
14
reg [7:0] DataInt;
15
assign DataOut=DataInt;
16
assign SftOut=DataInt[7];
17
18
always @( posedge Clk )begin
19
if( !Rst )DataInt <= 0;
20
else if(IsLoad) DataInt <= DataIn;
21
else if(SlClk) begin if( SftEn ) DataInt <= { DataInt [6:0], SftIn }; end
22
end
23
24 endmodule
64
TestBench
TestBench::
1 module SHIFT8_tb;
2
3 // Inputs
4 reg Clk;
5 reg SlClk;
6 reg Rst;
7 reg IsLoad;
8 reg [7:0] DataIn;
9 reg SftIn;
10
reg SftEn;
11
12
// Outputs
13
wire SftOut;
14
wire [7:0] DataOut;
15
// Instantiate the Unit Under Test (UUT)
16
SHIFT8 uut (
17
.Clk(Clk),
18
.SlClk(SlClk),
19
.Rst(Rst),
20
.IsLoad(IsLoad),
21
.DataIn(DataIn),
22
.SftIn(SftIn),
23
.SftEn(SftEn),
24
.SftOut(SftOut),
25
.DataOut(DataOut)
26
);
27
28
initial begin
29
30
Clk = 0;
31
SlClk = 0;
32
Rst = 0;
33
IsLoad = 0;
34
DataIn = 0;
35
SftIn = 0;
36
SftEn = 0;
37
# 10 Clk = !Clk;
38
# 10 Clk = !Clk;
39
# 10 Clk = !Clk;
40
Rst = 1;
41
42
43
end
44
45
46
reg [3 : 0] C1;
47
always @( posedge Clk ) SlClk <= !SlClk;
65
48
49
always @( posedge Clk ) begin
50
if( !Rst ) begin
51
IsLoad <= 1'b1; DataIn <=8'hAA; SftIn <=1'b0; C1 <= 8'd0;
52
end
53
else if( SlClk ) begin
54
if(C1 < 4'd8 ) begin IsLoad <= 1'b0; SftEn <= 1'b1; SftIn <= !SftIn; C1
<= C1 + 1'b1; end
55
else begin SftEn <= 1'b0; C1 <= 4'd0; DataIn <= 8'h00; IsLoad <= 1'b1;
end
56
end
57
end
58
59 endmodule
66
ExpandIO 3
2 74HC595 16 IO 4
LED
Figure 1: main Module

Clk
Input
System Clock
Rst
Input
System Reset
LchClk
SDout
Output
Output
74hc595 Lach Clock

74hc595 Serial input
SftClk
Output
74hc595 Shift Clock
SRst
Output
74hc595 Reset
Table 2:ExIO16 Module Function Description

Clk
Input
System Clock
Rst
Input
System Reset
LchClk
SDout
Output
Output
74hc595 Lach Clock

SftClk
Output
74hc595 Shift Clock
SRst
Output
74hc595 Reset
67
ExIO
74hc595 Output 16bits
Table 3:spi Module Function Description

Clk
Input
System Clock
Rst
Input
System Reset
Mosi
Miso
Output
Input
Master Out Serial In

Master In Serial Out
Sck
Output
Spi Clock
IsSta
IsDone
Output
Input
1: Start Spi transfer

1 byte have been transfered
Direst
WrData
Output
Output
Direction Set 1:Output 0:Input

Write Data Register 8bits
RdData
Input
Read Data Register 8bits
Spi Communication
Figure 2: Spi Timing
MOSI: SCK SCK
MISO: SCK SCK
NSS :
68
Figure 3: Spi module
Table 4: Shift Module Function Description

Clk
Input
System Clock
Rst
Input
System Reset
SlClk
Input
Shift Clock : Data shift form low to high al each raising edge
IsLoad
Input
Load data to shift register when high
DataIn
input
When IsLoad high data while be loaded into shift register 8bits
SftIn
input
Bit data shifted into shift register at each raising edge of SlClk
SftEn
input
Enable shifter
SftOut
output
Bit data shifted out from shift register at each raising edge of SlClk
DataOut
output
shift register Output 8bits
69
Figure 4: Spi State machine
Spi 0 IsSta TRUE
1 1 SPI 8bit SHIFT8

IsDone
SPI 0 Sck_en TRUE 2
1 1. 1 Sck_en
TRUE. TRUE, 0.
SHIFT8
70
Figure 5: 74HC595 LOGIC DIAGRAM
Figure 6: 74HC595 PIN
71
Table 4: 74HC595 FUNCTION TABLE

SftCl LchCl
SRs
FUNCTION
A
OE
k
k
t
X
X
X
L
L
X
X
L
L
X
X
X
H
L
X
L
H A
X
X
L
H
X
L
H
SPI 16bit
Module SPI
1 module spi(Clk,Rst,Sck,Mosi,Miso,RdData,WrData,DirSet,IsSta,IsDone);
2
3 input Clk;
4 input Rst;
5 output Sck;
6 output Mosi;
7 input Miso;
8 output [7:0] RdData;
9 input [7:0] WrData;
10 input DirSet;
11 input IsSta;
12 output IsDone;
13
14 reg [1:0] SckState;
15 reg s;
16 reg SckEn;
17
18 reg IsDone;
19
20 reg [6:0]SckC;
21 reg [3:0]BitC;
22 reg [7:0]RdData;
23
24
25 wire [7:0]DataOut;
26 wire SftOut;
27
28 reg Sck,SckD1;
29 wire SckUp,SckNp;
30
31 assign SckUp=Sck&&(!SckD1);
72
32 assign SckNp=!Sck&&(SckD1);
33 always @(posedge Clk) SckD1 <= Sck;
34
35 parameter BIT8 = 4'd8;
36
37 always @(posedge Clk) //count shifted bits
38 if(SckEn && SckUp) BitC <= BitC + 1'b1; else if(BitC == BIT8) BitC<=4'd0;
39
40 assign Mosi= DirSet ? SftOut : 1'b1;
41
42 always @(posedge Clk) // main process
43 if(!Rst)begin
44
s<=1'b0; IsDone <= 1'b0; SckEn <= 1'b0;
45 end
46 else begin
47
case(s)
48
0: //IDLE state
49
begin IsDone <= 1'b0; IsDone <= 1'b0; SckEn <= 1'b0; if( IsSta )s<= 1'b1; end
50
1://shift state
51
begin
52
SckEn<=1'b1; if(BitC == BIT8)begin RdData <= DataOut; SckEn <= 1'b0;
IsDone <= 1'b1; s <= 1'b0;end
53
end
54
endcase
55 end
56
57 // spi clock generator
58
59 parameter TSET = 7'd1;
60
61 always @(posedge Clk) // Shift Clock Process
62 if(!Rst)begin SckC <= 7'd0; Sck <= 1'b0; SckState <= 2'd0;end
63 else begin
64
case( SckState )
65
0:
66
begin SckC <= 7'd0; Sck <= 1'd0; if( SckEn ) SckState <= 2; end
67
1:
68
begin
69
Sck <= 1'b1; if( SckC >= TSET ) begin SckState <= 2; SckC <= 7'd0; end else
SckC <= SckC + 1'b1;
70
end
71
2:
72
begin
73
Sck <= 1'b0;
74
if( SckC >= TSET ) begin SckC<=7'd0; if( SckEn ) SckState <= 1; else
SckState <= 0; end
75
else SckC <= SckC + 1'b1;
76
end
73
77
endcase
78 end
79
80 wire SlClk;
81 wire IsSpiLd;
82 assign SlClk = DirSet ? SckNp : SckUp;
83 assign IsSpiLd = IsSta;
84 SHIFT8 SPI_DATA
85
(.Clk(Clk),
86
.Rst(Rst),
87
.SlClk(SlClk),
88
.IsLoad(IsSpiLd),
89
.DataIn(WrData),
90
.SftIn(Miso),
91
.SftEn(SckEn),
92
.SftOut(SftOut),
93
.DataOut(DataOut)
94
);
95
96
97 endmodule
spi module 16 IO
0 IsSta FALSE, 8bits
8bits . 0.IsDone TRUE
Figure 5: Spi Transmit machine
74
Module ExIOX16
1 module ExIOX16(Clk,Rst,SftClk,LchClk,SDout,SRst,ExIO);
2 input Clk;
3 input Rst;
4 output SftClk;
5 output LchClk;
6 output SDout;
7 output SRst;
8 input [15:0]ExIO;
9
10
11 reg LchClk;
12 reg SRst;
13
14 reg DirSet;
15 reg IsSta;
16 reg [7:0]WrData;
17 reg [2:0]s;
18
19 wire IsDone;
20
21 always @(posedge Clk)begin
22
if(!Rst)begin
23
DirSet <= 1'b0; IsSta <= 1'b0; s<= 1'b0; LchClk <= 1'b0; SRst <= 1'b0;
24
end
25
else begin
26
case(s)
27
0:
28
begin DirSet <= 1; IsSta <= 0; s <= 3'd1; SRst <= 1; end
29
1,2: // nop 2 clock
30
s <= s + 1'b1;
31
3: // Write MSB BYTE Of HC595
32
begin WrData <= ExIO[15:8]; IsSta <= 1; SRst <=1; s <= 4; end
33
4: // Wait done
34
begin IsSta <=0; if( IsDone ) begin s <= 5; LchClk <= 0; end end
35
5 : // Write LSB BYTE Of HC595
36
begin WrData <= ExIO[7 :0] ;IsSta <= 1;s <= 6; end
37
6: // Wait done
38
39
endcase
40
end
41 end
42
43 spi hc595x2(
44
.Clk(Clk),
45
.Rst(Rst),
46
.Sck(SftClk),
75
47
48
49
50
51
52
53
54
55
56 endmodule
.Mosi(SDout),
.Miso(Miso),
.RdData(RdData),
.WrData(WrData),
.DirSet(DirSet),
.IsSta(IsSta),
.IsDone(IsDone)
);
IO
Module main
1 module main(Clk,Rst,SftClk,LchClk,SDout,SRst);
2 input
Clk;
3 output SftClk;
4 output LchClk;
5 output SDout;
6 output SRst;
7 input
Rst;
8
9 reg [15:0] ExIO;
10 reg [22:0] C1;
11 always @(posedge Clk)
12
if(!Rst) begin C1 <=23'd0; end
13
else begin
14
if( C1 < 23'd5000000) C1 <= C1 + 1'b1;
15
else begin
16
C1 <= 23'd0; ExIO[15] <= !ExIO[15];
17
end
18
end
19
20 ExIOX16 u0(
21
.Clk(Clk),
22
.Rst(Rst),
23
.SftClk(SftClk),
24
.LchClk(LchClk),
25
.SRst(SRst),
26
.SDout(SDout),
27
.ExIO(ExIO)
28
);
29
30 endmodule
76
SpiDisplay 3
16 IO,
IO, 16 IO
12 4 7 0112233
Figure 1: main Module

Clk
Input
System Clock
Rst
Input
System Reset
LchClk
SDout
Output
Output
74hc595 Latch Clock

SftClk
Output
74hc595 Shift Clock
SRst
Output
74hc595 Reset
Table 2:Dpy4 Module Function Description

Clk
Input
System Clock
Rst
Input
System Reset
LchClk
SDout
Output
Output
74hc595 Lach Clock

SftClk
Output
74hc595 Shift Clock
SRst
Output
74hc595 Reset
77
Dpy0
Dpy1
input
input
74hc595 Output Led0 4bis

74hc595 Output Led1 4bits
Dpy2
Dpy3
input
input


Clk
Input
System Clock
Rst
Input
System Reset
Mosi
Miso
Output
Input

Sck
Output
Spi Clock
IsSta
IsDone
input
output

1 byte have been transferred
Direst
WrData
input
input

Write Data Register 8bits
RdData
output
Read Data Register 8bits
ExpandIO
Figure
Figure22: 7-Segment LED Display (Dynamic Lighting)
25
1S 25
78
Table 4:Code map to Value
Value
0
1
2
3
4
5
6
7
Code
8hc0
8hf9
8ha4
8hb0
8h99
8h92
8h82
8hf8
Value
8
9
A
B
C
D
E
F
Code
8h80
8h90
8h88
8h83
8hc6
8ha1
8h96
8h8e
L69-L100 SPI
ExpandIO
module Dpy4
1 module Dpy4(Clk,Rst,SftClk,LchClk,SDout,SRst,Dpy0,Dpy1,Dpy2,Dpy3);
2 input Clk;
3 input Rst;
4 output SftClk;
5 output LchClk;
6 output SDout;
7 output SRst;
8 input [3:0]Dpy0;
9 input [3:0]Dpy1;
10 input [3:0]Dpy2;
11 input [3:0]Dpy3;
12
13 parameter
14
zero = 8'b1100_0000,
15
one = 8'b1111_1001,
16
two = 8'b1010_0100,
17
three= 8'b1011_0000,
18
four = 8'b1001_1001,
19
five = 8'b1001_0010,
20
six = 8'b1000_0010,
21
seven= 8'b1111_1000,
22
eight= 8'b1000_0000,
23
nine = 8'b1001_0000;
24
25 parameter
26
IDLE =0,
27
BYT0 =1,
28
BYT0W=2,
29
BYT1 =3,
79
30
BYT1W=4;
31
32 reg LchClk;
33 reg SRst;
34
35 reg rdy;
36 reg DirSet;
37 reg IsSta;
38 reg [7:0]WrData;
39 reg [2:0]s;
40 reg [2:0]Dpy_n;
41 reg [3:0]dp;
42 reg [3:0]data;
43 reg [7:0]dat;
44
45 wire IsDone;
46
48
if(!Rst)begin
49
DirSet <= 1'b0; IsSta <= 1'b0; s<= 1'b0; LchClk <= 1'b0; SRst <= 1'b0;
50
end
51
else begin
52
case(s)
53
0:
54
begin DirSet <= 1; IsSta <= 0; s <= 3'd1; rdy <=0; SRst <= 1; end
55
1,2: // nop 2 clock
56
s <= s + 1'b1;
57
3: // Write MSB BYTE Of HC595
58
begin WrData <= dp; IsSta <= 1; SRst <=1; s <= 4; end
59
4: // Wait done
60
61
5 : // Write LSB BYTE Of HC595
62
begin WrData <= dat ;IsSta <= 1;s <= 6; end
63
6: // Wait done
64
begin IsSta <=0; if( IsDone ) begin s <= 0; LchClk <= 1;rdy <= 1;end end
65
endcase
66
end
67 end
68
70
if( rdy ) begin Dpy_n <= Dpy_n + 1'b1;
71
if( Dpy_n> 3 ) Dpy_n <= 1'b0; end
72 end
73
75
case ( Dpy_n )
76
0:
77
begin data <= Dpy0;dp <= 4'b1000;end
80
78
1:
79
80
2:
81
82
3:
83
84
endcase
85 end
86
87 always @(posedge Clk )begin
88
case( data )
89
0: dat <= zero;
90
1: dat <= one;
91
2: dat <= two;
92
3: dat <= three;
93
4: dat <= four;
94
5: dat <= five;
95
6: dat <= six;
96
7: dat <= seven;
97
8: dat <= eight;
98
9: dat <= nine;
99
endcase
100 end
101
102 spi hc595x2(
103
.Clk(Clk),
104
.Rst(Rst),
105
.Sck(SftClk),
106
.Mosi(SDout),
107
.Miso(Miso),
108
.RdData(RdData),
109
.WrData(WrData),
110
.DirSet(DirSet),
111
.IsSta(IsSta),
112
.IsDone(IsDone)
113
);
114
115 endmodule
81
0123
Module main
2 input
Clk;
3 output SftClk;
4 output LchClk;
5 output SDout;
6 output SRst;
7 input
Rst;
8
9 wire [3:0] Led1 = 4'd0;
10 wire [3:0] Led2 = 4'd1;
11 wire [3:0] Led3 = 4'd2;
12 wire [3:0] Led4 = 4'd3;
13
14 Dpy4 u0(
15
.Clk(Clk),
16
.Rst(Rst),
17
.SftClk(SftClk),
18
.LchClk(LchClk),
19
.SRst(SRst),
20
.SDout(SDout),
21
.Dpy0(Led1),
22
.Dpy1(Led2),
23
.Dpy2(Led3),
24
.Dpy3(Led4)
25
);
26
27 endmodule
82
SpiCounter 4
SPI verilog
74hc595 16 IO 12 4 7
9999
09999
9999
Figure 1: ExpandIO Module

Clk
Input
System Clock
Rst
Input
System Reset
LchClk
SDout
Output
Output
74hc595 Latch Clock

SftClk
Output
74hc595 Shift Clock
SRst
Output
74hc595 Reset
Table 2:Dpy4 Module Function Description

Clk
Input
System Clock
Rst
Input
System Reset
83
LchClk
SDout
Output
Output
74hc595 Lach Clock

SftClk
Output
74hc595 Shift Clock
SRst
Dpy0
Output
74hc595 Reset
74hc595 Output Led 0
Dpy1
Dpy2

Dpy3
74hc595 Output Led3

Clk
Input
System Clock
Rst
Input
System Reset
Mosi
Miso
Output
Input

Sck
Output
Spi Clock
IsSta
IsDone
Output
Input

1 byte have been transferred
Direst
WrData
Output
Output

Write Data Register
RdData
Input
Read Data Register
SpiDisplay
Module main
2 input
Clk;
3 output SftClk;
4 output LchClk;
5 output SDout;
6 output SRst;
7 input
Rst;
8
9 reg [3:0] Led4;
10 reg [3:0] Led3;
11 reg [3:0] Led2;
12 reg [3:0] Led1;
13
14 reg [6 :0] C2;
15 reg [9 :0] C3;
84
16 reg [13:0] C4;

18
19 reg [22:0] C5;
20 reg [3:0] i ,j , k;
22
24
if(!Rst) begin i <= 4'd0; j <= 4'd0; k <= 4'd0; end
25
else begin
26
if( C4 > 14'd999 )begin
27
if( 1000 *(k + 1 ) <= C4 ) k <= k + 1'b1; else begin Led4 <= k; C3 <= ( C41000*k ); k <= 4'd0; end
28
end else begin C3 <= C4; Led4 <= 4'd0; end
29
30
if( C3 > 10'd99 )begin
31
if( 100 *(i + 1 ) <= C3 ) i <= i + 1'b1; else begin Led3 <= i; C2 <= ( C3
-100*i ); i <= 4'd0; end
32
33
34
if( C2 > 7'd9
)begin
35
if(
10 *( j + 1) <= C2 ) j <= j + 1'b1 ;else begin Led2 <= j; Led1<= (C2 10*j ); j <= 4'd0;end //
36
end else begin Led1 <= C2; Led2 <= 4'd0; end
37
end
38 end
39
40 always @(posedge Clk)
41
if(!Rst) begin
42
C5 <=23'd0; C4 <= 10'd0;
43
end
44
else begin
45
if( C5 < 23'd5000000) C5 <= C5 + 1'b1;
46
else begin
47
C5 <= 23'd0; if( C4 < 14'd9999 ) C4 <= C4 + 1'b1; else C4 <= 10'd0;
48
end
49
end
50
51
52 Dpy4 u0(
53
.Clk(Clk),
54
.Rst(Rst),
55
.SftClk(SftClk),
56
.LchClk(LchClk),
57
.SRst(SRst),
58
.SDout(SDout),
59
.Dpy0(Led1),
60
.Dpy1(Led2),
61
.Dpy2(Led3),
62
.Dpy3(Led4)
63
);
64
65 endmodule
85
C5
C4 L23 L28 4
C4 1234 L16-L28 Led[3]

1L30-L32 Led[2] 2L34-L36 Led[1] 3
L37 Led[2] 4
86
ADC AD7478 4
AD7478 4 7
Figure 1: ADCAD7478 Module

T24LC02 Module Function Description
Table 1:
1:T24LC02
Clk
Input
System Clock
Rst
Input
System Reset
LchClk
SDout
Output
Output
74hc595 Latch Clock

SftClk
Output
74hc595 Shift Clock
SRst
CS
Output
Output
74hc595 Reset
AD7478 Chip Select
SClk
AI
Output
Input
Serial Clock.
Serial Data output to FPGA
87
AD7478 FEATURES
Fast Throughput Rate: 1 MSPS
fi
Specifi
fied for VDD of 2.35 V to 5.25 V
Low Power:
3.6 mW Typ at 1 MSPS with 3 V Supplies
15 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
70 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface
SPI/QSPI/MICROWIRE/DSP Compatible
Standby Mode: 1 A Max
6-Lead SOT-23 Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Figure 2: AD7478 Pin Description
88
Figure 3: AD7478 Interface timing
Figure 4: AD7478 module
module AD7478
1 module AD7478(Clk,Rst,IsSta,IsBusy,Sync,SClk,AI,AIReg
2
);
3 input Clk;
4 input Rst;
5 input IsSta;
6 output IsBusy;
7 input AI;
8 output reg Sync;
9 output reg SClk;
10 output reg [ 11:0 ]AIReg;
11
12 reg IsBusy;
89
13 reg [11:0]AIReg1;
14 reg [3 :0]C=0;
15 reg [3 :0]s;
16
17 //assign AIReg = AIReg1;
18
19 reg SClk1;
20 wire ClkUp;
21
22 assign ClkNp = (!SClk)&&SClk1;
23 assign ClkUp = (SClk )&&(!SClk1);
24
25 reg [0:0]SCLKDiv;
26 always @( posedge Clk ) if(s!=0) SClk<=!SClk; else SClk <=1'b1;
27
29
//IsSta1 <= IsSta;
30
SClk1 <= SClk;
31 end
32
34
if( !Rst )begin
35
s <= 4'd0; IsBusy <= 1'b0; C <= 4'd0; AIReg1 <= 12'd0; Sync <= 1'b1;
36
end else begin
37
case (s)
38
0:
39
begin
40
Sync <= 1'b1; IsBusy <= 1'b0; C <= 4'd0;
41
if( IsSta )begin IsBusy <= 1'b1; s <= 4'd1;Sync <= 1'b0; end
42
end
43
1,2,3,4:
44
if( ClkUp ) begin s <= s + 1'd1; end
45
5:
46
if( C < 4'd12 )begin
47
if( ClkUp ) begin Sync <= 1'b0;AIReg1[11:0] <= {AIReg1[10:0],AI}; C <=
C + 1'b1; end
48
end
49
else if( ClkUp ) begin C <= 4'd0;s <= 4'd6; Sync <= 1'b1;AIReg<=AIReg1;
end
50
6:
51
if( ClkUp ) s <= 4'd0;
52
endcase
53
end
54 end
55
90
56 endmodule
module main
1 module main(Clk,Rst,SftClk,LchClk,SDout,SRst,CS,SClk,AI);
2 input
Clk;
3 input
Rst;
4 output SftClk;
5 output LchClk;
6 output SDout;
7 output SRst;
8 output CS;
9 output SClk;
10 input
AI;
11
12
13 reg [3:0] Led4;
14 reg [3:0] Led3;
15 reg [3:0] Led2;
16 reg [3:0] Led1;
17
18 reg [6 :0] C2;
19 reg [9 :0] C3;
20 reg [13:0] C4;
21
22
23 reg [22:0] C5;
24 reg [3:0] i ,j , k;
25 wire [11:0] AIReg;
26 reg IsSta;
27 wire IsBusy;
28
30
IsSta <= 1'b1;
31
if( !IsBusy ) C4 <= AIReg[11:7];
32
33
if(!Rst) begin i <= 4'd0; j <= 4'd0; k <= 4'd0; end
34
else begin
35
if( C4 > 14'd999 )begin
36
if( 1000 *(k + 1 ) <= C4 ) k <= k + 1'b1; else begin Led4 <= k; C3 <= ( C41000*k ); k <= 4'd0; end
37
38
39
if( C3 > 10'd99 )begin
40
if( 100 *(i + 1 ) <= C3 ) i <= i + 1'b1; else begin Led3 <= i; C2 <= ( C3
-100*i ); i <= 4'd0; end
91
41
42
43
if( C2 > 7'd9
)begin
44
if(
10 *( j + 1) <= C2 ) j <= j + 1'b1 ;else begin Led2 <= j; Led1<= (C2 10*j ); j <= 4'd0;end //??????
45
end else begin Led1 <= C2; Led2 <= 4'd0; end
46
end
47 end
48
49
50 AD7478 u1(.Clk(Clk),
51
.Rst(Rst),
52
.IsSta(IsSta),
53
.IsBusy(IsBusy),
54
.Sync(CS),
55
.SClk(SClk),
56
.AI(AI),
57
.AIReg(AIReg)
58
);
59
60 Dpy4 u2(
61
.Clk(Clk),
62
.Rst(Rst),
63
.SftClk(SftClk),
64
.LchClk(LchClk),
65
.SRst(SRst),
66
.SDout(SDout),
67
.Dpy0(Led1),
68
.Dpy1(Led2),
69
.Dpy2(Led3),
70
.Dpy3(Led4)
71
);
72 endmodule
SPI
92
DAC AD5300 4
AD5300
Figure 1: DACAD5300 Module
Figure 2: DACAD5300 Module
Table 1:
main Module Function Description
1:main
Clk
Input
System Clock
Rst
Input
System Reset
Sync
SClk
Output
Output
AD5300 Chip Select

Serial Clock.
AO
Output
Serial Data output from FPGA

93
FEATURES
Single 8-Bit DAC
6-Lead SOT-23 and 8-Lead MSOP Packages
Micropower Operation: 140 A @ 5 V
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
2.7 V to 5.5 V Power Supply
Guaranteed Monotonic by Design
Reference Derived from Power Supply
Power-On Reset to 0 V
3 Power-Down Functions
Low Power Serial Interface with
Schmitt-Triggered Inputs
On-Chip Output Buffer Amplifier,
Rail-to-Rail Operation
SYNC Interrupt Facility
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable
Attenuators
Figure 3: AD5300 Pin Description
94
Figure 3: AD5300 Interface timing
Figure 4: AD5300 Input Register Contents
Figure 5: AD5300 module
95
module AD5300
1 module AD5300(Clk,Rst,IsSta,IsBusy,Sync,SClk,AO,AOReg
2
);
3 input Clk;
4 input Rst;
5 input IsSta;
6 output IsBusy;
7 output reg AO;
8 output reg Sync;
9 output reg SClk;
10 input [ 15:0 ]AOReg;
11
12 reg IsBusy;
13 reg [15:0]AOReg1;
14 reg [4 :0]C=0;
15 reg [1 :0]s;
16
17 reg SClk1;
18 wire ClkNp,ClkUp;
19
20 assign ClkNp = (!SClk)&&SClk1;
21 assign ClkUp = (SClk )&&(!SClk1);
22
23 always @( posedge Clk ) SClk<=!SClk;
24
26
SClk1 <= SClk;
27 end
28
30
if( !Rst )begin
31
s <= 2'D0; IsBusy <= 1'b0; C <= 5'd0; AOReg1 <= 16'd0; Sync <= 1'b1;
32
end else begin
33
case (s)
34
0:
35
begin
36
Sync <= 1'b1; IsBusy <= 1'b0; C <= 5'd0;
37
if( IsSta )begin AOReg1 <= AOReg; IsBusy <= 1'b1; s <= 1'b1; end
38
end
39
1:
40
if( ClkNp ) begin Sync <= 1'b0; s <= 2'd2; end
41
2:
42
if( C < 5'd16 )begin
43
if( ClkUp ) begin Sync <= 1'b0; AO <= AOReg1[15]; AOReg1[15:0] <=
{AOReg1[14:0],1'b0}; C <= C + 1'b1; end
96
44
end
45
else if( ClkNp )begin C <= 5'd0; Sync <= 1'b1; s <= 2'd3; end
46
3:
47
s <= 2'd0;
48
endcase
49
end
50 end
51
52 endmodule
module main
1 module main(Clk,Sync,SClk,AO);
2 input Clk;
3 output Sync;
4 output SClk;
5 output AO;
6
7 reg [8:0]init_time=0;
8 assign Rst=init_time[8];
10
if(!init_time[8])init_time<=init_time+1;
11 else begin init_time<=init_time; end
12 end
13
14 reg [15:0] AOReg=0;
15 reg IsSta;
16 wire IsBusy;
17 reg s = 0;
18
20
AOReg[15:12]<=4'b0000;
21
if((!IsBusy)&&(!IsSta))begin
22
IsSta <= 1;
23
case(s)
24
0: if( AOReg[ 11:4 ] < 8'd255 ) AOReg[11:4] <= AOReg[11:4] + 1'd1; else
s <= 1'b1;
25
1: if( AOReg[ 11:4 ] > 8'd0
) AOReg[11:4] <= AOReg[11:4] - 1'd1; else
s <= 1'b0;
26
endcase
27
end
28
else IsSta <= 1'b0;
29 end
30
31
32 AD5300 u0(
97
33
34
35
36
37
38
39
40
41
);
42 endmodule
.Clk(Clk),
.Rst(Rst),
.IsSta(IsSta),
.IsBusy(IsBusy),
.Sync(Sync),
.SClk(SClk),
.AO(AO),
.AOReg(AOReg)
98
1
I2C24C02 5
24LC02 1BYTE
4 3 1BYTE 4 4
2 1
Figure 1: I2C24C02 Module

T24LC02 Module Function Description
Table 1:
1:T24LC02
Clk
Input
System Clock
Rst
Input
System Reset
LchClk
Output
74hc595 Latch Clock
SDout
SftClk
Output
Output

74hc595 Shift Clock
SRst
Output
74hc595 Reset
99
Scl
Sda
inout
inout
I2C clock
I2C data bus
Sw1
input
button
Figure 2: I2C Module

I2C Module Function Description
Table 2:
2:I2C
Clk
Input
System Clock
Rst
Input
System Reset
Scl
InOut
I2C serial clock
Sda
RdData
InOut
Output
I2C serial data

Read Data
WrData
IsSta
Input
Input
Write Data
1: Start Send data 0: Stop Send data
IsRsta
DirSet
input
input
1:Restart Send data

1:Write 0:Read
IsAck
input
Ack value
100
IsRstaRst
IsDone
Output
Output
Reset Restart flag

Transmit process have been finished
IsBusy
IsABL
Output
Output
Transmit process is busy

Arbitration Lost
IsABLRst
input
Reset IsABL
Figure 3: 24LC02 Module

24LC02 PIN Description
Table 3:
3:24LC02
A0~A2
Input
A0~A2 I Address inputs
SDA
InOut
Serial data inputs/output
SCL
WP
put
In
Input
put
In
Input
Serial clock data input

Write protect
put
In
Input
Negative power supply

Positive power supply
VSS
VCC
Figure 4: I2c Timing
Figure 5: I2c Timing
101
I2C SLC SDA

I2C SLC SDA
I2C ACK : (1) 8 ACK
ACK
(2) 8bit
ACK ACK
Figure 5: 24LC02 Byte write
1
1 header,
2
3
Figure 6: 24LC02 Random read timing
1 header,
2
3 header,
4
24LC02
102
I2C IP CORE
Wait Start
Sw1
is
IsBusy?
YES
NO
IsBusy ?
YES
Write Header
NO
NO
IsDone?
Write Header
YES
IsDone?
NO
Write Address
YES
IsDone?
NO
Write Address
YES
IsDone?
NO
YES
Write Header Restart
IsDone?
Write Data
YES
Read Data
Figure 7: 24LC02 Write Read Process
103
NO

IDLE
IDLE
GenSta IsRst SCL SCL SDA
1 START
START:
SDA 0 SCL HEADER
HEADER
HEADER
8bits STOP
IDLE, 8bits ACK_HEADER
ACK_HEADER
ACK_HEADER
SCL ACK
SDA 0
ACK ACKACK XMIT_DATA
RCV_DATAACK STOP
XMIT_DATA
XMIT_DATA
8bits STO
IDLE, 8bits
ACK_XMIT
WAIT_ACK
WAIT_ACK
SCL ACK
SDA 0 ACK ACKACK
IDLE XMIT_DATA ACK STOP
104
RCV_DATA
RCV_DATA
STOP 8bit
ACK_DATA
ACK_DATA
ACK_DATA
ACK 1
IDLE STOP, RCV_DATA
STOP:
SCL 1 SDA 0SDA 1
IDLE
SCL
MScl_IDLE
MScl_IDLE
SCL 1 MScl_HIGH.
MScl_HIGH
MScl_HIGH
1, MScl_LOW ,
IDLE SCL MScl_IDLE
MScl_IDLE:
1, MScl_HIGH.
SHIFT8 I2CDATA_REG(
.Clk(Clk),
.SlClk(SlClk),
.Rst(Rst),
.IsLoad(IsI2cLd),
.DataIn(WrData),
.SftIn(SdaIn),
.SftEn(DOutEn),
.SftOut(SftOut),
.DataOut(DataOut)
);
105
265 assign
DOutEn =((s1==HEADER)||(s1==XMIT_DATA)||(s1==RCV_DATA))? 1 :
0;
266
assign
IsI2cLd
=((s1==IDLE )||(s1==WAIT_ACK )||(s1==ACK_HEADER)||DetcSta)? 1 : 0;
L265-L266
BITCNT
u2(.Clk(Clk),.Rst(Rst),.SclNp(SclNp),.LdData(CZero),.CEn(BitC1En),.IsLoad(BitC1Ld),
.DataOut(BitC1));
8 bits I2C
IsDone 1 RdData.
ClkCNT u3(.Clk(Clk),.Rst(Rst),.LdData(CZero), .CEn(SclC1En),.DataOut(SclC1));

SCL
ClkCNT u4(.Clk(Clk),.Rst(Rst),.LdData(CZero), .CEn(SdaC1En),.DataOut(SdaC1));

SDA
L129-L139 :
L151-L157:
L159-L166:
L112-L119:
L122-L127:
106
Module I2C
1 module I2C
(Clk,Rst,Scl,Sda,RdData,WrData,IsSta,IsRsta,DirSet,IsAck,IsRstaRst,IsDone,IsBusy,IsAB
L,IsABLRst);
2 input Clk;
3 input Rst;
4 inout Scl;
5 inout Sda;
6 output [7:0]RdData;
7 input [7:0]WrData;
8 input IsSta;
9 input IsRsta;
10 input DirSet;
11 input IsAck;
12 output IsRstaRst;
13 output IsDone;
14 output IsBusy;
15 output IsABL;
16 input IsABLRst;
17
18 parameter SclC1_HIGH = 250;
19 parameter SclC1_LOW = 250;
20
21 parameter START_HOLD = 80;
22 parameter DATA_HOLD = 100;
23
24 parameter
STOP_HOLD_2 = 150;
25 parameter
STOP_HOLD
= 220;
26
27 parameter CLR_REG = 8'b00000000;
28 parameter START_CNT = 4'b0000;
29 parameter CNT_DONE = 4'b0111;
30 parameter ZERO_CNT = 4'b0000;
31
32 parameter BIT_DONE
= 7;
33
34 parameter MScl_IDLE = 0;
35 parameter MScl_HIGH = 1;
36 parameter MScl_LOW = 2;
37
38 parameter IDLE
= 0;
39 parameter START = 1;
40 parameter HEADER
= 2;
41 parameter ACK_HEADER= 3;
42 parameter RCV_DATA = 4;
43 parameter XMIT_DATA = 5;
44 parameter ACK_DATA = 6;
45 parameter WAIT_ACK = 7;
46 parameter STOP
= 8;
47
48
107
49
50 reg [7:0]RdData;
51
52 reg DetcSta;
53 reg DetcStp;
54
55 reg GenSta;
56 reg GenStp;
57
58 reg Busy;
59 reg BusyD1;
60
61 reg IsABL;
62
63 reg IsStaD1;
64 reg IsRstaRst;
65 reg AckErr;
66 reg IsDone;
67
68 wire [3:0]BitC1;
69 wire BitC1En;
70 wire BitC1Ld;
71
72
73 reg MSda;
75 wire SftOut;
76
77 wire [7:0] CZero =8'd0;
78 reg DetcStpD1;
79
80
81 reg [1:0]s2;
82 reg [3:0]s1;
83
84 reg MScl;
85 reg SclC1En;
86 reg RSda;
87 reg SdaC1En;
88
89 wire [7:0]SdaC1;
90 wire [7:0]SclC1;
91 reg SdaIn;
92 reg SclIn;
93 wire SclNp;
94 wire SclUp;
95
96 assign SclUp=( !SclIn )&&( Scl != 1'b0);
97 assign SclNp=( SclIn )&&( Scl == 1'b0);
98
99 assign Scl = ( MScl == 1'b0 ) ? 1'b0 : 1'bz;
108
100 assign Sda

= ( RSda == 1'b0 ) ? 1'b0 : 1'bz;
102 assign IsBusy = Busy;
103
104 /************receive data from shift when ACK_DATA***********/
106
if( !Rst )begin RdData <= 1'b0; IsDone <= 1'b0; end
107
else begin
108
if( BitC1==4'd8 ) begin RdData <= DataOut; IsDone <= 1'b1; end else begin
RdData<=RdData; IsDone <= 1'b0;end
109
end
110 end
111
112 /*******Bus buy Detector*********/
114 if( !Rst )begin Busy <= 1'b0; BusyD1 <= 1'b0; end
115 else begin
116
BusyD1 <= Busy;
117
if( DetcSta||IsRsta||IsSta)Busy <= 1'b1; else if( DetcStp&&(s2==MScl_IDLE))
Busy <= 1'b0;
118 end
119 end
120
121 /*******Abitration Lose Detect**/
123
if(!Rst )begin IsABL <= 1'b0; end
124
else begin
125
if(
IsABLRst
)IsABL<=0;
else
if(( BusyD1&&GenSta )||(( DetcStpD1 )&&( !GenStp ))) IsABL <= 1'b1;
126
end
127 end
128
129 /*******Generate Start or Stop bit **************/
131
if( !Rst )begin GenSta <= 1'b0; GenStp <= 1'b0; DetcStpD1 <= 1'b0 ;end
132
else begin
133
DetcStpD1 <= DetcStp;
134
if(( !IsStaD1 )&&( IsSta )) GenSta <= 1'b1; else if( DetcSta ) GenSta <= 1'b0;
135
if(( IsStaD1 )&&( !IsSta )) GenStp <= 1'b1; else if( DetcStp ) GenStp <= 1'b0;
136
end
137 end
138
139 /************SclIn SdaIn,IsStaD1**********/
141
if( !Rst )
142
begin SdaIn <= 1'b1; SclIn <= 1'b1; IsStaD1 <= 1'b0; end
143
else begin
144
if( Scl == 1'b0 ) SclIn <= 1'b0; else SclIn <= 1'b1;
145
if( Sda == 1'b0 ) SdaIn <= 1'b0; else SdaIn <= 1'b1;
146
IsStaD1 <= IsSta;
147
end
148 end
109
149
150 /***********detect stop***************/
152
if( !Rst || DetcSta )begin DetcStp <= 1'b0; end
153
else begin
154
if(( !SdaIn )&&( Sda != 1'b0 ))
155
begin if( Scl != 1'b0 ) DetcStp <= 1'b1; else DetcStp <= 1'b0; end
156
end
157 end
158
159 /***********Detect Start**************/
161
if( !Rst || s1 == HEADER )begin DetcSta <= 1'b0; end
162
else begin
163
if(( SdaIn )&&( Sda==1'b0 ))
164
begin if( Scl!= 1'b0 ) DetcSta <= 1'b1; else DetcSta <= 1'b0; end
165
end
166 end
167
168 /****************main state machine***********************/
169 always@(posedge Clk )begin
170
if( !Rst )begin
171
s1 <= IDLE; IsRstaRst <= 1'b0; SdaC1En <= 1'b0; RSda <= 1'b1; AckErr <=
1'b0;
172
end
173
else begin
174
IsRstaRst <= 1'b0;
175
case( s1 )
176
IDLE:
177
if(( GenSta || IsRsta )&( s2==MScl_IDLE))
178
begin
179
RSda <= 1;SdaC1En <= 1'b1; if( SdaC1 == 8'd100 )begin SdaC1En <= 0;
s1 <= START; end
180
end
181
START://Generate Start Bite
182
begin IsRstaRst <= 1'b1; RSda <= 0; if( SclNp ) s1 <= HEADER; end
183
HEADER: //Shift Eight Bits Header
184
begin
185
if( BitC1 < 4'd8 ) RSda <= MSda; else s1 <= ACK_HEADER;if( GenStp ) s1
<= STOP;
186
end
187
ACK_HEADER:// Wait Ack Header
188
begin
189
RSda <= 1'b1; if( SclUp ) SdaC1En <= 1'b1;
190
if( SdaC1 == DATA_HOLD )
191
begin SdaC1En <= 1'b0; if( Sda == 1'b0 ) AckErr <= 1'b0; else AckErr <=
1'b1; end
192
if( SclNp ) begin
193
if( !AckErr )begin
if( DirSet ) s1 <= XMIT_DATA; else s1 <=
RCV_DATA; end
194
else begin s1 <= STOP; end
110
195
end
196
end
197
RCV_DATA://Recieve Data
198
begin RSda <= 1'b1; if( GenStp ) s1 <= STOP; else if( BitC1==4'd8 ) s1 <=
ACK_DATA; end
199
ACK_DATA://Recieve Data Ack
200
begin RSda <= MSda; if( SclNp ) begin if( IsRsta ) s1 <= IDLE; else s1 <=
RCV_DATA; end end
201
XMIT_DATA:begin // Send Data
202
if( BitC1 < 4'd8 ) RSda <= MSda;else s1 <= WAIT_ACK;
203
if( GenStp ) s1 <= STOP;
204
else if( IsRsta ) begin SdaC1En <= 1'd0; s1 <= IDLE; end
205
end
206
WAIT_ACK:begin// Wait Ack Send
207
if( SclUp ) SdaC1En <= 1'd1;
208
if( SdaC1 == DATA_HOLD )begin
209
SdaC1En <= 1'b0; if( Sda == 1'b0) AckErr <= 1'b0; else AckErr <=
1'b1;
210
end
211
if( SclNp )begin
212
SdaC1En <= 1'b0;
213
if( !AckErr ) begin if( IsRsta ) s1 <= IDLE; else s1 <= XMIT_DATA;
end
214
else s1 <= STOP;
215
end
216
end
217
STOP:begin //Generate Sotp Bit
218
if( SclUp )SdaC1En <= 1'b1;
219
if( SdaC1 < STOP_HOLD_2 ) RSda <= 1'b0;
220
else if( SdaC1 == STOP_HOLD_2 ) RSda <= 1'b1;
221
else if( SdaC1 == STOP_HOLD )begin SdaC1En <= 1'b0; s1 <= IDLE; end
222
end
223
endcase
224
end
225 end
226 //master Scl
227
229
if( !Rst )begin
230
s2 <= MScl_IDLE; MScl <= 1'b1; SclC1En <= 1'b0;
231
end
232
else begin
233
case( s2 )
234
MScl_IDLE:
235
begin
236
MScl <= 1'b1; if( DetcSta ) s2 <= MScl_HIGH;
237
end
238
MScl_HIGH:
239
begin
240
SclC1En <= 1'b1; MScl <= 1'b1;
241
if( SclC1 == SclC1_HIGH )begin if( s1 == IDLE ) s2 <= MScl_IDLE;else
111
s2 <= MScl_LOW; SclC1En <= 1'b0; end

242
end
243
MScl_LOW:
244
begin
245
SclC1En <= 1'b1; MScl <= 1'b0;
246
if( SclC1 == SclC1_LOW )begin SclC1En <= 1'b0; s2 <= MScl_HIGH;
end
247
end
248
endcase
249
end
250 end
251
253
if( !Rst )begin MSda <= 1'b1; end
254
else begin
255
if( s1 == HEADER || s1 == XMIT_DATA ) MSda <= SftOut;
256
else if( s1 == ACK_DATA ) MSda <= IsAck;
257
else MSda <= 1'b1;
258
end
259 end
261
262 wire DOutEn;
263 wire IsI2cLd;
264
265 assign
DOutEn =((s1==HEADER)||(s1==XMIT_DATA)||(s1==RCV_DATA))? 1 :
0;
266
assign
IsI2cLd
=((s1==IDLE )||(s1==WAIT_ACK )||(s1==ACK_HEADER)||DetcSta)? 1 : 0;
267
268 wire SlClk;
269 assign SlClk= (s1==RCV_DATA)? SclUp : SclNp;
270
271 SHIFT8 I2CDATA_REG(
272
.Clk(Clk),
273
.SlClk(SlClk),
274
.Rst(Rst),
275
.IsLoad(IsI2cLd),
276
.DataIn(WrData),
277
.SftIn(SdaIn),
278
.SftEn(DOutEn),
279
.SftOut(SftOut),
280
.DataOut(DataOut)
281
);
282
283 assign BitC1En = (s1==HEADER||s1==RCV_DATA||s1==XMIT_DATA) ? 1:0;
284 assign BitC1Ld = ! BitC1En ;
285
286
BITCNT
u2(.Clk(Clk),.Rst(Rst),.SclNp(SclNp),.LdData(CZero),.CEn(BitC1En),.IsLoad(BitC1Ld),.
DataOut(BitC1));
287 ClkCNT u3(.Clk(Clk),.Rst(Rst),.LdData(CZero), .CEn(SclC1En),.DataOut(SclC1));
112
288 ClkCNT u4(.Clk(Clk),.Rst(Rst),.LdData(CZero), .CEn(SdaC1En),.DataOut(SdaC1));

289
290 PULLUP U0 (.O (Sda));
291 PULLUP U1 (.O (Scl));
292 endmodule
Module SPI
1 module spi(Clk,Rst,Sck,Mosi,Miso,RdData,WrData,DirSet,IsSta,IsDone);
2
3 input Clk;
4 input Rst;
5 output Sck;
6 output Mosi;
7 input Miso;
8 output [7:0] RdData;
9 input [7:0] WrData;
10 input DirSet;
11 input IsSta;
12 output IsDone;
13
14 reg [1:0] SckState;
15 reg s;
16 reg SckEn;
17
18 reg IsDone;
19
20 reg [6:0]SckC;
21 reg [3:0]BitC;
22 reg [7:0]RdData;
23
24
26 wire SftOut;
27
28 reg Sck,SckD1;
29 wire SckUp,SckNp;
30
31 assign SckUp=Sck&&(!SckD1);
32 assign SckNp=!Sck&&(SckD1);
33 always @(posedge Clk) SckD1 <= Sck;
34
35 parameter BIT8 = 4'd8;
36
37 always @(posedge Clk) //count shifted bits
38 if(SckEn && SckUp) BitC <= BitC + 1'b1; else if(BitC == BIT8) BitC<=4'd0;
39
40 assign Mosi= DirSet ? SftOut : 1'b1;
41
42 always @(posedge Clk) // main process
43 if(!Rst)begin
113
44
s<=1'b0; IsDone <= 1'b0; SckEn <= 1'b0;
45 end
46 else begin
47
case(s)
48
0: //IDLE state
49
begin IsDone <= 1'b0; IsDone <= 1'b0; SckEn <= 1'b0; if( IsSta )s<= 1'b1; end
50
1://shift state
51
begin
52
SckEn<=1'b1; if(BitC == BIT8)begin RdData <= DataOut; SckEn <= 1'b0;
IsDone <= 1'b1; s <= 1'b0;end
53
end
54
endcase
55 end
57 // spi clock generator
58
59 parameter TSET = 7'd1;
60
61 always @(posedge Clk) // Shift Clock Process
62 if(!Rst)begin SckC <= 7'd0; Sck <= 1'b0; SckState <= 2'd0;end
63 else begin
64
case( SckState )
65
0:
66
begin SckC <= 7'd0; Sck <= 1'd0; if( SckEn ) SckState <= 2; end
67
1:
68
begin
69
Sck <= 1'b1; if( SckC >= TSET ) begin SckState <= 2; SckC <= 7'd0; end else
SckC <= SckC + 1'b1;
70
end
71
2:
72
begin
73
Sck <= 1'b0;
74
if( SckC >= TSET ) begin SckC<=7'd0; if( SckEn ) SckState <= 1; else
SckState <= 0; end
75
else SckC <= SckC + 1'b1;
76
end
77
endcase
78 end
80 wire SlClk;
81 wire IsSpiLd;
82 assign SlClk = DirSet ? SckNp : SckUp;
83 assign IsSpiLd = IsSta;
84 SHIFT8 SPI_DATA
85
(.Clk(Clk),
86
.Rst(Rst),
87
.SlClk(SlClk),
88
.IsLoad(IsSpiLd),
89
.DataIn(WrData),
90
.SftIn(Miso),
91
.SftEn(SckEn),
92
.SftOut(SftOut),
93
.DataOut(DataOut)
114
94
95
96
97 endmodule
);
Module T24LC02
1 module T24LC02(Clk,SRst,Sda,Scl,SftClk,LchClk,SDout,Sw1);
2 input Clk;
3 output SRst;
4 inout Sda;
5 inout Scl;
6 output SftClk;
7 output LchClk;
8 output SDout;
9 input Sw1;
10
11 parameter IDLE = 4'd0;
12 parameter HEADERw = 4'd1;
13 parameter ADDRw = 4'd2;
14 parameter XMITw = 4'd3;
15 parameter STOPw = 4'd4;
16 parameter HEADERr = 4'd5;
17 parameter ADDRr = 4'd6;
18 parameter XMITr = 4'd7;
19 parameter HEADERrr = 4'd8;
20 parameter READr = 4'd9;
21 parameter WAIT = 4'd10;
22
23
24
25 reg
[3 :0] s;
26 reg
[18:0] C1;
27 reg
[8 :0] Cinit;
28 reg
[7 :0] read_buf;
29 wire [7 :0] RdData;
30 reg
[7 :0] WrData;
31
32 reg
IsSta;
33 reg
DirSet;
34 reg
IsAck;
35 reg
IsRsta;
36 wire
IsBusy;
37 wire
IsRstaRst;
38
39 wire IsDone;
40 reg
IsDoneD1;
41
42 reg
[3:0] Led1;
43 reg
[3:0] Led2;
115
44 wire [3:0] Led3;

45 wire [3:0] Led4;
46
47 wire Rst;
48 assign Rst = Cinit[8];
49
50 always @(posedge Clk ) if( !Cinit[8] ) Cinit <= Cinit + 1'b1;
51
52 wire IsDoneUp;
53 assign IsDoneUp = !IsDoneD1 && IsDone ;
54 always @(posedge Clk ) IsDoneD1 <= IsDone;
55
57
if( !Rst ) begin
58
C1 <=19'd0; s <= 4'd0; read_buf <= 8'd0; DirSet <= 1'b0; WrData <= 8'd0;
59
IsSta <= 1'b0; IsAck <= 1'b0; IsRsta <= 1'b0;
60
end
61
else begin
62
if( IsRstaRst ) IsRsta <= 1'b0;
63
case( s )
64
0:
65
begin IsSta <= 1'b0; IsRsta <= 1'b0; IsAck <= 1'b0; if( !Sw1 ) s <= 4'd1;
Led1 <= 4'd0; Led2 <= 4'd0; end
66
1: // time must > 5MS
67
if( C1[18] != 1'b1 ) C1 <= C1 + 1'b1; else begin C1<=19'd0; s <= 4'd2;end
68
2: // Write Process Write Header
69
if( !IsBusy )begin DirSet <= 1'b1; WrData <= 8'b1010_0010; IsSta <= 1'b1; s
<= 4'd3; Led1 <= 4'd2; end
70
3: // Write Address
71
if( IsDoneUp ) begin WrData <= 8'b0000_1000; s <= 4'd4; Led1 <= 4'd3; end
72
4: // Write Data
73
if( IsDoneUp ) begin WrData <= 8'b0001_0011; s <= 4'd5; Led1 <= 4; end
74
5: // Write Data Finished
75
if( IsDoneUp ) begin IsSta <= 1'b0; s <= 4'd6; Led1 <= 4'd5; end
76
6:
77
if( C1[18] != 1'b1 ) C1 <= C1 + 1'b1; else begin C1<=19'd0; s <= 4'd7;end
78
7: // Write Header
79
if( !IsBusy ) begin WrData <= 8'b1010_0010; IsSta <= 1'b1; s <= 4'd8; Led2
<= 1'b1; end
80
8: //Read Process Write Address
81
if( IsDoneUp )begin WrData <= 8'b0000_1000; s <= 4'd9; Led2 <=4'd2; end
82
9: // Restart and write Header
83
if( IsDoneUp )begin IsRsta <= 1'b1; WrData <= 8'b1010_0011; s <= 4'd10;
Led2 <= 4'd3; end
84
10: // Set Direction
85
if( IsDoneUp )begin DirSet <= 1'd0; s <= 4'd11; Led2 <= 4'd3; end
86
11: //Read Data
87
if( IsDoneUp )begin IsSta <= 1'b0; IsAck <= 1'b1; read_buf <= RdData; s <=
4'd12; Led2 <= 4; end
88
12: // Read End
89
if( Sw1 && !IsSta ) s <= IDLE; else s <= s;
116
90
endcase
91
end
92 end
93
94 I2C t24lc02
95
(
96
.Rst(Rst),
97
.Clk(Clk),
98
.Scl(Scl),
99
.Sda(Sda),
100
.RdData(RdData),
101
.WrData(WrData),
102
.IsSta(IsSta),
103
.DirSet(DirSet),
104
.IsAck(IsAck),
105
.IsRsta(IsRsta),
106
.IsRstaRst(IsRstaRst),
107
.IsDone(IsDone),
108
.IsBusy(IsBusy),
109
.IsABL(IsABL),
110
.IsABLRst(IsABLRst)
111
);
112
113 assign Led3=read_buf[3:0];
114 assign Led4=read_buf[7:4];
115
116 Dpy4 Dpy4_SEG(
117
.Clk(Clk),
118
.Rst(Rst),
119
.SftClk(SftClk),
120
.LchClk(LchClk),
121
.SRst(SRst),
122
.SDout(SDout),
123
.Dpy0(Led1),
124
.Dpy1(Led2),
125
.Dpy2(Led3),
126
.Dpy3(Led4)
127
);
128 endmodule
117
SDRAM 5
Figure 1: SDRAM main Module

SDRAM main Module Function Description
Table 1:
1:SDRAM
Clk
Input
System Clock
Rst
Input
System Reset
SClk
SCmd
Output
Output
SDRAM Clock
SDRAM Command
SBaAddr
Output
SDRAM address bus
SData
SUdqm
InOut
Output
SDRAM data bus

SDRAM
SLdqm
LED
Output
Output
SDRAM
LED drive output
Table 2:SDRAM Module Function Description

Clk
Input
SDRAM module clock
Rst
Input
System Reset
IsWrEn
IsRdEn
input
input
SDRAM module write enable

SDRAM module read enable
IsDone
output
SDRAM module have finished task

118
IsBusy
Addr
output
input
SDRAM module is busy in initial state

SDRAM module address value
WrData
RdData
input
output
Data need to be writen into sdram module

Data need to be read from sdram module
SCmd
SBaAddr
output
output
SDRAM command
SDRAM address bus
SData
SUdqm
InOut
outout
SDRAM data bus

SDRAM UDQM
SLdqm
outout
SDRAM LDQM
Figure 2: SDRAM module inner module
119
Table 3:SDRAMInit Module Function Description

Clk
Input
SDRAM module clock
Rst
Input
System Reset
IsInitSta
IsInitDone
input
output
SDRAM initial module init start

SDRAM initial module init task finished
SCmd
SBaAddr
output
output
SDRAM command
SDRAM address bus
Table 4:SDRAMFun Module Function Description

Clk
Input
SDRAM module clock
Rst
Input
System Reset
IsFunSta
IsFunDone
input
output
SDRAM function module start

SDRAM function module task finished
IsArDone
Addr
output
input
SDRAM function module refresh task finished

SDRAM module address value
WrData
RdData
input
output
Data need to be writen into sdram module

Data need to be read from sdram module
SCmd
SBaAddr
output
output
SDRAM command
SDRAM address bus
SData
SUdqm
InOut
outout
SDRAM data bus

SDRAM UDQM
SLdqm
outout
SDRAM LDQM
Table 5:SDRAMCtr Module Function Description

Clk
Input
SDRAM module clock
Rst
Input
System Reset
IsWrEn
IsRdEn
input
input
SDRAM module write enable

SDRAM module read enable
IsDone
output
SDRAM module have finished task
IsBusy
IsInitDone
output
input
SDRAM module busy in initial state

SDRAM initial module init task finished
IsFunDone
IsArDone
input
input
SDRAM function module task finished

SDRAM function module refresh task finished
IsInitSta
IsFunSta
output
output
SDRAM initial module init start

SDRAM function module start
120
SDRAM
SDRAM 64M SDRAM,64M SDRAM .
Figure 3: SDRAM pins and configuration
64M SDRAM 4 BANK BANK 16M bits.

4bits BANK 4096 1024
8bits BANK 4096 512
16bits BANK 4096 256
16bits
121
Figure 4:16 Meg x 4 SDRAM
SDRAM
S1 INHIBIT NOP
100us
S2PRECHARGE
S3 AUTO REFRESH
S4
S5SDRAM
122
SDRAM
Figure 5:Mode Register

123
SDRAM CAS
M0-M2 M3 M4-6
CAS M7,M8 0M9 M11
Figure 6:initialize timing
124
SDRAM
SDRAM SDRAMInit
SDRAM SDRAM 15.625s
SDRAM
Figure 7:Auto refresh timing

125
Figure 7:Auto refresh timing
126
,
S1 ACTIVE BANK ROW
S2 RCD 15ns
S3 Column DQM.
S4 CAS
S5 trp 15ns
Figure 8:SINGLE READ WITH AUTO PRECHARGE

127
single read with auto precharge
128
,
S1 ACTIVE BANK ROW
S2 RCD 15ns
S3 Column DQM.
S4DQM trp 15ns
Figure 8:SINGLE WRITE

WRITE WITH AUTO PRECHARGE
129
SDRAM
SDRAM
if()else
SDRAM 50MHZ
25MHZ SDRAM
1 SDRAM
2 SDRAM
SDRAMCtr module
1 module SDRAMCtr
2
(Clk,Rst,IsWrEn,IsRdEn,IsDone,IsBusy,IsInitDone,IsFunDone,IsArDone,IsInitSta,IsFunSt
a);
3
4 input Clk;
5 input Rst;
6 input IsWrEn;
7 input IsRdEn;
8 output IsDone;
9 output IsBusy;
10 input IsInitDone;
11 input IsFunDone;
12 input IsArDone;
13 output IsInitSta;
14 output [2:0]IsFunSta;
15
16 /*********************************/
17 parameter T15US = 9'd100;
18 /*********************************/
19 reg [21:0]C1;
20 reg IsRef;
21
22
always @ ( posedge Clk or negedge Rst )
23
if( !Rst )
24
begin C1 <= 22'd0; IsRef <= 1'b0; end
25
else if( IsRef && IsArDone )
26
27
else if( C1 == T15US )
130
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
enable
55
enable
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73

else if( !IsRef )
C1 <= C1 + 1'b1;
/************************************/
reg [2:0]s;
reg [2:0]IsFunSta; //[2] Auto Refresh , [1] Read Action, [0] Write Action
reg IsInitSta;
reg IsBusy;
reg IsDone;
if( !Rst )
begin
s <= 3'd5;
IsFunSta <= 3'b000;
IsInitSta <= 1'b0;
IsBusy
<= 1'b1;
IsDone
<= 1'b0;
end
else
case( s )
// Initial SDRam at first
0: // IDLE state
if( IsRef ) begin IsFunSta <= 3'b100; s <= 3'd1; end
else if( IsRdEn ) begin IsFunSta <= 3'b010; s <= 3'd2; end // Write
else if( IsWrEn ) begin IsFunSta <= 3'b001; s <= 3'd2; end // Read
1: // Auto Refresh Done
if( IsArDone ) begin IsFunSta <= 3'd0; s <= 3'd0; end
2: // Func Done
if( IsFunDone ) begin IsFunSta <= 3'd0; s <= s + 1'b1; end
/***************************************/
3: // Generate Done Signal
begin IsDone <= 1'b1; s <= s + 1'b1; end
4:
begin IsDone <= 1'b0; s <= 3'd0; end
/******************************************/
5: // Initial SDRam
131
74
end
75
76
77
78
80 endmodule
if( IsInitDone ) begin IsBusy <= 1'b0; IsInitSta <= 1'b0; s <= 3'd0;
else begin IsBusy <= 1'b1; IsInitSta <= 1'b1; end
endcase
SDRAMInit module
1 module SDRAMInit(Clk,Rst,IsInitSta,IsInitDone,SCmd,SBaAddr);
2 input Clk;
3 input Rst;
4 input IsInitSta;
5 output IsInitDone;
6 output [4 :0]SCmd;
7 output [13:0]SBaAddr;
8
9 reg [3:0]s;
10 reg [11:0]C1;
11 reg [4:0]SCmd;
12 reg [13:0]SBaAddr;
13 reg IsInitDone;
14 /****************************************/
15 parameter T200US = 12'd4000;
16 /*********************************/
17 parameter _INIT = 5'b01111, _NOP = 5'b10111, _ACT = 5'b10011, _RD = 5'b10101,
_WR = 5'b10100,
18
_BSTP = 5'b10110, _PR = 5'b10010, _AR = 5'b10001, _LMR = 5'b10000;
19
20
21
if( !Rst )
22
begin
23
s <= 4'd0;
24
C1 <= 12'd0;
25
SCmd <= _NOP;
26
SBaAddr <= 14'h3fff; // rAddr[13:12] = BA, rAddr[11:0] = Addr,
all reset by 1
27
IsInitDone <= 1'b0;
28
end
29
else if( IsInitSta )
30
case( s )
31
32
/*********************************************/
33
34
0: // Delay 200us (mininum 100us)
35
if( C1 == T200US -1 ) begin C1 <= 12'd0; s <= s + 1'b1; end
36
else begin C1 <= C1 + 1'b1; end
37
132
38
/*******************************************/
39
40
1: // Send Precharge Command
41
begin SCmd <= _PR; SBaAddr <= 14'h3fff; s <= s + 1'b1; end
42
43
2: // Send 1 nop clock for tRP 20ns
44
begin SCmd <= _NOP; s <= s + 1'b1; end
45
46
3: // Send Auto Refresh Command
47
begin SCmd <= _AR; s <= s + 1'b1; end
48
49
4,5: // Send 2 nop clock for tRFC 63ns
50
51
52
/**********************************************/
53
54
55
56
57
7,8: // Send 2 nop clock for tRFC 63ns
58
59
60
9: // Send LMR command : Burst Read & Write, 3'b010 mean
CAS latecy = 2, Sequential, 8 burst length
61
begin SCmd <= _LMR; SBaAddr <={ 4'd0, 1'b0, 2'd0, 3'b010, 1'b0,
3'b011 }; s <= s + 1'b1; end
62
63
10,11: // Send 2 nop clock for tMRD
64
65
66
/********************************************/
67
68
12:
69
begin IsInitDone <= 1'b1; s <= s + 1'b1; end
70
71
13:
72
begin IsInitDone <= 1'b0; s <= 4'd0; end
73
74
/********************************************/
75
76
endcase
77
78 endmodule
133
SDRAMFun module
1 module
SDRAMFun(Clk,Rst,IsFunSta,IsFunDone,IsArDone,Addr,WrData,RdData,SCmd,SBaAd
dr,SData,SLdqm,SUdqm);
2 input Clk;
3 input Rst;
4 input [2 :0]IsFunSta;
5 output IsFunDone;
6 output IsArDone;
7 input [21 :0]Addr;
8 input [15 :0]WrData;
9 output [15 :0]RdData;
10 output [4 :0]SCmd; // [4]CKE , [3]CSn, [2]RAS, [1]CASn, [0]WEn
11 output [13 :0]SBaAddr; // [13:12]BA , [11:0]Addr
12 inout [15 :0]SData;
13 output SLdqm;
14 output SUdqm;
15
/*************************************/
16
17
parameter _INIT = 5'b01111, _NOP = 5'b10111, _ACT = 5'b10011, _RD =
5'b10101, _WR = 5'b10100,
18
_BSTP = 5'b10110, _PR = 5'b10010, _AR = 5'b10001, _LMR =
5'b10000;
19
20
/*********************************/
21
22 reg [4 :0]s;
23 reg [9 :0]C1;
24 reg [4 :0]SCmd;
25 reg [13:0]SBaAddr;
26 reg [1 :0]SDqm;
27 reg [15:0]RdData;
28 reg IsOut;
29 reg IsFunDone;
30 reg IsArDone;
31
32 always @ ( posedge Clk or negedge Rst )
33
if( !Rst )begin
34
s
<= 5'd0;
35
SCmd
<= _NOP;
36
SBaAddr<= 14'h3fff;
37
SDqm
<= 2'b11;
38
RdData <= 16'd0;
39
IsOut <= 1'b1;
40
IsFunDone <= 1'b0;
41
end
42
else if( IsFunSta[2] )
134
43
case( s )
44
45
/*********************************/
46
47
48
49
50
1,2: // Send 2 nop clock for tRFC - 63ns
51
52
53
/*********************************/
54
55
3: // generte done signal
56
begin IsArDone <= 1'b1; s <= s + 1'b1; end
57
58
4:
59
begin IsArDone <= 1'b0; s <= 5'd0; end
60
61
/*************************************/
62
63
endcase
64
65
case( s )
66
67
0: // Set IO to input and clear reg. RdData
68
begin IsOut <= 1'b0; RdData <= 16'd0; s <= s + 1'b1; end
69
70
1: // Send Active command , Bank address and Row address
71
begin SCmd <= _ACT; SBaAddr <= Addr[21:8]; s <= s + 1'b1;
end
72
73
2: // Send 1 nop clock for tRCD - 20ns
74
75
76
/***************************************/
77
78
3: // Send Read Command and Row address, pull down DQM 1
clock, 4'b0100 mean A0=1 with auto precharge.
79
begin SCmd <= _RD; SBaAddr <= { Addr[21:20], 4'b0100,
Addr[7:0]}; SDqm <= 2'b00; s <= s + 1'b1; end
80
81
4,5: // Send 1 nop clock for CAS Latency, pull up DQM;
82
begin SCmd <= _NOP; SDqm <= 2'b11; s <= s + 1'b1; end
83
84
/******************************************/
85
86
6: // Read Data
87
begin RdData <= SData; s <= s + 1'b1; end
135
88
89
/******************************************/
90
91
7: // generate Done signal
92
begin IsFunDone <= 1'b1; s <= s + 1'b1; end
93
94
8:
95
begin IsFunDone <= 1'b0; s <= 5'd0; end
96
97
/*******************************************/
98
99
endcase
100
101
case( s )
102
103
/***************************************/
104
105
0: // Set IO to output
106
begin IsOut <= 1'b1; s <= s + 1'b1; end
107
108
1: // Send Active Command, bank address and row address
109
begin SCmd <= _ACT; SBaAddr <= Addr[21:8]; s <= s + 1'b1;
end
110
111
112
113
114
/*********************************************/
115
116
3: // negedge FPGA update cmd Write and BRC Addr with auto
precharge
117
begin SCmd <= _WR; SBaAddr <= { Addr[21:20], 4'b0100,
Addr[7:0] }; SDqm <= 2'b00; s <= s + 1'b1; end
118
119
4,5,6: // Send 3 nop clock for tDPL and tRP
120
121
122
/**********************************************/
123
124
7: // generate done signal
125
126
127
8:
128
129
130
/*********************************************/
131
132
endcase
136
133
134
/************************************/
135
assign { SLdqm, SUdqm } = SDqm;
136
assign SData = IsOut ? WrData : 16'hzzzz;
137
/*************************************/
138
139 endmodule
SDRAM module
1 module SDRAM
2(
3
input Clk,
4
input Rst,
5
6
input IsWrEn,
7
input IsRdEn,
8
output IsDone,
9
output IsBusy,
10
11 input [21:0]Addr,
12
input [15:0]WrData,
13
output[15:0]RdData,
14
15
output[4 :0]SCmd,
16
output[13:0]SBaAddr,
17
inout [15:0]SData,
18
19
output SLdqm,
20
output SUdqm
21
22 );
23
24
/***********************************/
25
26
27
wire [2:0]IsFunSta;
28
wire IsInitSta;
29
wire IsInitDone;
30
wire IsFunDone;
31
wire IsArDone;
32
33
SDRAMCtr U1
34
(
35
.Clk( Clk ),
36
.Rst( Rst ),
37
.IsWrEn( IsWrEn ),
// input - from top
38
.IsRdEn( IsRdEn ),
// input - from top
137
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
.IsDone( IsDone ),
// output - to top
.IsBusy( IsBusy ),
// output - to top
.IsInitDone( IsInitDone ),
// input - from U2
.IsFunDone( IsFunDone ),
// input - from U3
.IsArDone( IsArDone ),
// input - from U3
.IsInitSta( IsInitSta ),
// output - to U2
.IsFunSta( IsFunSta )
// output - to U3
);
/***********************************/
wire [4:0]U2SCmd;
wire [13:0]U2SBaAddr;
SDRAMInit U2
(
.Clk( Clk ),
.Rst( Rst ),
.IsInitSta( IsInitSta ), // input - from U1
.IsInitDone( IsInitDone ),
// output - to U1
.SCmd( U2SCmd ),
// output - to selector
.SBaAddr( U2SBaAddr )
);
/***********************************/
wire [4:0]U3SCmd;
wire [13:0]U3SBaAddr;
SDRAMFun U3
(
.Clk
( Clk ),
.Rst
( Rst ),
.IsFunSta ( IsFunSta ), // input - from U1
.IsFunDone( IsFunDone ),
// output - to U1
.IsArDone ( IsArDone ),
.Addr
( Addr ),
// input - from top
.WrData
( WrData ),
// input - from top
.RdData
( RdData ),
// output - to top
.SCmd
( U3SCmd ),
.SBaAddr ( U3SBaAddr ),
.SData
( SData ),
// output - to top
.SLdqm
( SLdqm ),
.SUdqm
( SUdqm )
);
/************************************/
//Selector of SCmd pin and SBaAddr pin
138
87
88
reg [4:0]RCmd;
89
reg [13:0]RBaAddr;
90
91
always @ ( * )
92
if( IsInitSta ) begin RCmd = U2SCmd; RBaAddr = U2SBaAddr; end
93
else if( IsFunSta ) begin RCmd = U3SCmd; RBaAddr = U3SBaAddr; end
94
else begin RCmd = 5'bxxxxx; RBaAddr = 14'bxxxxxxxxxxxxxx; end
95
96
assign SCmd = RCmd;
97
assign SBaAddr = RBaAddr;
98
99
/************************************/
100
101
//assign SQ_IsInitSta = IsInitSta;
102
//assign SQ_IsInitDone = IsInitDone;
103
//assign SQ_Op_Start_Sig = Op_Start_Sig;
104
//assign SQ_Op_IsDone = Op_IsDone;
105
106
/************************************/
107
108 endmodule
Main module
1 module main
2(
3
input Clk,
4
input Rst,
5
6
output SClk,
7
output [4:0]SCmd,
8
output [13:0]SBaAddr,
9
inout [15:0]SData,
10
11
output SUdqm,
12
output SLdqm,
13
14
output [3:0]LED
15 );
16
17
/********************************/
18
19
wire IsDone;
20
wire IsBusy;
21
wire [15:0]RdData;
22
23
139
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
end
64
65
66
67
68
69
70
/***********************************/
parameter T3S = 26'd60000000, T1S = 26'd20000000;
/***********************************/
reg [6:0]s;
reg [25:0]C1;
reg [4:0]x;
reg [15:0]WrData;
reg [21:0]Addr;
reg [3:0]Led;
reg IsWrEn;
reg IsRdEn;
reg Clk1;
always @ ( posedge Clk)Clk1<=!Clk1;
always @ ( posedge Clk1 or negedge Rst )
if( !Rst )
begin
s <= 7'd0;
C1 <= 26'd0;
x <= 5'd1;
WrData <= 16'd0;
Addr <= 22'd0;
Led <= 4'd0;
IsWrEn <= 1'b0;
IsRdEn <= 1'b0;
end
else
case( s )
0: // waiting SDRAM initial
if( !IsBusy ) s <= s + 1'b1;
1:
if( IsDone ) begin IsWrEn <= 1'b0; s <= s + 1'b1; end
else begin IsWrEn <= 1'b1; WrData <= 16'h8421; Addr <= 22'd0;
2:
if( IsDone ) begin IsRdEn <= 1'b0; s <= s + 1'b1; end
else begin IsRdEn <= 1'b1; Addr <= 22'd0; end
3:
begin Led <= RdData[3:0]; s <= s + 1'b1; end
140
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
end
114
115
116
117
4:
if( C1 == T1S -1) begin C1 <= 26'd0; s <= s + 1'b1; end
else C1 <= C1 + 1'b1;
5:
6:
7:
else C1 <= C1 + 1'b1;
8:
9:
10:
else C1 <= C1 + 1'b1;
11:
12:
begin Led <= RdData[15:12]; s <= s + 1'b1;end
/****************************************/
13:
else C1 <= C1 + 1'b1;
14:
else begin IsWrEn <= 1'b1; WrData <= 16'd1; Addr <= 22'd1;
15:
141
end
118
119
120
121
end
122
123
124
125
end
126
127
128
129
end
130
131
132
133
end
134
135
136
137
end
138
139
140
141
end
142
143
144
145
end
146
147
148
149
end
150
151
152
153
end
154
155
16:
17:
18:
19:
20:
21:
22:
23:
24:
25:
142
156
157
end
158
159
160
161
end
162
163
164
165
end
166
167
168
169
end
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
end
192
193
194
195
196
197
198

26:
27:
28:
/*************************************/
29:
else C1 <= C1 + 1'b1;
30:
if( x == 16 ) begin x <= 5'd0; s <= s + 7'd3; end
else if( IsDone ) begin IsRdEn <= 1'b0; s <= s + 1'b1; end
else begin IsRdEn <= 1'b1; Addr <= {17'd0, x}; end
31:
begin Led <= RdData[3:0]; x <= x + 1'b1; s <= s + 1'b1; end
32:
if( C1 == T1S -1) begin C1 <= 26'd0; s <= s - 7'd2; end
else C1 <= C1 + 1'b1;
33:
34:
35:
begin Led <= RdData[3:0]; end
143
199
200
endcase
201
202
/***************************/
203
204
assign SClk = Clk;
205
assign LED = Led;
206
207
/****************************/
208
SDRAM U1
209
(
210
.Clk
( Clk1),
211
.Rst
( Rst ),
212
.IsWrEn ( IsWrEn ),
213
.IsRdEn ( IsRdEn ),
214
.IsDone ( IsDone ),
215
.IsBusy ( IsBusy ),
216
.Addr
( Addr ),
217
.WrData( WrData ),
218
.RdData ( RdData ),
219
.SCmd
( SCmd ),
220
.SBaAddr( SBaAddr ),
221
.SData ( SData ),
222
.SUdqm ( SUdqm ),
223
.SLdqm ( SLdqm )
224
);
225 endmodule
144
IP-CORE
ROM 3
RAM
RAM
RAM
ROM
ROM
ROM
Figure 1
145
Figure 2: Single-port ROM

RAM ROM Figure 2 .
Figure 3: Dual-port ROM

ROM A,B
146
8bits, 256bytes
8bits,
Figure 4
8bits 256bytes ENA Figure 4.
147
ROM
Figure 5
Figure 6: Spartan
Spartan66 Block Memory: Register Port [A|B] Outputs of Memory Primitives and Memory
Bock Ram
Block Ram IP 11
148
ROM..coe.
Figure 7
RSTA 0 7
.
Figure 8
8.
149
Figure 9 Read Rom
Figure 10 Read Rom
Test bench
1 module ROM_tb;
2
3 // Inputs
4 reg clka;
5 reg rsta;
6 reg ena;
7 reg [7:0] addra;
8
9 // Outputs
10
wire [7:0] douta;
11
12
13
ROM uut (
14
.clka(clka),
15
.rsta(rsta),
16
.ena(ena),
17
.addra(addra),
18
.douta(douta)
19
);
20
21
initial begin
22
23
clka = 0;
24
rsta = 1;
25
ena = 0;
26
addra = 0;
27
#10 clka = !clka;
28
#10 clka = !clka;
29
#10 clka = !clka;
30
rsta = 0;
31
forever #10 clka = !clka;
32
// Add stimulus here
33
150
34
end
35
36
always @( posedge clka ) begin
37
if(rsta)begin addra <= 8'd0; ena <= 1'b0; end
38
else begin
39
ena <= 1'b1; addra <= addra +1'b1;
40
end
41
end
42
43 endmodule
151
RAM
RAM
RAM
ROM
ROM
RAM
Figure 1
152

RAM RAM Figure 2 .

RAM 2 A B, 3 A B

RAM A,B
Single Port RAM.
153
8bits, 256bytes
8bits,
Figure 5
154

6

7

WEA WEA
8bits 256bytes , 5
155
Figure 10
Figure 11
11:: Spartan
156

Bock Ram
Block Ram IP 11
10.
Figure 12
0 .
157
Figure 13
.
Figure 14 simulation s in state 0,write data from address 0 to 255
Figure 15 simulation s in state 1,read from address 0 to 255

158
Test bench
1 module BRAM_tb;
2
3 // Inputs
4 reg clka;
5 reg rsta;
6 reg ena;
7 reg [0:0] wea;
8 reg [7:0] addra;
9 reg [7:0] dina;
10
11
// Outputs
12
wire [7:0] douta;
13
14
BRAM uut (
15
.clka(clka),
16
.rsta(rsta),
17
.ena(ena),
18 1 .wea(wea),
19
.addra(addra),
20
.dina(dina),
21
.douta(douta)
22
);
23
24
initial begin
25
26
clka = 1'b0;
27
rsta = 1'b1;
28
ena = 1'b0;
29
wea = 1'b0;
30
addra = 8'd0;
31
dina = 8'd0;
32
#10 clka = !clka;
33
#10 clka = !clka;
34
#10 clka = !clka;
35
rsta = 0;
36
// Wait 100 ns for global reset to finish
37
38
39
end
40
41
reg s;
42
always @( posedge clka) begin
43
if(rsta)begin
44
ena <= 1'b0; wea = 1'b0; addra = 8'd0; dina
45
end else begin
46
ena <= 1'b1;
47
case(s)
159
= 8'd0; s <= 1'b0;
48
0:
49
if(addra<255) begin
50
wea <= 1'b1; addra <= addra + 1'b1; dina <= dina + 1'b1;
51
end
52
else begin
53
wea <= 1'b0; addra <= 8'd0; s <= 1'b1;
54
end
55
1:
56
if(addra<255) begin
57
addra <= addra + 1'b1;
58
end
59
endcase
60
end
61
end
62
63 endmodule
160
RAM
RAM
RAM
ROM
ROM
RAM
Figure 1
161

RAM RAM Figure 2 .

RAM 2 A B, 3 A B

RAM A,B
Single Port RAM.
162
8bits, 256bytes
8bits,
Figure 5
163

6

7

WEA WEA
8bits 256bytes , 5
164
Figure 10
Figure 11
11:: Spartan
Bock Ram
Block Ram IP 11
10.
165
Figure 12
RSTA 0 12
.
166
Figure 13
13.

167
Test bench
1 module BRAM_tb;
2
3 // Inputs
4 reg clka;
5 reg rsta;
6 reg ena;
7 reg [0:0] wea;
8 reg [7:0] addra;
9 reg [7:0] dina;
10
// Outputs
11
wire [7:0] douta;
12
13
BRAM uut (
14
.clka(clka),
15
.rsta(rsta),
16
.ena(ena),
17
.wea(wea),
18
.addra(addra),
19
.dina(dina),
20
.douta(douta)
21
);
22
initial begin
23
24
clka = 1'b0;
25
rsta = 1'b1;
26
ena = 1'b0;
27
wea = 1'b0;
28
addra = 8'd0;
29
dina = 8'd0;
30
#10 clka = !clka;
31
#10 clka = !clka;
32
#10 clka = !clka;
33
rsta = 0;
34
35
36
37
end
38
39
reg s;
40
41
if(rsta)begin
42
43
end else begin
44
ena <= 1'b1;
45
case(s)
46
0:
168
= 8'd0; s <= 1'b0;
47
if(addra<255) begin
48
49
end
50
else begin
51
wea <= 1'b0; addra <= 8'd0; s <= 1'b1;
52
end
53
1:
54
if(addra<255) begin
55
wea <= 1'b1; addra <= addra + 1'b1; dina <= dina - 1'b1;
56
end
57
else begin
58
wea <= 1'b0; addra <= 8'd0; s <= 1'b1;
59
end
60
endcase
61
end
62
end
63
64 endmodule
169
RAM
RAM
RAM
ROM
ROM
RAM
Figure 1
170

RAM RAM Figure 2 .

RAM 2 A B, 3 A B

RAM A,B
Single Port RAM.
171
8bits, 256bytes
8bits,
Figure 5
172

6

7

WEA WEA
8bits 256bytes , 5
173
Figure 10
Figure 11
Bock Ram
Block Ram IP 11
10.
174
Figure 12
RSTA 0 12
.
175
Figure 13
13.

176
Test bench
1 module BRAM_tb;
2
3 // Inputs
4 reg clka;
5 reg rsta;
6 reg ena;
7 reg [0:0] wea;
8 reg [7:0] addra;
9 reg [7:0] dina;
10
11
// Outputs
12
wire [7:0] douta;
13
14
BRAM uut (
15
.clka(clka),
16
.rsta(rsta),
17
.ena(ena),
18 1 .wea(wea),
19
.addra(addra),
20
.dina(dina),
21
.douta(douta)
22
);
23
24
initial begin
25
26
clka = 1'b0;
27
rsta = 1'b1;
28
ena = 1'b0;
29
wea = 1'b0;
30
addra = 8'd0;
31
dina = 8'd0;
32
#10 clka = !clka;
33
#10 clka = !clka;
34
#10 clka = !clka;
35
rsta = 0;
36
37
38
39
end
40
41
reg s;
42
43
if(rsta)begin
44
45
end else begin
46
ena <= 1'b1;
177
= 8'd0; s <= 1'b0;
47
case(s)
48
0:
49
if(addra<255) begin
50
51
end
52
else begin
53
wea <= 1'b0; addra <= 8'd0; s <= 1'b1;
54
end
55
1:
56
if(addra<255) begin
57
addra <= addra + 1'b1;
58
end
59
endcase
60
end
61
end
62
63 endmodule
178
RAM 3
RAM
RAM
RAM
ROM
ROM
RAM
Figure 1
179

RAM RAM Figure 2 .

RAM 2 A B, 3 A B

RAM A,B
Simple DualPort RAM.
180
8bits, 256bytes
256bytes
8bits,
Figure 5
181

6

7

WEA WEA
8bits 256bytes , 5
182
Figure 10
Figure 11
Bock Ram
Block Ram IP 11
10.
183
Figure 12
RSTA 0 12
.
Figure 13
13.
184
Figure 14 simulation Write and Read
Figure 15 simulation Write and Read
Test bench
1 module BRAM_tb;
2 // Inputs
3 reg clka;
4 reg ena;
5 reg [0:0] wea;
6 reg [7:0] addra;
7 reg [7:0] dina;
8 wire clkb;
9 reg rstb;
10
reg enb;
11 reg [7:0] addrb;
12
// Outputs
13
wire [7:0] doutb;
14
15
BRAM uut (
16
.clka(clka),
17
.ena(ena),
18
.wea(wea),
19
.addra(addra),
185
20
.dina(dina),
21
.clkb(clkb),
22
.rstb(rstb),
23
.enb(enb),
24
.addrb(addrb),
25
.doutb(doutb)
26
);
27
initial begin
28
29
clka = 0;
30
ena = 0;
31
wea = 0;
32
addra = 0;
33
dina = 0;
34
rstb = 1;
35
enb = 0;
36
addrb = 0;
37
38
#10 clka = !clka;
39
#10 clka = !clka;
40
#10 clka = !clka;
41
rstb = 0;
42
43
end
44
45
reg IsWr;
46
assign clkb = clka;
47
48
always @(posedge clka)begin
49
if(rstb)begin IsWr <= 1'b0; end
50
else begin
51
IsWr <= !IsWr;
52
end
53
end
54
55
56
if(rstb)begin
57
addra <= 8'd0; dina <=8'd0; ena <= 1'b0;
58
end else begin
59
if(IsWr)begin
60
if( addra < 8'd255 ) begin addra <= addra + 1'b1; dina <= dina + 1'b1;
wea<=1'b1; ena <= 1'b1;end
61
end else begin wea<=1'b0; ena <= 1'b0; end
62
end
63
end
186
64
65
66
if(rstb)begin
67
addrb <= 8'd0; enb <= 1'b0;
68
end else begin
69
70
if(!IsWr)begin
71
if( addrb < 8'd255 ) begin addrb <= addra;enb <= 1'b1;
72
end else enb <= 1'b0;
73
end
74
end
75
76 endmodule
187
end
FIFO 3
Figure 1 select Native
Figure 2 select Common CLK
188
Figure 3 set write width 8,depth 256
Figure 4 set almost full flag
189
Figure 5 select Asynchronous Reset with reset value 1
Figure 6 keep no change
190
Figure 7 start write data into fifo
Figure 8 fifo is full and start read data
Figure 9 read all the data fifo is empty
1 module Fifo_tb;
2 // Inputs
3 reg clk;
4 reg rst;
5 reg [7:0] din;
6 reg wr_en;
7 reg rd_en;
8
191
9 // Outputs
10
wire [7:0] dout;
11 wire full;
12
wire almost_full;
13
wire empty;
14
15
Fifo uut (
16
.clk(clk),
17
.rst(rst),
18
.din(din),
19
.wr_en(wr_en),
20
.rd_en(rd_en),
21
.dout(dout),
22
.full(full),
23
.almost_full(almost_full),
24
.empty(empty)
25
);
26
27
initial begin
28
29
clk = 0;
30
rst = 1;
31
din = 0;
32
wr_en = 0;
33
rd_en = 0;
34
#10 clk = !clk;
35
#10 clk = !clk;
36
#10 clk = !clk;
37
rst = 0;
38
forever #10 clk = !clk;
39
end
40
41
reg [3 : 0] Rst =0;
42
reg s;
43
44
always @( posedge clk ) if( !Rst[3] ) Rst <= Rst + 1'b1;
45
46
always @( posedge clk ) begin
47
if( !Rst[3] ) begin din <= 8'd0; wr_en<=1'b0; rd_en<=1'b0; s <= 1'b0; end
48
else begin
49
case(s)
50
0:
51
if( !almost_full ) begin wr_en <= 1'b1; din <= din + 1'b1; end else begin
wr_en <= 1'b0; s <= 1'b1; end
52
1:
53
if( !empty ) rd_en <= 1'b1; else rd_en <= 1'b0;
54
endcase
55
end
192
56
end
57
58 endmodule
193
DCM
Figure 1 set as shown above
194
Figure 3 set as shown ab
195
Figure 5
Figure 6
196

ERROR:Place:1206 - This design contains a global buffer instance,
<u1/clkout1_buf>, driving the net, <CLK2X_OBUF>, that is driving the
following (first 30) non-clock source pins off chip.
< PIN: CLK2X.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.
< PIN "u1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1136 - This design contains a global buffer instance,
<u1/clkout1_buf>, driving the net, <CLK2X_OBUF>, that is driving the
following (first 30) non-clock source pins.
< PIN: CLK2X.O; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "u1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
I/O ODDR2
xilinx ug381
ug381
ODDR2
197
Figure 8
L8-L27 ERROR.
Figure 9 simulation
198
Main module
1 module main(Clk,CLK2X);
2
3 input Clk;
4 output CLK2X;
5
6 wire CLK2X1;
7 ODDR2 #(
8
// The following parameters specify the behavior
9
// of the component.
10
.DDR_ALIGNMENT("NONE"), // Sets output alignment
11
// to "NONE", "C0" or "C1"
12
.INIT(1'b0),
// Sets initial state of the Q
13
//
output to 1'b0 or 1'b1
14
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
15
//
set/reset
16 )
17 ODDR2_inst (
18
.Q(CLK2X),
// 1-bit DDR output data
19
.C0(CLK2X1), // 1-bit clock input
20
.C1(~CLK2X1), // 1-bit clock input
21
.CE(1'b1), // 1-bit clock enable input
22
.D0(1'b1), // 1-bit data input (associated with C0)
23
.D1(1'b0), // 1-bit data input (associated with C1)
24
.R(1'b0),
// 1-bit reset input
25
.S(1'b0)
// 1-bit set input
26 );
27
28 DCM1 u1 (
29
.CLK_IN1(Clk),
30
.CLK_OUT1(CLK2X1)
31
);
32 endmodule
Test Bench
1 module main_tb;
2 // Inputs
3 reg Clk;
4 // Outputs
5 wire CLK2X;
6 // Instantiate the Unit Under Test (UUT)
7 main uut (
8
.Clk(Clk),
9
.CLK2X(CLK2X)
10
);
11
initial begin
199
12
13
Clk = 0;
14
15
16
end
17 endmodule
200
201
2
SDRAM 100MHZ 5
DCM 100M, 100M 180
Figure 1 SDRAM use DCM
CLK2X,SDRAM CLK2X180
SDRAM
DCM
.
SDRAMCtr parameter T15US = 11'd1500;
SDRAMInit
202
reg [4:0]s;
reg [14:0]C1;
parameter T200US = 15'd20000;
if( !Rst )
begin
s <= 5'd0;
C1 <= 15'd0;
SCmd <= _NOP;
SBaAddr <= 14'h3fff; // rAddr[13:12] = BA, rAddr[11:0] = Addr, all
reset by 1
IsInitDone <= 1'b0;
end
else if( IsInitSta )
case( s )
/*********************************************/
0: // Delay 200us (mininum 100us)
if( C1 == T200US -1 ) begin C1 <= 15'd0; s <= s + 1'b1; end
else begin C1 <= C1 + 1'b1; end
/*******************************************/
1: // Send Precharge Command
begin SCmd <= _PR; SBaAddr <= 14'h3fff; s <= s + 1'b1; end
2: // Send 1 nop clock for tRP 20ns
4,5,6,7,8,9: // Send 2 nop clock for tRFC 63ns
/**********************************************/
11,12,13,14,15,16: // Send 2 nop clock for tRFC 63ns
17: // Send LMR command : Burst Read & Write, 3'b010 mean CAS
203
latecy = 2, Sequential, 8 burst length

begin SCmd <= _LMR; SBaAddr <={ 4'd0, 1'b0, 2'd0, 3'b010, 1'b0,
3'b011 }; s <= s + 1'b1; end
18,19: // Send 2 nop clock for tMRD
/********************************************/
20:
begin IsInitDone <= 1'b1; s <= s + 1'b1; end
21:
begin IsInitDone <= 1'b0; s <= 5'd0; end
/********************************************/
endcase
endmodule
SDRAMFun
if( !Rst )begin
s
<= 5'd0;
SCmd
<= _NOP;
SBaAddr<= 14'h3fff;
SDqm
<= 2'b11;
RdData <= 16'd0;
IsOut <= 1'b1;
IsFunDone <= 1'b0;
end
case( s )
/*********************************/
1,2,3,4,5,6,7: // Send 2 nop clock for tRFC - 63ns
/*********************************/
204
8: // generte done signal

begin IsArDone <= 1'b1; s <= s + 1'b1; end
9:
begin IsArDone <= 1'b0; s <= 5'd0; end
/*************************************/
endcase
case( s )
0: // Set IO to input and clear reg. RdData
begin IsOut <= 1'b0; RdData <= 16'd0; s <= s + 1'b1; end
1: // Send Active command , Bank address and Row address
begin SCmd <= _ACT; SBaAddr <= Addr[21:8]; s <= s + 1'b1; end
/***************************************/
3: // Send Read Command and Row address, pull down DQM 1 clock,
4'b0100 mean A0=1 with auto precharge.
begin SCmd <= _RD; SBaAddr <= { Addr[21:20], 4'b0100,
Addr[7:0]}; SDqm <= 2'b00; s <= s + 1'b1; end
4,5: // Send 1 nop clock for CAS Latency, pull up DQM;
/******************************************/
6: // Read Data
begin RdData <= SData; s <= s + 1'b1; end
/******************************************/
7: // generate Done signal
8:
/*******************************************/
endcase
205
case( s )
/***************************************/
0: // Set IO to output
begin IsOut <= 1'b1; s <= s + 1'b1; end
1: // Send Active Command, bank address and row address
begin SCmd <= _ACT; SBaAddr <= Addr[21:8]; s <= s + 1'b1; end
/*********************************************/
3: // negedge FPGA update cmd Write and BRC Addr with auto
precharge
begin SCmd <= _WR; SBaAddr <= { Addr[21:20], 4'b0100,
Addr[7:0] }; SDqm <= 2'b00; s <= s + 1'b1; end
4,5,6,7: // Send 3 nop clock for tDPL and tRP
/**********************************************/
8: // generate done signal
9:
/*********************************************/
endcase
/************************************/
assign { SLdqm, SUdqm } = SDqm;
assign SData = IsOut ? WrData : 16'hzzzz;
/*************************************/
endmodule
206
Figure 1 pc software communication witch fpga board
USB COM COM COM4,

COM COM4
FPGA
LED,ADC,DAC LED,DAC
7E
FF
FF AA AA 7F
7E ,7F FF,FF,AA AA
SUM SUM 0
207
00,7E,7D,7F 00
7D ,20
PC FPGA PC 255FPGA
255 PC
FPGA
FIFO IP CORE
FPGA
208
Figure 2 main module
main com_slave
Main module
1 `define COM_IN_RD 8'd1
2 `define OUT_C_S 8'd2
3 `define OUT_DAC 8'd3
4
5
module
main( Clk,com0_txd,com0_rxd,SyncADC,SClkADC,ADCD,SyncDAC,SClkDAC,DACD,
LED,SW);
6
7 input Clk;
8 output com0_txd;
9 input com0_rxd;
10 output SyncADC;
11 output SClkADC;
12 input ADCD;
209
13
14 output SyncDAC;
15 output SClkDAC;
16 output DACD;
17 output reg [3:0] LED;
18 input [3:0] SW;
19
20
21 reg [31:0]com0_out_reg;
22 reg [2 :0]com0_send_len;
23 reg com0_ack;
24 wire [7:0]com0_header;
25 wire [31:0]com0_reg_in;
26 wire com0_new_msg_up;
27
28 wire [11:0] AIReg;
29 reg [15:0] AOReg=0;
30
31 reg [3:0]LEDr;
32 wire [1:0]LEDn;
33 assign LEDn=LEDr[1:0];
34
36
LED[LEDn]<=LEDr[3];
37
AOReg[15:12]<=4'b0000;
38
com0_ack<=0;
39
if(com0_new_msg_up)begin
40
case(com0_header[7:0])
41
`COM_IN_RD
:begin
com0_out_reg[31:0]
<=
{0,AIReg[11:4],AOReg[11:4],LED,SW};com0_send_len<=4;com0_ack<=1;end
42
`OUT_C_S
:begin LEDr
[ 3:0 ]<= com0_reg_in[ 3:0 ];
com0_send_len <=0; com0_ack <=1; end
43
`OUT_DAC
:begin AOReg[11:4]<= com0_reg_in[ 7:0 ];
com0_send_len <=0; com0_ack <=1; end
44
default:;
45
endcase
46
end
47 end
48
49
50 wire [7:0]LOCAL_ADDR;
51 assign LOCAL_ADDR = 8'd255;
52
53
54 wire rst;
210
55
56 reg [8:0]C1;
57 assign rst = C1[8];
59
if(!C1[8])C1 <= C1 + 1'b1;
60 end
61
62 com_slave com0( .com_clk(Clk),
63
.com_rst(rst),
64
.com_txd(com0_txd),
65
.com_rxd(com0_rxd),
66
.LOCAL_ADDR(LOCAL_ADDR),
67
.com_send_msg(com0_out_reg),
68
.com_send_len(com0_send_len),
69
.com_send_msg_rq(com0_ack),
70
.com_header(com0_header),
71
.com_get_msg(com0_reg_in),
72
.com_new_msg_rq(com0_new_msg_up)
73
);
74 wire IsADCSta ;
75 wire IsDACSTa;
76
77 assign IsADCSta = 1'b1;
78 assign IsDACSTa = com0_ack ;
79
80
81
AD7478
ADC(.Clk(Clk),.Rst(rst),.IsSta(IsADCSta),.IsBusy(IsADCBusy),.Sync(SyncADC),.SClk(
SClkADC),.AI(ADCD),.AIReg(AIReg) );
82
AD5300
DAC(.Clk(Clk),.Rst(rst),.IsSta(IsDACSTa),.IsBusy(IsDACBusy),.Sync(SyncDAC),.SClk(
SClkDAC),.AO(DACD),.AOReg(AOReg) );
83 endmodule
com_slave module
1 module com_slave(com_clk,com_rst,
2
com_txd,com_rxd,
3
LOCAL_ADDR,
4
com_send_msg,com_send_len,com_send_msg_rq,
5
com_header,com_get_msg,com_new_msg_rq
6
);
7 input com_clk;
8 input com_rst;
9 output com_txd;
211
10 input com_rxd;
11
12 input [7:0]LOCAL_ADDR;
13 input [47:0]com_send_msg;
14 input [2 :0]com_send_len;
15 input com_send_msg_rq;
16 output[7:0]com_header;
17 output[39:0]com_get_msg;
18 output com_new_msg_rq;
19
20 `define SEND_IDLE 4'd0
21 `define SEND_START 4'd1
22 `define SEND_ADDR 4'd2
23 `define SEND_ADDR_TURN 4'd3
24 `define SEND_DATA 4'd4
25 `define SEND_DATA_TURN 4'd5
26 `define SEND_SUM 4'd6
27 `define SEND_SUM_TURN 4'd7
28 `define SEND_END
4'd8
29
30 `define SLAVE_IDLE 3'd0
31 `define SLAVE_ADDR 3'd1
32 `define SLAVE_ADDR_TURN 3'd2
33 `define SLAVE_RECV 3'd3
34 `define SLAVE_RECV_TURN 3'd4
35 `define SLAVE_END 3'd5
36
37 wire fi_fu;
38 wire IsRxdDone;
39 wire IsTxdDone;
40
41 reg [7:0]send_msg_men[5:0];
42 reg [7:0]sum_out;
43 reg fi_wr;
44 reg [7:0]fi_in;
45 reg [2:0]com_msg_rq_lens;
46 reg [2:0]send_len;
47 reg [3:0]send_state;
48
49 wire[7 :0]master_addr;
50 wire[7 :0]com_header;
51 wire[39:0]com_get_msg;
52 reg [2 :0]rcv_i;
53 reg [2 :0]slave_state;
54 reg [7 :0]sum_in;
212
55 reg com_new_msg_rq;
56 reg [7 :0] slave_rcv_men[6:0];
57
58 always@(posedge com_clk)begin
59
if(!com_rst)begin
60
send_msg_men[0]<=0;send_msg_men[1]<=0;send_msg_men[2]<=0;
61
send_msg_men[3]<=0;send_msg_men[4]<=8'b0000_0000;
62
sum_out<=0;
63
fi_wr<=0;fi_in<=0;send_len<=0;send_state<=0;end
64
else begin
65
if(com_send_msg_rq)begin
66
sum_out<=0;fi_wr<=0;
67
com_msg_rq_lens<=com_send_len;
68
send_msg_men[0]<=com_send_msg[7 : 0];
69
send_msg_men[1]<=com_send_msg[15: 8];
70
send_msg_men[2]<=com_send_msg[23:16];
71
72
73
74
send_state<=`SEND_START;
75
end
76
case(send_state)
77
`SEND_IDLE : begin sum_out<=0;fi_wr<=0; end
78
`SEND_START:begin // slave send start flag
79
send_len<=0;
80
if(!fi_fu)begin fi_wr<=1;fi_in<=8'h7e;send_state<=`SEND_ADDR;end
81
else begin fi_wr<=0;send_state<=send_state;end
82
end
83
`SEND_ADDR:begin // slave send master addr
84
if(!fi_fu)begin
85
if(master_addr==8'h7e||master_addr==8'h7d||master_addr==8'h7f||master_addr==8'h00)be
gin
86
fi_in<=8'h7d
;fi_wr<=1;sum_out<=sum_out^master_addr;send_state<=`SEND
_ADDR_TURN;
87
end
88
else begin
89
fi_in<=master_addr;fi_wr<=1;sum_out<=sum_out^master_addr;send_state<=`SEND_
DATA;
90
end
91
end else begin fi_wr<=0;send_state<=send_state; end
92
end
93
`SEND_ADDR_TURN:begin
213
fi_in<=master_addr^8'h20;fi_wr<=1;send_state<=`SEND_DATA;end
94
`SEND_DATA:begin // salve send data to master
95
if(send_len<com_msg_rq_lens)
96
if(send_msg_men[send_len]==8'h7e||send_msg_men[send_len]==8'h7d||send_msg_men[s
end_len]==8'h7f||send_msg_men[send_len]==8'h00)begin
97
fi_in<=8'h7d
;fi_wr<=1;sum_out<=sum_out^send_msg_men[send_len];send_state
<=`SEND_DATA_TURN;
98
end else begin
99
if(!fi_fu)
begin
fi_in<=send_msg_men[send_len];send_len<=send_len+1;sum_out<=sum_out^send_msg_
men[send_len];
100
end
101
else begin fi_wr<=0;send_state<=send_state;end
102
end
103
else begin fi_wr<=0;send_state<=`SEND_SUM;end
104
end
105
`SEND_DATA_TURN:begin
106
fi_in<=send_msg_men[send_len]^8'h20;fi_wr<=1;send_len<=send_len+1;send_state<=`S
END_DATA;
107
end
108
`SEND_SUM:begin
109
if(!fi_fu)begin
110
if(sum_out==8'h7e||sum_out==8'h7d||sum_out==8'h7f||sum_out==8'h00)begin
111
fi_in<=8'h7d;fi_wr<=1;send_state<=`SEND_SUM_TURN;
112
end
113
else begin fi_in<=sum_out;fi_wr<=1;send_state<=`SEND_END;end
114
end else begin fi_wr<=0;send_state<=send_state;end
115
end
116
`SEND_SUM_TURN:begin
fi_wr<=1;fi_in<=sum_out^8'h20;send_state<=`SEND_END;end
117
`SEND_END:begin
118
if(!fi_fu)begin fi_wr<=1;fi_in<=8'h7f;send_state<=`SEND_IDLE;end
119
else begin fi_wr<=0;send_state<=send_state; end
120
end
121
endcase
122
end
123 end
124
125 assign master_addr[7 : 0]=slave_rcv_men[0];
126 assign com_header [7 : 0]=slave_rcv_men[1];
127 assign com_get_msg[7 : 0]=slave_rcv_men[2];
214
128 assign com_get_msg[15: 8]=slave_rcv_men[3];

129 assign com_get_msg[23:16]=slave_rcv_men[4];
132
133 wire [7:0]com_rxdout;
134
135
136
137 always @(posedge com_clk)begin
138
if(!com_rst)begin
rcv_i<=0;slave_state<=`SLAVE_IDLE;com_new_msg_rq<=0;sum_in<=0;end
139
else begin
140
if(IsRxdDone&&com_rxdout==8'h7e)begin
slave_state<=`SLAVE_ADDR;rcv_i<=0;com_new_msg_rq<=0;sum_in<=0;end
141
case (slave_state)
142
`SLAVE_IDLE:begin
143
rcv_i<=0;com_new_msg_rq<=0;sum_in<=0;
144
end
145
`SLAVE_ADDR:begin
146
if(IsRxdDone)begin
147
if(com_rxdout==8'h7d)begin
slave_state<=`SLAVE_ADDR_TURN;end
148
else
if((com_rxdout==8'h7f)||(com_rxdout!=LOCAL_ADDR))begin
slave_state<=`SLAVE_IDLE;end
149
else
begin
sum_in<=sum_in^com_rxdout;slave_state<=`SLAVE_RECV;end
150
//else slave_state<=`SLAVE_IDLE;
151
end
152
else slave_state<=slave_state;
153
end
154
`SLAVE_ADDR_TURN:
155
if(IsRxdDone)begin
156
if(com_rxdout^8'h20==LOCAL_ADDR)begin
157
sum_in<=sum_in^com_rxdout^8'h20;slave_state<=`SLAVE_RECV;
158
end
159
else slave_state<=`SLAVE_IDLE;
160
end
161
`SLAVE_RECV:begin
162
if(IsRxdDone)begin
163
if(com_rxdout==8'h7d)begin
slave_state<=`SLAVE_RECV_TURN;end
164
else if(com_rxdout==8'h7f)begin slave_state<=`SLAVE_END ;end
165
else
begin
slave_rcv_men[rcv_i]<=com_rxdout;sum_in<=sum_in^com_rxdout;rcv_i<=rcv_i+1;slave
215
_state<=slave_state;end
166
end
167
end
168
`SLAVE_RECV_TURN:begin
169
if(IsRxdDone)begin
170
slave_rcv_men[rcv_i]<=com_rxdout^8'h20;sum_in<=sum_in^com_rxdout^8'h20;rcv_
i<=rcv_i+1;slave_state<=`SLAVE_RECV;end
171
end
172
`SLAVE_END:begin
173
if(sum_in==0)begin com_new_msg_rq<=1;end
174
slave_state<=`SLAVE_IDLE;
175
end
176
endcase
177
end
178 end
179
180 reg IsTxdSta;
181 reg fi_rd;
182 wire [7:0]fi_out;
183
184 wire fi_rst;
185 assign fi_rst=!com_rst;
186
187
UartRxd
U1
(.Clk(com_clk),.Dout(com_rxdout),.IsDone(IsRxdDone),.Rxd(com_rxd));
188
UartTxd
U2
(.Clk(com_clk),.IsSta(IsTxdSta),.Din(fi_out),.IsDone(IsTxdDone),.Txd(com_txd));
189
fifo
uut_fifo
(.clk(com_clk),.rst(fi_rst),.din(fi_in),.wr_en(fi_wr),.rd_en(fi_rd),.dout(fi_out),.almost_full
(fi_fu),.empty(fi_ep));
190
191 always @(posedge com_clk)begin //read fifo and send data
192
if(!com_rst) begin IsTxdSta<=0;fi_rd<=0; end
193
else begin
194
fi_rd<=0; IsTxdSta<=0;
195
if((!fi_ep)&&IsTxdDone&&IsTxdSta==0)begin
196
fi_rd<=1;IsTxdSta<=1;
197
end
198
end
199 end
200 endmodule
216
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217

Spartan6 Verilog

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OPENPUU

SDRAM 100MHZ 5........................................................................................... 202

XC6SLX9-TQG144 Xilinx Spartan6 FPGA

PL2303 USB TO UART

64Mbit Independent SDRAM

LDOO 3.3V A05

LDOO 1.2V A03

M25P16 16Mbits SPI Flash

AD7478 SPI Serial 8bits ADC with 1MSPS

AD5300 SPI Serial 8bits DAC with 1MSPS

ENC28J60T/SS 10M Ethernet

HR911105A Network transformer

DC2.0 Power Input

Power Switch select Power source

ADC input and DAC output

JTAG Program Port

4Bits Seven Segment LED

LED system state LED

ADC And DAC

1MSPS 8bits SPI ADC.

1MSPS 8bits SPI DAC.

PCB Top View

Figure 1: RunLed Module

module RunLed(Clk,Rst,Led); Clk,Rst,Led

Top Module FPGA

output output [3:0] Led;

reg reg [3 :0] Led;

wire wire C1_Clk; C1_Clk wire

always @( ) always @( posedge Clk )

assign output ,inout wire

always @( posedge clk ) begin //

<= A<=B A B A B TURE,

> A>B A B A B TURE, FALSE

>= A>=B A B B TURE,

!= A!=B A B A B TURE FALSE.

A=8b1111_0000; B=8b1010_1111; A&B

A=8b1111_0000; B=8b1010_1111; A^B

&& A=1,B=2; A&&B TRUE; A=1,B=0, A&&B

Figure 2: Path and delay time

while for if() else if()

#10 10ns #100 100ns.

Figure 3:RunLed Simulation

Figure 1: Button Module

Figure 2 : Button Simulation

Figure 1: UartLoop Module

Uart serial out

Top module Sub module

Top module UartRxd Uart_Txd.

U1 .IsDone(IsRxdDone), IsDone UartRxd

Figure 3: UartTxd Module

Uart serial out

Start Send Data when from 0 to 1

Data needed to been sent

Figure 4: Uart Timing

1 module UartTxd (Clk,IsSta,Din,IsDone,Txd);

Figure 5: case module

assign TxdUp = IsSta1 & (!IsSta2);

Figure 6: Three registers synchronization

Figure 7: Metastable Timing

Figure 8: Metastable Timing

Module Uart Rxd

IDLE RXD SAMP

Uart Block Ram 4

Block RAM Uart FPGA