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40-GHz Transimpedance Amplifier With Differential Outputs Using InPInGaAs Heterojunction Bipolar Transistors
Charles Q. Wu, Emilio A. Sovero, Member, IEEE, and Bruce Massey, Member, IEEE
AbstractHigh-gain and high-bandwidth transimpedance amplifiers (TIAs) are required for fiber-optic receiver modules. This paper reports on the design, fabrication, and characterization of a 40-Gb/s TIA for SONET/SDH STS-768/STM-256 applications based on an InPInGaAs single heterojunction bipolar transistor (SHBT) process developed at Vitesse Semiconductor Corporation (Vitesse Indium Phosphide Release 1 or VIP-1). This amplifier consists of a single-ended input transimpedance pre-amplifier and a differential output post-amplifier. The measured differential transimpedance is 1800 with 3-dB bandwidth greater than 40 GHz. The high gain of this circuit eliminates the need for a standalone limiting amplifier between the conventional transimpedance preamplifier and the demultiplexer in short-reach applications.

Fig. 1. Block diagram of a typical 40 Gb/s optical receiver module. PA: post-amplifier.

Index Terms40 Gb/s, post-amplifier, single heterojunction bipolar transistor (SHBT), transimpedance amplifier (TIA).

I. INTRODUCTION PTICAL fiber transmit systems with a data rate of 40 Gb/s (STS-768) are currently under development. A typical fiber-optic communication receiver system is illustrated in Fig. 1. The optical signal is first detected and converted to electronic current by a photodetector. A transimpedance amplifier (TIA) is used to convert the current swing to a voltage swing at its output. A post-amplifier is typically utilized to amplify the signal into a clock and data recovery unit (CDR), and then into a demultiplexer (DEMUX) which deserializes the high-speed data into a parallel data stream [1]. InPInGaAs-based heterojunction bipolar transistor (HBT) TIAs have been reported in recent years [2][5]. Previously reported designs [2], [3] used an emitter follower as the output buffer. This resulted in high bandwidth performance but suffered high return loss ( ) that causes time-domain jitter. To improve the return loss and increase the transimpedance gain, an integrated version of the transimpedance pre-amplifier and post-amplifying stages with differential outputs was designed. In contrast to most distributed amplifier designs with ac-coupled outputs, this lumped-design has dc-coupled outputs. This eliminates the requirement for a dc block (capacitor or bias-T) between the TIA and CDR/DEMUX. In addition, the InPInGaAs material system allows monolithic integration of the TIA with a p-i-n photodetector.

Fig. 2. Measured f and f performance with various collector current I of a transistor with effective emitter area of 1.2 m 4.3 m.

II. DEVICE PERFORMANCE AND PROCESSING InPInGaAs single heterojunction bipolar transistor (SHBT) devices based on the Vitesse Indium Phosphide Release 1 of 30, of (VIP-1) process have a dc current gain of 150 GHz, as shown in Fig. 2. High 150 GHz, and and are achieved at much lower current density ( 1 mA/ m ) compared with the state-of-the-art SiGe HBT devices. This advantage enables designs of low power consumption. The VIP-1 process has vertical mesa isolated n-p-n bipolar transistors with self-aligned base. Both transistors and diodes are scalable. The minimum effective emitter width is 0.8 m. Further lithographic improvement can easily increase the and for future applications. Proprietary contacts with low resistance and high thermal stability over 400 C enable high wafer yield and good reliability. The VIP-1 process also features three layers of aluminum interconnect metal, precision resistors, and MIM capacitors on 4-in InP wafers.

Manuscript received January 15, 2003; revised April 30, 2003. The authors are with Vitesse Semiconductor Corporation, Camarillo, CA 93021 USA (e-mail: cwu@vitesse.com). Digital Object Identifier 10.1109/JSSC.2003.815927

0018-9200/03$17.00 2003 IEEE

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Fig. 3.

TIA block diagram.

Compared with other technologies, insulating InP substrate allows higher bandwidth interconnects (limiting aspect of noise. The 40-Gb/s receiver design). It has very low ( 4 V) of InP transistors is high breakdown voltage also suitable for output driving stages. Comparing to SiGe of InP HBTs gives more headroom for the process, lower and same power-supply designs. In addition, both can be tailored with appropriate epi design. With the help of these process advantages, a 40-Gb/s 16 : 1 multiplexer (MUX) 1 with integrated pseudorandom bit sequence (PRBS) 2 generator (close to 5000 HBTs) has been demonstrated [10]. The 40-Gb/s TIA circuits have been fabricated based on the same process. The results are reported in the following. III. CIRCUIT DESIGN The functional block diagram of the TIA is depicted in Fig. 3. The pre-amplifier is designed to have a transimpedance gain of 250 with the input port optimized for packaging with a 50-GHz bandwidth p-i-n photodetector. The post-amplifier consists of a gain stage and an output buffer. It has a single-ended voltage gain of 12 dB and the simulated output return loss ( ) is lower than 10 dB up to 60 GHz. This integration is targeted to achieve the differential gain of 2 k and the bandwidth of 40 GHz needed for OC-768 photoreceiver modules. The transimpedance pre-amplifier uses a conventional common-emitter feedback architecture (Fig. 4) with a single power supply. This architecture has better noise performance compared with the common-base approach [9]. A peaking is used to increase the overall bandwidth in capacitor contrast of inductor peaking [4]. Two diodes and resistor provide the dc offset regulation to increase the dynamic range (maximum input current) of the pre-amplifier up to 5 mA (peak-to-peak). To optimize the tradeoff between bandwidth, noise, and dynamic range, extensive simulations have been run and to select the most appropriate values of transistor sizes. The design was simulated with the 50-GHz photodetector model and a 120-pH bond-wire inductance between the photodetector and the TIA. The pre-amplifier without the bond wire has also been characterized and is reported in this paper. The post-amplifier has two stages: the gain stage and the output buffer. Fig. 5 illustrates the schematic of the first stage

Fig. 4.

Schematic of transimpedance pre-amplifier.

Fig. 5.

Schematic of one stage of the post-amplifier.

of the post-amplifier. It is a modified Cherry Hopper design [5], and [6]. The gain is controlled by current source , provide feedback from the output to the collector of . This parallel-feedback design has wider bandwidth than the conventional Cherry Hopper circuit [6]. This stage also provides a conversion of the single-ended input signal to differential output. The output buffer is an additional gain stage and uses the same architecture. A traditional Cherry Hopper circuit is not desirable for dc-coupled current mode logic (CML)-type output buffers due to the nonzero voltage offset. In this modified archibypasses the current from tecture, the feedback transistor , bringing the high level close to 0 V. and also improve the return loss ( ). In contrast to standard CML, this output buffer produces a higher gain bandwidth product.

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Fig. 8.

Transimpedance gain of the pre-amplifier over the frequency.

Fig. 6. Schematic of emitter followers.

Fig. 9. Transimpedance test methodology comparison.

IV. CHARACTERIZATION OF PRE-AMPLIFIER POST-AMPLIFIER STAGES

AND

The effective transimpedance gain without photodetector was tested on wafer with coplanar probes. It was calculated from measured S-parameters based on the equation
Fig. 7. Chip photograph of the TIA circuit.

Two emitter followers were added between gain stages to provide dc left shifting. With proper design, the output impedance is adjusted to be more inductive, resulting in a peaking of the and are gain response and an improved bandwidth [9]. used to damp possible local resonances (Fig. 6). For a 40-GHz or higher speed design, the distributed effects of the RF and ground interconnects have to be taken into account [5], [8]. In general, the length of high-speed signal and ground paths should be reduced to a minimum. A photograph of the IC is shown in Fig. 7. The overall chip size is approximately 1 mm 1 mm. In addition, the power supply is decoupled with on-chip bypass capacitors of 60 pF. Serial damping resistors (36 ) are also used in conjunction with the bypass capacitors to dampen any potential resonances [7]. To minimize undesired feedback and possible oscillation, the power-supply lines between pre-amplifier and post-amplifier are separated on chip. Future versions will reduce the length of output 50- transmission lines to a minimum.

with equal to 50 [4]. The probes have been calibrated to assure the accuracy of all S-parameters. of the pre-amplifiers (50- load) with different feedThe back resistors of 270350 has been characterized (Fig. 8). A 3-dB bandwidth of more than 40 GHz and gain of 4547 dB (180230 ) have been achieved. A test chip has been designed to verify the transimpedance over frequency. It uses a 1-k resistor to convert the input voltage swing to the current swing into the TIA [3]. Measured bandwidth closely matches the value calculated from the measured S-parameters, as shown in Fig. 9. Instead of 50 , lower input impedance of the TIA can increase the RC-limited bandwidth of the detector [5]. Measured input impedance of the reported design is 35 . To demonstrate the TIA output capability, a 40-Gb/s eye di1 PRBS) of the post-amplifier stage agram measurement (2 only on a different test chip is presented in Fig. 10. The input signal is 100 mV . Therefore, the post-amplifier (12-dB gain)

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Fig. 10.

The 40-Gb/s eye diagram of the post-amplifier.

Fig. 13. Phase and group delay variation of the transimpedance over the frequency.

Fig. 11.

Measured S-parameters (single-ended) of the TIA.

Fig. 14. Large-signal measurement of the TIA.

Fig. 12. Transimpedance gain of the TIA over the frequency.

demonstrates output amplitude of 400 mV (800-mV differential). V. EXPERIMENTAL RESULTS OF THE COMBINED CIRCUIT The whole TIA IC dissipates 600 mW at a power supply of 5.2 V and an ambient temperature of 27 C. The circuit also operates at 85 C with no performance degradation. is lower than Fig. 11 shows the measured S-parameters. 8 dB up to 60 GHz. Local variation of is less than 0.5 dB. As shown in Fig. 12, the whole circuit exhibits a single-ended transimpedance gain of 59 dB (1800- differential) and 3-dB bandwidth of 42 GHz. Measured gain is 1 dB less than the simulated result. The difference was mainly caused by slightly lower sheet resistance of the resistors versus simulation.

The phase of varies linearly with frequency, indicating a small group delay ( 10 ps), as shown in Fig. 13. This result also verified the accuracy of the test setup calibration. Simulated rms input-referred noise current is 4.5 A (060 GHz). This value translates into an input sensitivity of 63 A at a bit-error rate (BER) of 10 . However, the measured input referred noise is 7 A. The difference is mainly due to the undesired transimpedance peaking as shown in Fig. 13. An input current of 100 A to 5 mA has been applied to the circuit. The measured output swing amplitude is illustrated in Fig. 14. The output starts to limit at 400800 A. Before the limiting point, the slope in the figure shows a single-ended transimpedance of 900 , or a differential value of 1800 . Beyond 800 A, the output swing is limited to 480 mV. Fig. 15 shows 10-Gb/s data eyes of the TIA output with 1 PRBS input. The measured dynamic range of the TIA 2 is 45 mA. The output rise/fall time was mainly limited by the edge rate of the input signal rather than the TIA. Plans are to integrate a 4050-GHz photodetector or an equivalent LRC test module [3] and a 40-Gb/s signal source to the TIA for final 40-Gb/s BER test.

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REFERENCES
[1] E. A. Sovero, A. Hendarman, B. Massey, C. Q. Wu, B. McDonough Sr., N. Hendrickson, A. Huelsman, and I. Deyhimy, Recent progress in 40 Gb/s IC/OEIC design and manufacturing, in Proc. Laser and ElectroOptic Society (LEOS) Meeting, Nov. 2001, pp. 501502. [2] A. Huber, D. Huber, T. Morf, H. Jackel, C. Bergamaschi, V. Hurm, M. Ludwig, and M. Schlechtweg, Monolithic, high transimpedance gain (3.3 k
), 40 Gb/s InP-HBT photoreceiver with differential outputs, Electron. Lett., vol. 35, no. 11, pp. 897898, May 27, 1999. [3] J. Mullrich, H. Thurner, E. Mullner, J. F. Jensen, W. E. Stanchina, M. Kardos, and H.-M. Rein, High-gain transimpedance amplifier in InPbased HBT technology for the receiver in 40-Gb/s optical-fiber TDM links, IEEE J. Solid-State Circuits, vol. 35, pp. 12601265, Sept. 2000. [4] R. K. Montgomery, A. Feygenson, P. R. Smith, R. D. Yadvish, R. A. Hamm, and H. Temkin, A 28-GHz transimpedance pre-amplifier with inductive bandwidth enhancement, in IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, Dec. 1992, pp. 423426. [5] H. D. Huber, R. Bauknecht, C. Bergamaschi, M. Bitter, A. Huber, T. Morf, A. Neiger, M. Rohner, I. Schnyder, V. Schwarz, and A. Jackel, InPInGaAs single HBT technology for photoreceiver OEICs at 40 Gb/s and beyond, J. Lightwave Technol., vol. 18, pp. 9921000, July 2000. [6] N. Ishihara, O. Nakajima, H. Ichino, and Y. Yamauchi, 9 GHz bandwidth, 820 dB controllable-gain monolithic amplifier using AlGaAsGaAs HBT technology, Electron. Lett., vol. 25, no. 19, pp. 13171318, Sept. 14, 1989. [7] W. Pohlmann, A silicon-bipolar amplifier for 10 Gb/s with 45-dB gain, IEEE J. Solid-State Circuits, vol. 29, pp. 551556, May 1994. [8] H.-M. Rein and M. Moller, Design considerations for very-high-speed Si-bipolar ICs operating up to 50 Gb/s, IEEE J. Solid-State Circuits, vol. 31, pp. 10761090, Aug. 1996. [9] H. H. Kim, C. A. Burrus, and J. Bauman, A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver, IEEE J. Solid-State Circuits, vol. 36, pp. 769776, May 2001. [10] A. Hendarman, E. A. Sovero, X. Xu, and K. Witt, STS-768 multiplexer with full rate output data retimer in InP HBT, in IEEE GaAs IC Symp. Tech. Dig., Oct. 2002, pp. 211214. [11] C. Q. Wu, E. A. Sovero, and B. Massey, 40 GHz transimpedance amplifier with differential outputs using InP/InGaAs heterojunction bipolar transistors, in IEEE GaAs IC Symp. Tech. Dig., Oct. 2002, pp. 6368.

Fig. 15.

The 10-Gb/s output eye diagram of the TIA.

TABLE I SUMMARY OF MEASUREMENT RESULTS

VI. SUMMARY AND CONCLUSION These measured results demonstrate that InPInGaAs technology is preferred for design and fabrication of 40-Gb/s TIA. Integration of the transimpedance pre-amplifier and differential post-amplifier on the same IC has been discussed. The performance of the TIA is summarized in Table I. The 42-GHz bandwidth and 1800- differential gain have been measured. The transimpedance bandwidth product of 76 THz is one of the highest values reported to date. High dynamic range of up to of less than 8 dB from 0 to 60 GHz 45 mA and good are also shown in Table I.

Charles Q. Wu received the B.S. degree in materials science and engineering from the University of Science and Technology of China, Hefei, China, the M.S. degree in materials science and engineering from the University of California at Los Angeles, and the second M.S. degree in electrical engineering from the University of Southern California, Los Angeles, in 1990, 1993, and 2000, respectively. Since 1996, he has been a Member of Technical Staff with Vitesse Semiconductor Corporation, Camarillo, CA, where he is currently a Senior Member of the Physical Media Devices group working on analog circuit design for 10/40-Gb/s optical communication systems.

ACKNOWLEDGMENT The authors wish to thank M. Van Dyke and L. Bunz for test and characterization support, B. Li and P. Partyka for transistor modeling, and B. Mayampurath, M. Dru, L. Wiederspahn, and A. Huelsman for valuable suggestions.

Emilio A. Sovero (M85) received the B.S. degree in engineering, the M.S. degree in mechanical engineering, and the Ph.D. degree in applied physics and information science from the California Institute of Technology, Pasadena, in 1970, 1971, and 1977, respectively. He was a Senior Scientist with Rockwell International Science Center, Thousand Oaks, CA, until 2000. He worked in III-V semiconductor (GaAs and InP) circuit development for microwave and millimeter-wave integrated circuits, for high power and low noise. He holds six U.S. patents for his work in this area. Since 2000, he has been with Vitesse Semiconductor Corporation, Camarillo, CA, where he is currently a Principal Engineer involved in various aspects of circuit development and design using Vitesse internal InP foundry. The applications include 40- and 10-GB/s circuit for telecommunications applications. His current areas of interest are broad-band analog amplifiers and millimeter-wave amplifiers using InP bipolar circuits.

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Bruce Massey (M87) received the B.S. degree in engineering physics from the University of Maine at Orono in 1985, and attended advanced courses at the University of Southern California, Los Angeles, from 1988 to 1990. He worked on CMOS mixed-signal design and on the GaAs Pilot Line at TRW and infrared circuit and systems design at the Hughes Santa Barbara Research Center prior to joining Vitesse Semiconductor Corporation, Camarillo, CA, in 1995. He is currently a Senior Member of Technical Staff in the Physical Media Devices group. His research interests include high data-rate analog circuit design and development. Mr. Massey is a member of the IEEE Solid-State Circuits Society, the IEEE Microwave Theory and Techniques Society, and the IEEE Components, Packaging, and Manufacturing Technology Society.