RSL5.

RSP LAD 2 - MAIN --- Total Rungs in File = 2

This program is totally useless... as far as controlling any process. Now on the other hand if you would like to see how different instructions are converted read on. This program was converted using the DHRIO option. Bits in the rack range will be remapped to I/O. Bits outside of this range will point to the INT array (I000 or O000). I/O bit addresses use the format: _RRS:I.Data[M].B where: RR = rack in octal S = Starting module group I = Input (or O for output) M = Module group offset B = Terminal number in decimal Subroutine three bits JSR Jump To Subroutine Prog File Number

0000

U:3

0001

END

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RSL5.RSP LAD 3 - BITS --- Total Rungs in File = 6

This is a page title This is a rung comment. This section of rungs show how BITS are converted. This is the first input INPUT_0 I:000 0000 0 Address comment for I:000/01 INPUT_1 I:000 0001 1 Address comment for I:000/03 INPUT_3 I:000 3 Input comment for I:000/05 INPUT_5 I:000 0002 5 Comment for I:000/10 INPUT_10 I:000 0003 10 Comment for I:000/14 INPUT_14 I:000 14 11 Comment for I:000/15 INPUT_15 I:000 15 12 Comment for I:000/16 INPUT_16 I:000 16 13 Comment for I:000/17 INPUT_17 I:000 17 6 Comment for I:000/11 INPUT_11 I:000 7 Comment for I:000/12 INPUT_12 I:000 Comment for I:000/13 INPUT_13 I:000 Input comment for I:000/06 INPUT_6 I:000 2 Address comment for I:000/04 INPUT_4 I:000 4 Input comment for I:000/07 INPUT_7 I:000 Address comment for I:000/02 INPUT_2 I:000

This is the first output OUTPUT_0 O:000 0 Address comment for O:000/01 OUTPUT_1 O:000 L 1

Address comment for O:000/01 OUTPUT_1 O:000 U 1 Output comment for O:000/17 OUTPUT_17 O:000 17

0004

One shot B3:0 ONS 0

Output for One Shot B3:0 1 END

0005

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RSL5.RSP LAD 4 - TIMERS --- Total Rungs in File = 4

Timers TON Timer with 0.01 time base enable bit T4:0 0000 EN

TON Timer with 0.01 time base timing bit T4:0 TT

TON Timer with 0.01 time base done bit T4:0 DN

TON Timer with 0.01 time base TON Timer On Delay Timer T4:0 Time Base 0.01 Preset 999< Accum 0< TOF Timer with 1.0 time base TOF Timer Off Delay Timer T4:1 Time Base 1.0 Preset 999< Accum 0< RTO Retentive Timer with 0.01 time base RTO Retentive Timer On Timer T4:2 Time Base 0.01 Preset 32767< Accum 0<

EN DN

TOF Timer with 1.0 time base T4:1 0001 DN

EN DN

RTO Retentive Timer with 0.01 time base TT T4:2 0002 TT

EN DN

0003

END

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RSL5.RSP LAD 5 - COUNTERS --- Total Rungs in File = 4

Counters CTU Counter Up enable bit C5:5 0000 CU

CTU Counter Up CTU Count Up Counter Preset Accum CU C5:5 32000< 0< DN

CTD Counter Down enable bit C5:6 0001 CD

CTD Counter Down CTD Count Down Counter Preset Accum CTD Counter under flow bit C5:6 UN CD C5:6 10< 0< DN

CTD Counter over flow bit C5:6 0002 OV 0003

CTD Counter done bit C5:6 DN

CTD Counter Down C5:6 RES

END

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RSL5.RSP LAD 6 - IO --- Total Rungs in File = 6

I/O instructions BTR enable bit N10:0 0000 15 13 12 BTR done bit N10:0 BTR error bit N10:0 BTR Control Block BTR Block Transfer Read Module Type Generic Block Transfer Rack 001 Group 0 Module 0 Control Block N10:0 Data File N7:0 Length 13 Continuous No Setup Screen < BTW Control Block BTW Block Transfer Write Module Type Generic Block Transfer Rack 001 Group 0 Module 0 Control Block N10:5 Data File N7:20 Length 37 Continuous No Setup Screen < MSG Control Block MSG Read/Write Message Control N10:10 Setup Screen < EN DN ER 020 IIN 021 IOT END EN DN ER EN DN ER

BTW enable bit N10:5 0001 15

BTW done bit N10:5 13

BTW error bit N10:5 12

MSG enable bit N10:10 0002 15

MSG done bit N10:10 13

MSG error bit N10:10 12

0003 0004 0005

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RSL5.RSP LAD 7 - CMPR_CMPT --- Total Rungs in File = 10

Compare and Compute instructions 0000 CMP Comparison Expression Compute CPT Compute Dest Expression Limit Test 0001 LIM Limit Test Low Lim Test High Lim 0 0< N11:3 0< 4095 4095<

N11:0 < N11:1

F8:0 0.0< N11:2 * 10000.0

Add ADD Add Source A Source B Dest N11:4 0< 1 1< N11:5 0<

Masked Equal 0002 MEQ Masked Equal Source B3:1 0000000000000000 < Mask 0FFFH 4095< Compare B3:2 0000000000000000 < Equal 0003 EQU Equal Source A Source B N11:9 0< N11:10 0<

Subtract SUB Subtract Source A Source B Dest N11:6 0< N11:7 0< N11:8 0<

Multiply MUL Multiply Source A Source B Dest

N11:11 0< 10 10< N11:12 0<

0004

Not Equal NEQ Not Equal Source A Source B

Divide N11:13 0< 0 0< DIV Divide Source A Source B Dest N11:14 0< N11:15 0< N11:16 0<

0005

Less Than LES Less Than (A<B) Source A N11:17 0< Source B N11:18 0<

Square Root SQR Square Root Source N11:19 0< Dest N11:20 0<

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RSL5.RSP LAD 7 - CMPR_CMPT --- Total Rungs in File = 10

Greater Than 0006 GRT Greater Than (A>B) Source A N11:21 0< Source B N11:22 0< Less than or equal LEQ Less Than or Eql (A<=B) Source A N11:25 0< Source B N11:26 0< Greater than or equal 0008 GEQ Grtr Than or Eql (A>=B) Source A N11:28 0< Source B N11:29 0<

Negate NEG Negate Source Dest N11:23 0< N11:24 0<

To BCD TOD To BCD Source Dest N11:27 0< O:022 0<

0007

From BCD FRD From BCD Source Dest

I:023 0< N11:30 0<

0009

END

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RSL5.RSP LAD 8 - MOV_LOGIC --- Total Rungs in File = 9

Move instructions Move 0000 MOV Move Source T4:0.ACC 0< Dest N12:0 0< Move with mask MVM Masked Move Source N12:1 0< Mask 0FFH 255< Dest N12:2 0< Bitwise And 0002 AND Bitwise AND Source A B3:3 0000000000000000 < Source B B3:4 0000000000000000 < Dest B3:5 0000000000000000 < Bitwise Or 0003 OR Bitwise Inclusive OR Source A B3:6 0000000000000000 < Source B B3:7 0000000000000000 < Dest B3:8 0000000000000000 < Bitwise Exclusive Or XOR Bitwise Exclusive OR Source A B3:9 0000000000000000 < Source B B3:9 0000000000000000 < Dest B3:9 0000000000000000 < Not 0005 NOT NOT Source Dest N12:3 0< N12:4 0<

0001

0004

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RSL5.RSP LAD 8 - MOV_LOGIC --- Total Rungs in File = 9

Clear 0006 CLR Clear Dest N12:5 0<

0007

Bit Field Distribute BTD Bit Field Distributor Source B3:10 0000000000000000 < Source Bit 3 Dest B3:11 0000000000000000 < Dest Bit 10 Length 5

0008

END

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RSL5.RSP LAD 9 - FILE --- Total Rungs in File = 9

File instructions FAL with mode: ALL enable bit R6:2 0000 EN

FAL with mode: ALL done bit R6:2 DN

FAL with mode: ALL error bit R6:2 ER

FAL with mode: ALL FAL File Arith/Logical Control R6:2 Length 100< Position 0< Mode ALL Dest #N13:0 0< Expression #N14:0 + 32

EN DN ER

FAL with mode: INC enable bit R6:3 0001 EN

FAL with mode: INC done bit R6:3 DN

FAL with mode: INC error bit R6:3 ER

FAL with mode: INC FAL File Arith/Logical Control R6:3 Length 150< Position 4< Mode INCREMENTAL Dest N13:101 0< Expression #N14:101 - #N13:0

EN DN ER

FAL with mode: 50 enable bit R6:4 0002 EN

FAL with mode: 50 done bit R6:4 DN

FAL with mode: 50 error bit R6:4 ER

FAL with mode: 50 FAL File Arith/Logical Control Length Position Mode Dest Expression

EN DN ER

R6:4 200< 0< 50 #N13:1 0< N14:101 * #N13:120

FSC with mode: ALL enable bit R6:5 0003 EN

FSC with mode: ALL done bit R6:5 DN

FSC with mode: ALL found bit R6:5 FD

FSC with mode: ALL FSC File Search/Compare Control R6:5 Length 30< Position 0< Mode ALL Expression #N13:200 > 75

EN DN ER

FSC with mode: INC enable bit R6:6 0004 EN

FSC with mode: INC done bit R6:6 DN

FSC with mode: INC found bit R6:6 FD

FSC with mode: INC FSC File Search/Compare Control R6:6 Length 30< Position 0< Mode INCREMENTAL Expression #N13:200 < 75

EN DN ER

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RSL5.RSP LAD 9 - FILE --- Total Rungs in File = 9

FSC with mode: 1 enable bit R6:7 0005 EN

FSC with mode: 1 done bit R6:7 DN

FSC with mode: 1 found bit R6:7 FD

FSC with mode: 1 FSC File Search/Compare Control R6:7 Length 30< Position 0< Mode 1 Expression #N13:200 = 75 Copy

EN DN ER

0006

COP Copy File Source Dest Length File fill

#N13:0 #N14:0 100

0007

FLL Fill File Source Dest Length

0 #N13:1 99

0008

END

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RSL5.RSP LAD 10 - SHIFT --- Total Rungs in File = 5

Shift instructions BSL enable bit R6:10 0000 EN

BSL done bit R6:10 DN

BSL Unload bit R6:10 UL

BSL Control BSL Bit Shift Left File Control Bit Address Length BSR Control BSR Bit Shift Right File Control Bit Address Length FFL Control FFL FIFO Load Source B15:20 FIFO #B15:10 Control R6:12 Length 10< Position 0< FFU Control FFU FIFO Unload FIFO #B15:10 Dest B15:21 Control R6:13 Length 10< Position 0< EU DN EM EN DN EM EN #B15:5 R6:11 I:007/2 64< DN EN #B15:0 R6:10 I:007/1 64< DN

BSR enable bit R6:11 0001 EN

BSR done bit R6:11 DN

BSR unload bit R6:11 UL

FFL enable bit R6:12 0002 EN

FFL done bit R6:12 DN

FFL empty bit R6:12 EM

FFU enable bit R6:13 0003 EU

FFU done bit R6:13 DN

FFU empty bit R6:13 EM

0004

END

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RSL5.RSP LAD 11 - SEQUENCR --- Total Rungs in File = 3

0000

Sequencer instructions SQI/SQO Control SQI Sequencer Input File #B17:0 Mask 0FF0H Source I:026 Control R6:20 Length 8< Position 0< Load sequence file input condition I:001

SQI/SQO Control SQO Sequencer Output File #B17:9 Mask 0FF0H Dest O:024 Control R6:20 Length 8< Position 0<

EN DN

SQL Control SQL Sequencer Load File #B17:0 Source I:026 Control R6:21 Length 8< Position 0< EN DN

0001 10

0002

END

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RSL5.RSP LAD 12 - PROGRAM --- Total Rungs in File = 8

0000

SBR Subroutine Label 5 Q12:5 LBL Input condition I:001

RET Return Label 5 Q12:5 JMP

0001

AFI

0002 11 0003 0004 JSR Jump To Subroutine Prog File Number

MCR

TND

U:12

0005 0006 RET Return

MCR

0007

END

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RSL5.RSP LAD 13 - SPECIAL --- Total Rungs in File = 4

Special instructions FBC enable bit R6:30 0000 EN DN FD IN ER FBC done bit R6:30 FBC found bit R6:30 FBC inhibit bit R6:30 FBC error bit R6:30

FBC File Bit Comparison Source #B18:0 Reference #B18:20 Result #N19:21 Control R6:30 Length 9< Position 0< Control R6:31 Length 9< Position 0<

EN DN FD IN ER

DDT enable bit R6:32 0001 EN

DDT done bit R6:32 DN

DDT found bit R6:32 FD

DDT inhibit bit R6:32 IN

DDT error bit R6:32 ER

DDT Diagnostic Detect Source #B18:0 Reference #B18:20 Result #N19:22 Control R6:32 Length 9< Position 0< Control R6:33 Length 9< Position 0< PID Control block

EN DN FD IN ER

PID enable bit N20:0 0002 15

PID Set Output Mode N20:0 4

PID mode N20:0 1

PID PID Control Block N20:0 Process Variable N7:4 Tieback 0 Control Variable N7:235 Setup Screen <

0003

END

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