Voltages Balancing in Neutral-Point-Clamped Active Rectifiers Based On Current Harmonic Distortion

Voltages Balancing in Neutral-Point-Clamped Active Rectifiers Based on
Current Harmonic Distortion

Mario Marchesoni
Universit di Genova
Dipartimento di Ingegneria
Elettrica
Via allopera Pia 11a
16145 Genova Italy
Tel: +39-010-3532183
Fax: +39-010-3532700
marchesoni@die.unige.it
www.unige.it

Paolo Segarich
Sciro S.p.A.
Via Gavotti, 5/6
16128 Genova Italy
Tel: +39-010-2912701
Fax: +39-010-2912750
p.segarich@sciro.com
www.sciro.com

Ernesto Soressi
ASI Robicon
Power Electronics Research
Center (CRELP)
Via De Marini, 1
16149 Genova Italy
Tel.: +39-010-6402536
Fax.: +39-010-6402540
soressi@ieee.org
www.asirobicon.com

Keywords
Modulation strategies, Multilevel converters, Industrial applications, Converter control
Abstract
A new method, based on current harmonic distortion, is proposed to compensate dc-link capacitors
voltages fluctuations in a Neutral-Point-Clamped (NPC) active rectifier. This approach is very useful
especially in no-load or low-load operations, where other methods fail. Analytical, simulation and
experimental results are presented.
1. Introduction
Multilevel converters are gaining industrial maturity in several applications. The Neutral-Point-
Clamped converter [1] represents one of the most used structures that permits to reach voltage levels
up to 4160V, which is the standard voltage level for medium voltage drives in the USA [2]. The back-
to-back connection of a NPC rectifier (Active Front End, AFE) with a NPC inverter allows to obtain
the best technical performances also on the line-side, where power factor correction is therefore
possible. However, in complex converter structures like this, some hidden problems sometimes appear
and need reliable solutions.
The neutral point balancing problem has been studied in the past, and some solutions have been
proposed, which are based on redundant switching configurations [3-5] or on the addition of zero-
sequence voltage components to the output voltage [6]. However, all these methods seem to be not
always useful in no-load or low-load operations, when the supplied current tends to zero. In real
systems, no-load conditions determine almost always the loss of dc-link capacitors voltages balance,
owing to converter non ideality. A new method is here proposed to compensate dc-link capacitors
voltages fluctuations in a Neutral-Point-Clamped (NPC) active rectifier, that gives good results in all
the operating conditions.
2. Neutral Point Current Evaluation
Figure 1 shows a schematic representation of the NPC converter, based on the three-state switches T
R
,
T
S
, T
T
. Each converter phase current is forced to flow across the Neutral Point (NP) when the switch is
in the 0-position. The stay of each switch in the 0-position is a function of the modulation that is being
used and of the output phase voltages (V
R
, V
S
, V
T
) required. In the following, a Sinusoidal Pulse
Width Modulation (SPWM) will be considered, with a carrier frequency equal to f
s
.
Let us define the m
i
index, that represents the instantaneous duty cycle of each of the three switches
(constant during the switching interval T
s
= 1/f
s
, variable in the fundamental period) that can be easily

Voltages Balancing in Neutral-Point-Clamped Active Rectifiers Based on Current Harmonic Distortion MARCHESONI Mario
EPE 2003 - Toulouse ISBN : 90-75815-07-7 P.1

I
0
i
T
i
S
i
R
v
T
0

-

+

T
T
v
S
0
-

+
T
S
v
R
0

-

+
T
R
V
DW
V
UP
C
D
C
U
NP

Fig. 1: Schematic representation of the NPC converter

derived from the instantaneous reference phase voltage v
i
during the modulation process, for every i-
phase (i = R, S, T), according to (1):

< =
> =
0 if
0 if
i
DW
i
i
i
UP
i
i
v
V
v
m
v
V
v
m
(1)

where V
UP
and V
DW
are the absolute voltage values of the upper and of the lower capacitor,
respectively. When m
i
is greater than zero, the switch T
i
commutes between + and 0, while when m
i
is
lower than zero T
i
commutes between - and 0. The m
i
index represents the time (with respect to the
switching period T
s
) during which the related switch stays in the + position (if v
i
> 0) or in the
position (if v
i
> 0). Each phase current, i
i
, can be considered constant during the switching period T
s
,
otherwise its average value should be considered. Therefore, an average current contribution I
0,i
that
flows across the Neutral Point can be defined as expressed by (2), while the overall average current
contribution I
0
is reported in (3).

( )
i i i
i m I = 1
, 0
(2)

( ) ( ) ( )
T T S S R R
i m i m i m I + + = 1 1 1
0
(3)

Equation (2) defines the instantaneous average current, I
0
, that flows across the NP, that is, the
current averaged on the modulation cycle of T
C
duration. The I
0
current can exhibit irregular
behaviours, especially in transient conditions, which can lead to an incorrect voltage sharing between
the dc-link capacitors. Indeed, if C
U
= C
D
= C, the capacitors voltage difference as a function of time
is given by relationship (4):

=
t
DC
d I
C
V
0
2
(4)

Such capacitance values must be designed in order that, in the worse operating condition, the voltages
unbalance in a switching cycle must be lower than the allowed tolerance (e.g., lower than 5%).

In sinusoidal steady state operations, both the rectifier input currents and voltages assume the
instantaneous average values displayed in Fig. 2 on the left, in the case of purely reactive operating
conditions; on the right, the partial NP current contributions, defined by (2), and the global NP current,
defined by (3), are shown in the same operating conditions.
2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.5
0
0.5
1
Phase voltages
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.5
0
0.5
1
Phase currents

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.5
0
0.5
1
I0,R I0,S I0,T currents
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.5
0
0.5
1
I0 current
Fig. 2: Converter waveforms in purely reactive operating conditions
Left: instantaneous average phase voltages and currents (p.u. vs. time [s])
Right: partial and global neutral point currents (p.u. vs. time [s])

2.1 NP Current Computation in Sinusoidal Steady-State Operations
The NP currents, I
0
and I
0,i
, are clearly dependent on the amplitudes and displacement of the phase
currents and voltages. Relationship (2) is quite complex and is not best suited for the problem
analytical development. However, the NP current can be approximatively expressed using some
trigonometric functions. If the reference rectifier phase voltages (or the 1
st
harmonic component
rectifier phase voltages) are defined as follows (5), where V
DC
is half the dc-link voltage and m is the
modulation index,

( )
|
.
|
\
|
+ =
|
.
|
\
|
+ =
=

3
4
cos
3
2
cos
cos
t mV V
t mV V
t mV V
DC T
DC S
DC R
(5)

and the three instantaneous average (as defined above) rectifier phase currents are expressed by (6),

( )
|
.
|
\
|
+ + =
|
.
|
\
|
+ + =
+ =

3
4
cos
3
2
cos
cos
t A I
t A I
t A I
I T
I S
I R
(6)

relationship (2) can be approximated according to (7):

( ) ( )
|
.
|
\
|
+ |
.
|
\
|
=
|
|
.
|
\
|
|
|
.
|
\
|
|
.
|
\
|
+ + =
|
.
|
\
|
+ |
.
|
\
|
=
|
|
.
|
\
|
|
|
.
|
\
|
|
.
|
\
|
+ + =
|
.
|
\
|
= |
.
|
\
|
+ =

3
8
2 cos
2 2
1
3
8
2 cos 1
2
1
3
4
2 cos
2 2
1
3
4
2 cos 1
2
1
2 cos
2 2
1 2 cos 1
2
1
, 0
, 0
, 0
t
m m
I t
m
I
t
m m
I t
m
I
t
m m
I t
m
I
T T
S S
R R
(7)
3
After some calculations and approximations, the three phase current contributions to the current that
flows across the Neutral Point, expressed by (2), can be represented as follows:

( ) ( ) ( ) ( )
|
|
.
|
\
|
|
.
|
\
|
+ + |
.
|
\
|
+
|
.
|
\
|
+ + |
.
|
\
|
=
|
|
.
|
\
|
|
.
|
\
|
+ + |
.
|
\
|
+
|
.
|
\
|
+ + |
.
|
\
|
=
+
+ |
.
|
\
|
=

3
4
cos
3
8
2 cos
2 3
4
cos
2
1
3
2
cos
3
4
2 cos
2 3
2
cos
2
1
cos 2 cos
2
cos
2
1
, 0
, 0
, 0
t t
A m
t
m
A I
t t
A m
t
m
A I
t t
A m
t
m
A I
I
I T
I
I S
I
I R
(8)

and then:

( ) ( ) ( ) ( )
|
|
.
|
\
|
|
.
|
\
|
+ + |
.
|
\
|
+ +
|
.
|
\
|
+ + |
.
|
\
|
=
|
|
.
|
\
|
|
.
|
\
|
+ + |
.
|
\
|
+ +
|
.
|
\
|
+ + |
.
|
\
|
=
+ +
+ |
.
|
\
|
=

3
4
cos
3
12
3 cos
4 3
4
cos
2
1
3
2
cos
3
6
3 cos
4 3
2
cos
2
1
cos 3 cos
4
cos
2
1
, 0
, 0
, 0
t t
A m
t
m
A I
t t
A m
t
m
A I
t t
A m
t
m
A I
I
I T
I
I S
I
I R
(9)

Therefore, a single-phase contribution to the NP current is given by a fundamental first harmonic
component and a third harmonic component, whose amplitudes is dependent on both phase voltage
and current. The total I
0
value is given by the sum of the three third harmonic contributions expressed
by (9), components and is given by (10):

( ( +

= t
A m
I
I
3 cos
4
3
0
)) (10)
Figure 3 shows, on the left, the Neutral Point currents computed by using (9) and (10), respectively,
obtained by posing m=A
I
=1 and =/2. On the right, the simulated Neutral Point currents, as
expressed by (2) and (3), are shown using the same parameters: the good approximation which has
been obtained can be appreciated.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.5
0
0.5
1
Computed I0,r I0,s I0,t currents
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.5
0
0.5
1
Computed I0 current

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-1
-0.5
0
0.5
1
Simulated I0,r I0,s I0,t currents
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-1
-0.5
0
0.5
1
Simulated I0 current

Fig. 3: Computed Neutral Point currents (p.u. vs. time [s])
Left: approximated Neutral Point currents, computed according to (9) and (10)
Right: simulated Neutral Point currents

4
3. Neutral Point Voltage Control
The analysis performed in the previous section has served as the basis for the synthesis of the
balancing method, that uses additional phase current components, with K amplitude, phase and 3
frequency. In other words, if the A
I
amplitude of the three-phase currents is imposed as follows,

( ) + = t K A
I
3 cos (11)

the Neutral Point current I
0
assumes the expression (12) when a null real power is drawn from the line
that is, when is imposed to be equal to /2. (12) which simply reduces to (13) when also = /2.

( )
|
|
.
|
\
|
|
.
|
\
|
+ |
.
|
\
|
+ +
= |
.
|
\
|
+ +
=
2
cos
2
6 cos
8
3
2
3 cos 3 cos
4
3
0

t
K m
t t
K m
I (12)
( ) ( 1 6 cos
8
3
0
+
= t
K m
I ) (13)
The resulting Neutral Point current, I
0
, is composed by a constant component and a 6th harmonic
component, both proportional to m and K. The 6th harmonic component does not greatly affect the NP
voltage, being at a relatively high frequency and having a zero mean value. Instead, the constant
component can be used to compensate voltage fluctuations in the dc-link capacitors; to this end, a
Neutral Point voltage balancing regulator has been designed, that imposes the required K value.
4. Neutral Point Voltage Regulator
Aim of the control strategy outlined in the previous section is the Neutral Point voltage control in any
operating condition, with particular reference to steady-state operations and even in no-load
operations, that is, with a zero real power drawn from the line. It is worth underlining that, in no-load
conditions, all the conventional balancing algorithms based on redundant switching vectors are not
effective, because there is no current that can be used to perform the balancing action. However, the
application of the new devised balancing control strategy is subjected to the conditions that are
summarized in the following, as stated in the initial part of the paper, which are not always verified.

Sinusoidal operations: this assumption is generally verified in steady-state operations but is not
satisfied during transients. Capacitor dc-link voltages naturally loose their balance in transient
operations and the distorted current injection, described in the previous Section, tends to reduce
their voltage difference, which is completely nullified once steady-state operations is recovered.
Simulation tests allowed us to understand that new devised balancing strategy is not sufficient to
promptly eliminate voltages difference during transient phenomena, therefore dc-link capacitance
values must be suitably designed to absorb voltages fluctuations. The control algorithm dynamics
is comparable to the mains electrical period.

Sinusoidal Pulse Width Modulation: operations ruled by SPWM represent a fundamental
hypothesis to be satisfied, in order that the analytical results that have been shown preserve their
validity. Therefore, Space Vector Modulation (SVM) algorithms cannot be applied with the
proposed technique, unless modulation indexes higher than 0.5 are used. In fact, it is easy to
verify that phase voltage waveforms obtained with SVM and SPWM are similar at high
modulation indexes, which imply operations in the outer hexagonal sectors. However, when a
NPC converter is used as an Active Front End, modulation index is almost constant and equal to
about 0.8 ( 20%) if converter semiconductor devices are correctly exploited in voltage.

The required K amplitude of the modulating signal defined by (11) can be determined using a
conventional PI controller, whose input is the error between the reference (typically set at a zero
value) and the measured dc-link capacitor voltages difference (see Fig. 4). Such a difference, s, has
been expressed on a percent basis, as shown by (14), where V
UP
and V
DOWN
are the measured voltages
of the upper and lower dc-link capacitors, as shown by Fig.1.
5

DW UP
DW UP
V V
V V
s
+
= (14)

The tuning of the PI regulator parameters is critical if an integral gain different from zero is chosen:
the integral action introduces a delay that can limit the regulator effectiveness when abrupt currents
variations are imposed.

Fig. 4: Reactive phase currents amplitude generation
5. Simulation and Experimental Results
First, some simulation results are presented, that refer to a system with a nominal dc-link voltage equal
to 4800 V (2 2400 V) and dc-link capacitance values equal to 18 mF.
Fig. 5 shows the dc-link capacitor voltages when dc-link current variations, from 0 to 650 A (about
half the nominal value) and from 650 to 0 A are imposed (beginning t = 0.8 s, end t = 1.4 s, rise time
and fall time equal to about 1 ms). The initial capacitor voltages are initially unbalanced, as they
differs of about 100 V in the pre-charge stage, and then they reach almost the same value in all the
subsequent stages, when the new devised balancing method is operating. The effectiveness of the
proposed method appears especially in no-load or low-load operations, before and after the load
variations. Figures 6 show the phase currents behaviour during the same transient phenomenon.
Then, other simulation tests have been performed, in order to better show the compensating action
when asymmetric load conditions are imposed. Fig. 7 shows the dc-link capacitor voltages when dc-
link current variations, from 0 to 500 A and from 500 to 0 A are imposed (beginning t = 0.8 s, end t =
1.4 s, rise time and fall time equal to about 1 ms); in this case two current generators load the upper
and lower dc-link terminals with a 5ms delay, thus causing a dc-link capacitors voltage unbalance.

DC-LINK VOLTAGES [V]
0 0.5 1 1.5 2
2150
2200
2250
2300
2350
2400
2450
2500
Time [s]
Fig. 5 Capacitor voltages during system start-up: balancing method is applied after the pre-charge
stage
6

0.16 0.18 0.2 0.22 0.24 0.26 0.28
-2000
-1500
-1000
-500
0
500
1000
1500
2000
2500
PHASE CURRENTS [A]
Time [s]

1.37 1.38 1.39 1.4 1.41 1.42 1.43 1.44 1.45
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
PHASE CURRENTS [A]
Time [s]
Fig. 6 Phase currents during system start-up (on the left) and during load -> no-load (on the right)
transitions

It can be noted that the dc-link capacitor voltages difference is always recovered, with better transient
results when the compensator gain is higher. Even here, balancing is successful also in no-load
operations. Fig. 8 shows a phase current during the load -> no-load transitions, where it can be
observed that a not negligible current, distorted according the proposed strategy main concept, flows
even in no-load conditions. However, owing to the high frequency distortion that is superimposed by
the power semiconductor switching process, it is not easy to evaluate the entity of the additional
disturbance caused to the line. Figures 9, that show the compensating phase current reference during
the load -> no-load transition, bring into evidence that only a small amount of distorted phase current
is needed, up to 0.08 per unit (p.u.) in the worst condition, when the compensating action is more
effective owing to the higher compensation gain. In these Figures, also the dc-link capacitors voltages
difference s and the compensation signal K behaviours can be observed: these two quantities are
proportional because they are the controller input and output, respectively, where only a proportional
action has been imposed. Phase current reference, capacitors voltages difference s and compensation
signal K are significantly different from zero only in transient conditions: when the balance is
achieved, the compensating action has a very low impact on the line currents, as only the real
converter asymmetries must be compensated.

0 0.5 1 1.5 2
2150
2200
2250
2300
2350
2400
2450
2500
2550
Time [s]

0 0.5 1 1.5 2
2150
2200
2250
2300
2350
2400
2450
2500
2550
Time[s]

Fig. 7 Capacitor voltages during system start-up, no-load -> load, load -> no-load transitions
(balancing method is applied after the pre-charge)
Left: high compensator gain
Right: low compensator gain
7

1.35 1.4 1.45 1.5 1.55
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
PHASE CURRENT [A]
Time [s]

1.35 1.4 1.45 1.5 1.55
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
PHASE CURRENT [A]
Time [s]

Fig. 8 Phase current during load -> no-load transition
Right: low compensator gain

1.35 1.4 1.45 1.5 1.55 1.6
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
unbalance
compensation K
phase curr. ref.
Time [s]
[p.u.]

1.35 1.4 1.45 1.5 1.55 1.6
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
unbalance
compensation K
phase curr. ref.
Time [s]
[p.u.]

Fig. 9 Percent capacitors voltages difference s, compensation signal K and phase current reference
during load -> no-load transition
Right: low compensator gain (s and K coincide)

Finally, Figs. 10 show some experimental results that refer to a reduced scale prototype system
(nominal dc-link voltage equal to 680 V, dc-link capacitance values equal to 3 mF) during the start-up
transient and the subsequent no-load operations. Even in this case, dc-link capacitor voltages exhibit a
correct voltage sharing owing to the action of the new devised method.

8

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
310
315
320
325
330
335
340
345
350
355
Time [s]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
-4
-3
-2
-1
0
1
2
DC-LINK VOLTAGES DIFFERENCE [V]
Time [s]

Fig. 10 Experimental results during start-up transient
Left: dc-link capacitor voltages difference
Right: dc-link capacitor voltages and related reference

6. Conclusions
When a real Neutral-Point-Clamped converter system is developed, the Neutral Point voltage exhibits
an unstable behaviour that must be avoided in all the operating conditions. A new control strategy has
been proposed to compensate dc-link capacitors voltages fluctuations in a NPC active rectifier, that
permits to achieve a correct capacitors voltages sharing also in no-load conditions, when conventional
balancing methods fail. Analytical, simulation and experimental results, derived from a reduced scale
prototype, confirm the validity of the proposed approach, that can be extended also to NPC inverters.
Voltages balancing is obtained at the expenses of the line currents quality, that is slightly made worse
by the introduced harmonic distortion. However, additional phase currents harmonics are almost
always negligible, except than in transients operations, where other conventional balancing methods
can be simultaneously applied, thus reducing the overall line impact of the new devised strategy. It is
worth underlining that in no-load conditions, where the proposed strategy is the only effective one, the
compensating action needs distorted currents with almost null amplitudes, as only the real converter
asymmetries must be compensated.

7. References

[1]. A. Nabae, I. Takahashi, H. Akagi. A neutral-point clamped PWM inverter. IEEE Trans. on I.A., Vol. IA-
17, No. 5, 1981, pp. 518-523.
[2]. C. Bacigalupo, M. Marchesoni, P. Segarich, E. Soressi. A synchronous motor drive with great speed
accuracy and high dynamic range for rolling mill applications. Proceedings of the 9th European Conf. on
Power Electronics and Applications (EPE 2001), Graz, Austria, August 27-29, 2001.
[3]. M. Fracchia, T. Ghiara, M. Marchesoni, M. Mazzucchelli. Optimized modulation techniques for the
generalized n-level converter. PESC92 Conference Record, Toledo, Spain, June/July 1992, pp.1205-1213.
[4]. M. Koyama, T. Fujii, R. Uchida, T. Kawabata. Space voltage vector-based new PWM method for large
capacity three-level GTO inverter. Proceedings of the IECON Conf., San Diego, California, USA,
November 9-13, 1992, pp. 271-276.
[5]. S. Ogasawara, H. Akagi. Analysis of variation of neutral point potential in neutral-point-clamped voltage
source PWM inverters. IEEE-IAS Annual Meeting Conference Record, 1993, pp. 965-970.
[6]. N. Celanovich, D. Boroyevich. A comprehensive study of neutral-point voltage balancing problem in
three-level neutral-point-clamped voltage source PWM inverters. IEEE Trans. on Power Electronics, vol.
15, pp.242-249, March 2000.
9

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