TX/RX with interrupts from clock_pt1

//*************************************************************************** *** // CC430F513x Demo - USCI_A0, UART 9600 Full-Duplex Transceiver, 32K ACLK // // Description: USCI_A0 communicates continuously as fast as possible // full-duplex with another device. Normal mode is LPM3, with activity only // during RX and TX ISR's. The TX ISR indicates the UART is ready to send // another character. The RX ISR indicates the UART has received a character. // At 9600 baud, a full character is tranceived ~1ms. // The levels on P1.4/5 are TX'ed. RX'ed value is displayed on P1.0/1. // ACLK = BRCLK = LFXT1 = 32768, MCLK = SMCLK = DCO~ 1048k // Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = 3.41 (0003h 4Ah) // // // CC430F5137 CC430F5137 // --------------------------------// /|\ | XIN|/|\ | XIN|// | | | 32KHz | | | 32KHz // --|RST XOUT|--|RST XOUT|// | | | | // | | | | // | | | | // ->|P1.4 | | P1.0|-> LED // ->|P1.5 | | P1.1|-> LED // LED <-|P1.0 | | P1.4|<// LED <-|P1.1 | | P1.5|<// | UCA0TXD/P2.7|--------->|P2.6/UCA0RXD | // | | 9600 | | // | UCA0RXD/P2.6|<---------|P2.7/UCA0TXD | // // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //*************************************************************************** *** #include "cc430x513x.h" void main(void) { WDTCTL = WDTPW+WDTHOLD; P5SEL |= 0x03; do { UCSCTL7 &= ~(XT1LFOFFG + DCOFFG); SFRIFG1 &= ~OFIFG; __delay_cycles(100000); // Clear XT2,XT1,DCO fault flags // Clear fault flags // Delay for Osc to stabilize

// Stop watchdog timer // Enable XT1 pins

}while (SFRIFG1&OFIFG); P1OUT = 0x000; P1DIR |= BIT0+BIT1; PMAPPWD = 0x02D52; mapping regs P2MAP6 = PM_UCA0RXD; P2MAP7 = PM_UCA0TXD; PMAPPWD = 0; P2DIR |= BIT7; P2SEL |= BIT6 + BIT7; function UCA0CTL1 |= UCSWRST; UCA0CTL1 |= UCSSEL_1; UCA0BR0 = 0x03; UCA0BR1 = 0x00; UCA0MCTL = 0x06; UCA0CTL1 &= ~UCSWRST; machine** UCA0IE |= UCTXIE + UCRXIE; __bis_SR_register(LPM3_bits + GIE); enabled __no_operation(); } #pragma vector=USCI_A0_VECTOR __interrupt void USCI_A0_ISR(void) { unsigned char tx_char; switch(__even_in_range(UCA0IV,4)) case 0: break; case 2: P1OUT = UCA0RXBUF; break; case 4: __delay_cycles(5000); bytes tx_char = P1IN; tx_char = tx_char >> 4; UCA0TXBUF = tx_char; break; default: break; } } {

// Test oscillator fault flag // P1.0/1 setup for LED output // // Get write-access to port // Map UCA0RXD output to P2.6 // Map UCA0TXD output to P2.7 // Lock port mapping registers // Set P2.7 as TX output // Select P2.6 & P2.7 to UART // // // // // // **Put state machine in reset** CLK = ACLK 32k/9600 - 3.41 Modulation **Initialize USCI state

// Enable USCI_A0 TX/RX interrupt // Enter LPM3 w/ interrupts // For debugger

// Vector 0 - no interrupt // Vector 2 - RXIFG // RXBUF1 to TXBUF1 // Vector 4 - TXIFG // Add small gap between TX'ed

// Transmit character

TX/RX with interrupts from clock_pt2

//*************************************************************************** *** // CC430F513x Demo - USCI_A0, SPI 3-Wire Master Incremented Data // // Description: SPI master talks to SPI slave using 3-wire mode. Incrementing // data is sent by the master starting at 0x01. Received data is expected to // be same as the previous transmission. USCI RX ISR is used to handle // communication with the CPU, normally in LPM0. If high, P1.0 indicates // valid data reception. Because all execution after LPM0 is in ISRs, // initialization waits for DCO to stabilize against ACLK. // ACLK = ~32.768kHz, MCLK = SMCLK = DCO ~ 1048kHz. BRCLK = SMCLK/2 // // Use with SPI Slave Data Echo code example. If slave is in debug mode, P1.2 // slave reset signal conflicts with slave's JTAG; to work around, use IAR's // "Release JTAG on Go" on slave device. If breakpoints are set in // slave RX ISR, master must stopped also to avoid overrunning slave // RXBUF. // // CC430F5137 // ----------------// /|\| | // | | | // --|RST P1.0|-> LED // | | // | P2.0|-> Data Out (UCA0SIMO) // | | // | P2.2|<- Data In (UCA0SOMI) // | | // Slave reset <-|P1.2 P2.4|-> Serial Clock Out (UCA0CLK) // // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //*************************************************************************** *** #include "cc430x513x.h" unsigned char MST_Data,SLV_Data; void main(void) { WDTCTL = WDTPW+WDTHOLD; PMAPPWD = 0x02D52; mapping regs P2MAP0 = PM_UCA0SIMO; P2MAP2 = PM_UCA0SOMI; P2MAP4 = PM_UCA0CLK; PMAPPWD = 0;

// Stop watchdog timer // Get write-access to port // // // // Map UCA0SIMO output to P2.0 Map UCA0SOMI output to P2.2 Map UCA0CLK output to P2.4 Lock port mapping registers

P1OUT |= BIT2; P1DIR |= BIT2 + BIT0; direction P2DIR |= BIT0 + BIT2 + BIT4; pins P2SEL |= BIT0 + BIT2 + BIT4; purposes. UCA0CTL1 |= UCSWRST; UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB; UCA0CTL1 |= UCSSEL_2; UCA0BR0 = 0x02; UCA0BR1 = 0; UCA0MCTL = 0; UCA0CTL1 &= ~UCSWRST; machine** UCA0IE |= UCRXIE; P1OUT &= ~0x02; initialized, P1OUT |= 0x02; __delay_cycles(100); MST_Data = 0x01; SLV_Data = 0x00; while (!(UCA0IFG&UCTXIFG)); UCA0TXBUF = MST_Data; __bis_SR_register(LPM0_bits + GIE); } #pragma vector=USCI_A0_VECTOR __interrupt void USCI_A0_ISR(void) { switch(__even_in_range(UCA0IV,4)) { case 0: break; case 2: while (!(UCA0IFG&UCTXIFG)); if (UCA0RXBUF==SLV_Data) P1OUT |= 0x01; else P1OUT &= ~0x01; MST_Data++; SLV_Data++; UCA0TXBUF = MST_Data; to __delay_cycles(40);

// Set P1.0 for LED // Set P1.2 for slave reset // Set P1.0, P1.2 to output // ACLK, MCLK, SMCLK set out to // P2.0,2,4 for debugging // // // // // // // // **Put state machine in reset** 3-pin, 8-bit SPI master Clock polarity high, MSB SMCLK /2 No modulation **Initialize USCI state

// Enable USCI_A0 RX interrupt // Now with SPI signals // reset slave // Wait for slave to initialize // Initialize data values // // USCI_A0 TX buffer ready? // Transmit first character // CPU off, enable interrupts

// Vector 0 - no interrupt // Vector 2 - RXIFG // USCI_A0 TX buffer ready? // Test for correct character RX'd // If correct, light LED // If incorrect, clear LED // Increment data // Send next value // Add time between transmissions

information break; case 4: break; default: break; } }

// make sure slave can process // Vector 4 - TXIFG

TX Receive
//*************************************************************************** *** // CC430F513x Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK // // Description: Echo a received character, RX ISR used. Normal mode is LPM0. // USCI_A0 RX interrupt triggers TX Echo. // Baud rate divider with 1048576hz = 1048576/115200 = ~9.1 (009h|01h) // ACLK = REFO = ~32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // See User Guide for baud rate divider table // // CC430F5137 // ----------------// /|\| | // | | | // --|RST | // | | // | P2.7/UCA0TXD|------------> // | | 115200 - 8N1 // | P2.6/UCA0RXD|<-----------// // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //*************************************************************************** *** #include "cc430x513x.h" void main(void)

WDTCTL = WDTPW + WDTHOLD;

// Stop WDT // Get write-access to port // Map UCA0RXD output to P2.6 // Map UCA0TXD output to P2.7 // Lock port mapping registers // Set P2.7 as TX output // Select P2.6 & P2.7 to UART // // // // // // **Put state machine in reset** SMCLK 1MHz 115200 (see User's Guide) 1MHz 115200 Modulation UCBRSx=1, UCBRFx=0 **Initialize USCI state

PMAPPWD = 0x02D52; mapping regs P2MAP6 = PM_UCA0RXD; P2MAP7 = PM_UCA0TXD; PMAPPWD = 0; P2DIR |= BIT7; P2SEL |= BIT6 + BIT7; function UCA0CTL1 |= UCSWRST; UCA0CTL1 |= UCSSEL_2; UCA0BR0 = 9; UCA0BR1 = 0; UCA0MCTL |= UCBRS_1 + UCBRF_0; UCA0CTL1 &= ~UCSWRST; machine** UCA0IE |= UCRXIE; __bis_SR_register(LPM0_bits + GIE); __no_operation(); }

// Enable USCI_A0 RX interrupt // Enter LPM0, interrupts enabled // For debugger

// Echo back RXed character, confirm TX buffer is ready first #pragma vector=USCI_A0_VECTOR __interrupt void USCI_A0_ISR(void) { switch(__even_in_range(UCA0IV,4)) { case 0:break; // Vector 0 - no interrupt case 2: // Vector 2 - RXIFG while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready? UCA0TXBUF = UCA0RXBUF; // TX -> RXed character break; case 4:break; // Vector 4 - TXIFG default: break; } }

Transmit RX

//*************************************************************************** *** // CC430F513x Demo - USCI_A0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz ACLK // // Description: Echo a received character, RX ISR used. Normal mode is LPM3, // USCI_A0 RX interrupt triggers TX Echo. // ACLK = REFO = 32768Hz, MCLK = SMCLK = DCO ~1.045MHz // Baud rate divider with 32768Hz XTAL @9600 = 32768Hz/9600 = 3.41 // See User Guide for baud rate divider table // // CC430F5137 // ----------------// /|\| | // | | | // --|RST | // | | // | P2.7/UCA0TXD|------------> // | | 9600 - 8N1 // | P2.6/UCA0RXD|<-----------// // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //*************************************************************************** *** #include "cc430x513x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; PMAPPWD = 0x02D52; mapping regs P2MAP6 = PM_UCA0RXD; P2MAP7 = PM_UCA0TXD; PMAPPWD = 0; P2DIR |= BIT7; P2SEL |= BIT6 + BIT7; function UCA0CTL1 |= UCSWRST; UCA0CTL1 |= UCSSEL_1; UCA0BR0 = 0x03; Guide) UCA0BR1 = 0x00; UCA0MCTL = UCBRS_3+UCBRF_0; UCA0CTL1 &= ~UCSWRST; machine** UCA0IE |= UCRXIE; __bis_SR_register(LPM3_bits + GIE); __no_operation();

// Stop WDT // Get write-access to port // Map UCA0RXD output to P2.6 // Map UCA0TXD output to P2.7 // Lock port mapping registers // Set P2.7 as TX output // Select P2.6 & P2.7 to UART // **Put state machine in reset** // CLK = ACLK // 32kHz/9600=3.41 (see User's // // Modulation UCBRSx=3, UCBRFx=0 // **Initialize USCI state // Enable USCI_A0 RX interrupt // Enter LPM3, interrupts enabled // For debugger

// Echo back RXed character, confirm TX buffer is ready first #pragma vector=USCI_A0_VECTOR __interrupt void USCI_A0_ISR(void) { switch(__even_in_range(UCA0IV,4)) { case 0:break; // Vector 0 - no interrupt case 2: // Vector 2 - RXIFG while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready? UCA0TXBUF = UCA0RXBUF; // TX -> RXed character break; case 4:break; // Vector 4 - TXIFG default: break; } }