October 18, 2010

IRS2092
PROTECTED DIGITAL AUDIO AMPLIFIER Features
Integrated analog input Class D audio amplifier driver in a small 16 pin package Floating inputs enable easy half bridge implementation Programmable bidirectional over-current protection with self-reset function Programmable preset deadtime for improved THD performances Start and stop click noise reduction High noise immunity 100 V ratings deliver up to 500 W in output power Operates up to 800 kHz RoHS compliant

Product Summary
VOFFSET (max) Gate driver Io+ Io 100 V 1.0 A 1.2 A 25/40/65/105 ns 500 ns <20 mV ~800 kHz >60 dB 0.01 % 200 Vrms

Selectable Deadtime OC protection delay (max) DC offset PWM frequency Error amplifier open loop gain THD+N* (1kHz, 50W, 4) Residual Noise* (AES-17 Filter)

* measured with recommended circuit

Typical Applications
Home theater systems Mini component stereo systems Powered speaker systems General purpose audio power amplifiers

Package Options

SOIC16N

PDIP16

Typical Connection Diagram

IRS2092
1

+B
16 15 14 13 12 11 10 9

VAA GND INCOMP CSD VSS VREF OCSET

CSH VB HO VS VCC LO COM DT

INPUT

2 3 4 5 6 7 8

Speaker

Vcc 12V -B

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Table of Contents
Description Simplified Block Diagram Typical Application Diagram Qualification Information Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Waveform Definitions Functional Block Diagram Input/Output Pin Equivalent Circuit Diagram Lead Definitions Lead Assignments Package Details Tape and Reel Details Part Marking Information Ordering Information

Page
3 4 4 5 6 7 8 10 11 12 13 13 14 16 17 18

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Description
The IRS2092 is a high voltage, high performance Class D audio amplifier driver with PWM modulator and protection. In conjunction with two external MOSFET and a few external components, a complete Class D audio amplifier with protection can be realized. International Rectifiers proprietary noise isolation technology allows high current gate drive stage and high speed low noise error amplifier reside on a single small silicon die. Open elements of PWM modulator section allow flexible PWM topology implementation.

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Simplified Block Diagram

Typical Application Diagram

Refer to IRAUDAMP5 reference design for details.

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1 k

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Qualification Information
Qualification Level Industrial (per JEDEC JESD 47E) Comments: This IC has passed JEDECs Industrial qualification. IRs Consumer qualification level is granted by extension of the higher Industrial level. MSL2 SOIC16N (per IPC/JEDEC J-STD-020C) DIP16 Not applicable Class B (per JEDEC standard JESD22-A114D) Class 2 (per EIA/JEDEC standard EIA/JESD22-A115-A) Class IV (per JEDEC standard JESD22-C101C) Class I, Level A (per JESD78A) Yes

Moisture Sensitivity Level Machine Model ESD Human Body Model Charged Device Model IC Latch-Up Test RoHS Compliant

Qualification standards can be found at International Rectifiers web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information.

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Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCSH VCC VLO VAA VSS VGND IINVCSD VCOMP VDT VOCSET IAAZ ISSZ ICCZ IBSZ IOREF dVS/dt dVSS/dt Pd RthJA TJ TS TL Note1: Note2: Note3: Definition High side floating supply voltage High side floating supply voltage (Note2) High side floating output voltage CSH pin input voltage Low side fixed supply voltage (Note2) Low side output voltage Floating input positive supply voltage (Note2) Floating input negative supply voltage (Note2) Floating input supply ground voltage Inverting input current (Note1) SD pin input voltage COMP pin input voltage DT pin input voltage OCSET pin input voltage Floating input positive supply zener clamp current (Note2) Floating input negative supply zener clamp current (Note2) Low side supply zener clamp current (Note3) Floating supply zener clamp current (Note3) Reference output current Allowable Vs voltage slew rate Allowable Vss voltage slew rate (Note3) SOIC16N Maximum power dissipation @ TA +25C DIP16 SOIC16N Thermal resistance, Junction to ambient DIP16 Junction Temperature Storage Temperature Lead temperature (soldering, 10 seconds) Min -0.3 VB -20 VS -0.3 VS -0.3 -0.3 -0.3 (See IAAZ) -1 (See ISSZ) VSS -0.3 (See ISSZ) --VSS -0.3 VSS -0.3 -0.3 -0.3 -------------------------55 --Max 220 VB +0.3 VB +0.3 VB +0.3 20 Vcc+0.3 210 GND +0.3 VAA +0.3 (See IAAZ) 3 VAA +0.3 VAA +0.3 VCC +0.3 VCC+0.3 20 20 10 10 5 50 50 1.0 1.6 115 75 150 150 300 mA V Units

mA

V/ns V/ms W C/W C C C

IN- contains clamping diode to GND. VDD IN+, GND -VSS, VCC-COM and VB-VS contain internal shunt zener diodes. Please note that the voltage ratings of these can be limited by the clamping current. For the rising and falling edges of step signal of 10 V. VSS=15 V to 200 V.

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Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions below. The Vs and COM offset ratings are tested with supplies biased at VAA-VSS=10 V, VCC=12 V and VB-VS=12 V. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead.

Symbol VB VS IAAZ ISSZ VSS VHO VCC VLO VGND VINVCSD VCOMP CCOMP VDT IOREF VOCSET VCSH dVss/dt
IPW

fSW TA

Definition High side floating supply absolute voltage High side floating supply offset voltage Floating input positive supply zener clamp current Floating input negative supply zener clamp current Floating input supply absolute voltage High side floating output voltage Low side fixed supply voltage Low side output voltage GND pin input voltage Inverting input voltage CSD pin input voltage COMP pin input voltage COMP pin phase compensation capacitor to GND DT pin input voltage Reference output current to COM (Note 2) OCSET pin input voltage CSH pin input voltage Allowable Vss voltage slew rate upon power-up (Note4) Input pulse width Switching Frequency Ambient Temperature

Min. VS +10
(Note 1)

1 1 0 Vs 10 0 VSS (Note 3) VGND -0.5 VSS VSS 1 0 0.3 0.5 Vs 10 (Note 5) -40

Max. VS +18 200 11 11 200 VB 18 VCC VAA (Note 3) VGND +0.5 VAA VAA VCC 0.8 5 VB 50 800 125

Units V mA

nF V mA V V/ms ns kHz C

Note 1: Logic operational for Vs equal to 5 V to +200 V. Logic state held for Vs equal to 5 V to VBS. Note 2: Nominal voltage for VREF is 5.1 V. IOREF of 0.3 0.8 mA dictates total external resistor value on VREF to be 6.3 k to 16.7 k. Note 3: GND input voltage is limited by IAAZ and ISSZ. Note 4: VSS ramps up from 0 V to 200 V. Note 5: Output logic status may not respond correctly if input pulse width is smaller than the minimum pulse width.

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Electrical Characteristics
VCC,VBS= 12 V, VSS=VS=COM=0 V, VAA=10 V, CL=1 nF and TA=25 C unless otherwise specified. Definition
Vcc supply UVLO positive threshold Vcc supply UVLO negative threshold UVCC hysteresis Low side quiescent current Low side zener diode clamp voltage High side well UVLO positive threshold High side well UVLO negative threshold UVBS hysteresis High side quiescent current High to Low side leakage current High side zener diode clamp voltage VA+, VA- floating supply UVLO positive threshold from VSS VA+, VA- floating supply UVLO negative threshold from VSS UVAA hysteresis Floating Input positive quiescent supply current Floating Input positive quiescent supply current Floating Input positive quiescent supply current Floating input side to Low side leakage current VAA floating supply zener diode clamp voltage, positive, with respect to GND VSS floating supply zener diode clamp voltage, negative, with respect to GND Input offset voltage Input bias current Small signal bandwidth OTA Output voltage OTA transconductance OTA gain OTA input noise voltage Slew rate Common-mode rejection ratio Supply voltage rejection ratio PWM comparator threshold in COMP COMP pin star-up local oscillation

Symbol Low Side Supply

UVCC+ UVCCUVCCHYS IQCC VCLAMPL UVBS+ UVBSUVBSHYS IQBS ILKH VCLAMPH UVAA+ UVAAUVAAHYS IQAA0 IQAA1 IQAA2 ILKM VCLAMPM+ VCLAMPM-

Min
8.4 8.2 19.6 8.0 7.8 19.6 8.2 7.7 6.0 -8.0

Typ
8.9 8.7 0.2 20.4 8.5 8.3 0.2 20.4 8.7 8.2 0.5 0.5 8 8 7.0 -7.0

Max
9.4 9.2 3 21.6 9.0 8.8 1 50 21.6 9.2 8.7 2 11 11 50 8.0

Units

Test Conditions

V mA V VDT=VCC ICC=5 mA

High Side Floating Supply

V mA A V

VB=VS =200 V IBS=5 mA VSS =0 V, GND pin floating VSS =0 V, GND pin floating VSS =0 V, GND pin floating VAA=10 V, VSS =0 V, VCSD =VSS VAA=10 V, VSS =0 V, VCSD =VAA VAA=10 V, VSS =0 V, VCSD =GND VAA=VSS=VGND= 100 V IAA=5 mA, ISS=5 mA, VGND=0 V, VCSD =VSS IAA=5 mA, ISS=5 mA, VGND=0 V, VCSD =VSS

Floating Input Supply

mA

V -6.0

Audio Input (VGND=0, VAA=5V, VSS=-5V)

VOS IBIN BW VCOMP gm GV VNrms SR CMRR PSRR VthPWM fOTA www.irf.com -15 VAA-1 60 0.7 0 9 100 250 5 60 65 (VAA-VSS)/2 1.0 15 40 VSS+1 1.5 mV nA MHz V mS dB mVrms V/us dB V MHz CCOMP=2 nF, Rf=3.3 k VIN-=10 mV BW=20 kHz, Resolution BW=22 Hz Fig.5 CCOMP=1 nF

PWM comparator
VCSD =GND

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frequency

Protection
VREF VthOCL VthOCH Vth1 Vth2 ICSD+ ICSDtSD tOCH tOCL Io+ IoVOL VOH ton toff tr tf DT1 DT2 DT3 DT4 VDT1 VDT2 VDT3 Reference output voltage Low side OC threshold in Vs High side OC threshold in VCSH CSD pin shutdown release threshold CSD pin self reset threshold CSD pin discharge current CSD pin charge current Shutdown propagation delay from VCSD > VSS + VthOCH to Shutdown Propagation delay time from VCSH > VthOCH to Shutdown Propagation delay time from Vs> VthOCL to Shutdown Output high short circuit current (Source) Output low short circuit current (Sink) Low level out put voltage LO COM, HO - VS High level out put voltage VCC LO, VB - HO High and low side turn-on propagation delay High and low side turn-off propagation delay Turn-on rise time Turn-off fall time Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4 DT mode select threshold 2 DT mode select threshold 3 DT mode select threshold 4 4.8 1.1 1.1+ Vs 0.62xVAA 0.26xVAA 70 70 15 25 50 85 0.51xVcc 0.32xVcc 0.21xVcc 5.1 1.2 1.2+ Vs 0.70xVAA 0.30xVAA 100 100 1.0 1.2 360 335 20 15 25 40 65 105 0.57xVcc 0.36xVcc 0.23xVcc 5.4 1.3 1.3+ Vs 0.78xVAA 0.34xVAA 130 130 250 500 500 0.1 V 1.4 50 35 35 ns 55 85 135 0.63xVcc 0.40xVcc 0.25xVcc V VDT1>VDT> VDT2, VDT2>VDT> VDT3, VDT3>VDT> VDT4, VDT>VDT1, VDT = VCC VDT = VCC Io=0 A A A ns Fig.3 Fig.4 Vo=0 V, PW<10 s Vo=12 V, PW<10 s V IOREF =0.5 mA OCSET=1.2 V, Fig.6 Vs=200 V,

VCSD = VSS +5 V VCSD = VSS +5 V

Gate Driver

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Waveform Definitions

Vth1
CSD

90% HO/LO

tSD

Figure 1: Switching Time Waveform Definitions

Figure 2: CSD to Shutdown Waveform Definitions

VS

VthOCL

CSH VS

VthOCH

90% LO

90% HO

tOCL

tOCH

Figure 3: VS > VthOCL to Shutdown Waveform

Figure 4: VCSH > VthOCH to Shutdown Waveform

Figure 5: OTA input noise voltage mesurent circuit

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Functional Block Diagram: IRS2092

FLOATING INPUT CLICK NOISE ELLIMINATION

UV DETECT

CSH VB

VAA

IN-

VAA+VSS 2

HIGH SIDE CS

UV Q

OTA

COMP

HO

GND

PWM MODULATOR HV LEVEL SHIFT UV DETECT

COMP

HV LEVEL SHIFT

FLOATING HIGH SIDE

5V REG UV DETECT

HV LEVEL SHIFT

VS

VCC

VSS

DEAD TIME

CSD
CHARGE/ DISCHARGE SD DT

LO
HV LEVEL SHIFT PROTECTION CONTROL HV LEVEL SHIFT

COM

VREF
LOW SIDE CS

OCSET

DT

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Input/Output Pin Equivalent Circuit Diagrams: IRS2092

VB
ESD Diode 20 V Clamp ESD Diode

HO

VS
200 V

V CC VCC
ESD Diode 20 V Clamp ESD Diode

LO

COM

VAA
ESD Diode

VCC
ESD Diode

COMP or CSD
ESD Diode

DT, VREF or OCSET COM

ESD Diode

VSS

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Lead Definitions: IRS2092
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VAA GND INCOMP CSD VSS VREF OCSET DT COM LO VCC VS HO VB CSH Description Floating input positive supply Floating input supply return Analog inverting input Phase compensation input, comparator input Shutdown timing capacitor Floating input negative supply 5V reference voltage to program OCSET pin Low side over current threshold setting Deadtime program input Low side supply return Low side output Low side supply High side floating supply return High side output High side floating supply High side over current sensing input

Lead Assignments

VAA GND INCOMP CSD VSS VREF OCSET

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

CSH VB HO VS VCC LO COM DT

PDIP16 and SOIC16N

IRS2092

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Package Details: PDIP16

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Package Details: SOIC16N

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Tape and Reel Details: SOIC16N
LOADED TAPE FEED DIRECTION

A A

D F C

NOTE : CONTROLLING DIMENSION IN MM

E G

CARRIER TAPE DIMENSION FOR 16SOICN Metric Imperial Code Min Max Min Max A 7.90 8.10 0.311 0.318 B 3.90 4.10 0.153 0.161 C 15.70 16.30 0.618 0.641 D 7.40 7.60 0.291 0.299 E 6.40 6.60 0.252 0.260 F 10.20 10.40 0.402 0.409 G 1.50 n/a 0.059 n/a H 1.50 1.60 0.059 0.062

D C E B A

H REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 22.40 n/a 0.881 G 18.50 21.10 0.728 0.830 H 16.40 18.40 0.645 0.724

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Part Marking Information

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Ordering Information

Standard Pack Base Part Number Package Type Form PDIP16 IRS2092 SOIC16N Tube/Bulk Tube/Bulk Tape and Reel Quantity 25 45 2500 IRS2092PBF IRS2092SPBF IRS2092STRPBF Complete Part Number

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied.

For technical support, please contact IRs Technical Assistance Center http://www.irf.com/technical-info/
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105

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