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t t n e e r c m 2. System View and Disassembly .... e u S c c Do a iT ial M t . 3. Definition & Location of Connectors/Switches n e id f nComponents ... 4. Definition & Location of Major o C
5. Pin Description of Major Component ...
1.3 Other Functions ..... 39 1.4 Peripheral Components 45 1.5 Power Management ... 47
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5.1 Intel Merom Processor CPU . 76 5.2 VIA VN896 North Bridge .. 81 5.3 VIA VT8237A South Bridge . 85
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7.1 No Power . 96 7.2 No Display .. 101 7.3 Graphics Controller Test Error LCD No Display ...... 104 7.4 External Monitor No Display 106 7.5 Memory Test Error .... 108 7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error .... 110 7.7 Hard Disk Drive Test Error . 112 7.8 ODD Drive Test Error ... 115 7.9 USB Port Test Error .. 117 7.10 Audio Test Error .. 119 7.11 LAN Test Error .... 122 7.12 Mini Express (Wireless) Socket Test Error ... 124 7.13 Express Card Socket Test Error ..... 126
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
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Memory
HDD
ODD Display Clock Generator VGA Control LVDS Transmitter LAN Express Card Audio System
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667 MT/s (667 MHz) and 800 MT/s (800 MHz) FSB support
On-die, 2-MB second level cache with advanced transfer cache architecture shared between the two cores Advance gunning transceiver logic (AGTL +) bus driver technology
frequency points
Enhanced Intel speed step technology to enable real-time dynamic switching between multiple voltage and Source synchronous double-pumped (2) address Source synchronous quad-pumped (4) data Other key feature are:
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Support for DBI (Data Bus Invor ersion) Support for MSI (Message signaled interrupt)
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On-die 1 MB second level cache with advance transfer cache architecture shared between the two cores 478-pin Micro-FCPGA packages VCCA 1.5 V VCCP 1.05 V
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Programmable output frequency Programmable asynchronous 3 V66&PCI frequency Programmable asynchronous PCI-Express frequency Programmable output divider ratios Programmable output skew
Watchdog timer technology to reset system if system malfunctions Programmable watch dog safe frequency
Uses external 14.318 MHz reference input, external crystal load caps are required for frequency tuning
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1 pair of differential feedback pins for input to output synchronization Supports up to 2 DDR DIMMs
Output rise and fall time for DDR outputs: 650 ps 950 ps Duty cycle: 47% - 53%
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High performance UMA north bridge: Integrated VIA C7 and Intel Pentium M north bridge with 800 / 667/
533 / 400 MHz FSB support. PCI express bus controller and UniChrome Pro 3D / 2D graphics & video controllers in a single chip
Advanced 64-bit SDRAM controller supporting DDR2 667/533 and DDR 400/333/266/200 SDRAM Combines with VIA VT8237A/VT8237R plus for 10/100 LAN, ATA133 IDE, LPC, USB 2.0, serial ATA
and high definition audio (VT8237A)
37.5x37.5 mm HSBGA package (Ball grid array with heat spreader) with 952 balls and 1.00 mm ball pitch
CPU interface
Supports 800/667/533/400 MHz FSB VIA C7 and Intel Pentium M processors Supports Intel hyper-threading technology Supports DBI (Dynamic Bus Inversion) Supports trust configuration cycle Deep In-order Command Queue (IOQ)
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Supports DDR2 mode Supports DDR2 667/533 memory Supports mixed 64/128/256/512/1024/2048x8/16 DDR2 SDRAMs
Supports 2 unbuffered double-sided DIMMs and up to 4 GB of physical memory Supports CL 2/3/4/5 for DDR2 667/533
Programmable I/O drive capability for memory address, data and control signals DRAM interface pseudo-synchronous with host CPU for optimal memory performance Concurrent CPU, PCIe, internal graphics controller and V-link access for minimum memory access latency Rank interleave and up to16-bank page interleave (i.e., 16 pages open simultaneously) based on LRU to
effectively reduce memory access latency
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Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while
accessing the current bank)
1st port: A 16-Lane port for high end graphics interface. Configurable lane width, 16/8/4/2/1, through hand-shaking for transfer rate up to 4 GB/sec bi-directional Supports two upstream virtual channels 2nd port: A 1-Lane port for peripheral devices
Supports interconnect power management Supports polarity reversal Supports trust configuration cycle Supports hot plug
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Supports 66 MHz, 4x and 8x transfer modes, V-link interface with 533 MB/sec total bandwidth Half duplex transfers with separate command/strobe for 4x 8-bit mode and full duplex for 8x 4-bit mode Request/data split-transaction
Transaction assurance for V-link host-to-client access eliminates V-link host-client retry cycles Intelligent V-link transaction protocol to minimize data wait-state and throttle transfer latency to avoid data
overflow
Optimized Unified Memory Architecture (UMA) Supports 16/32/64 MB frame buffers size
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Graphics engine clocks up to 333 MHz decoupled from memory clock Internal AGP 8x performance
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BitBLT (Bit Block Transfer) functions including alpha BLTs Color expansion, source color key and destination color key Bresenham line drawing/style line function Transparency mode
3D acceleration features
3D graphics processor
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- 128-bit 3D graphics engine - Dual pixel rendering pipes - Dual texture units
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- Supports ROP2
- Supports various texture formats, including: 16/32 bbp ARGB, 8 bbp palletized (ARGB), YUV 422/420
and compressed texture (DXTC)
- High quality texture filter for Nearest, Linear, bi-linear, tri-linear and anisotropic modes - Flat and gouraud shading - Vertex fog and fog table
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- Z-Bias, LOD-Bias, polygon offset, edge anti-aliasing and alpha blending - Bump mapping and cubic mapping - Hardware back-face culling
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- Pixel rate up to 400 million pixels per second for 2 textures each - Texel bilinear fill rate up to 266 million texels per second - High quality dithering
- Multiplexed DVP0 and DVP1 for LVDS transmitter - Dedicated DVP2 for TV encoder CRT display
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- Supports CRT resolutions up to 2048x1536 at 75 Hz 12-bit DDR/18-bit/24-bit LVDS transmitter interface for LCD panel - 12-bit DDR and clock rate up to 165 MHz
- Built-in digital phase adjuster to fine tune signal timing between clock and data bus
Advanced system power management support
Supports dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0) Supports SMI, SMM and STPCLK mechanisms Supports enhanced Intel Speedstep technology Low-leakage I/O pads
Advanced graphics power management support
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I2C serial bus and DDC monitor communications for CRT plug-and-play configuration
Supports 16-bit, 66 MHz, 4x and 8x transfer modes, Ultra V-link interface with 1 GB/sec maximum bandwidth Full duplex, with separate 8-bit Up and Down data path and command/strobe, in 8x mode
Transaction assurance for V-link host to client access eliminates V-link host-client retry cycles Intelligent V-link transaction protocol to minimize data wait-state, throttle transfer latency to avoid data overflow Highly efficient V-link arbitration with minimum overhead
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Complies with serial ATA specification revision 1.0 Dual Channel master mode PCI On-chip two-channel Serial ATA (S-ATA) PHY for support of up to two S-ATA devices directly S-ATA devices can be configured in multiple RAID configurations supports RAID Level 0, RAID Level 1
and JBOD
S-ATA drive transfer rate is capable of up to 150 MB/s per channel (serial speed of 1.5 Gbit/s) External crystal input for serial ATA port operation Supports defer spin up and port multiplier
High definition (HD) audio controller
High definition audio controller with 192 KHz sample rate, 24-bit per sample and up to 8 channels Microsoft UAA (Universal Audio Architecture) driver support Up to four independent playback streams and audio codecs Multiple recording channels for array microphone Supports jack sensing/retasking
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Eight USB 2.0 ports with integrated PHY One USB 2.0 root hub and four USB 1.1 root hubs USB 2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compliant
USB 1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible
Integrated physical layer transceivers with optional over-current detection status on USB inputs Eighteen level (doublewords) data FIFO with full scatter and gather capability Legacy keyboard and PS/2 mouse support One USB 2.0 debug port
High performance PCI master interface with scatter/gather and bursting capability Standard MII interface to external PHYceiver 1/10/100 MHz full and half duplex operation Independent 2 K byte FIFOs for receive and transmit
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Dual channel hard disk controller supporting up to four enhanced IDE devices
Data transfer rate up to 133 MB/sec to cover PIO mode 4, multi-word DMA mode 2 and UltraDMA-133 interface Dual DMA engines for concurrent dual channel operation Full scatter gather capability
Supports ATAPI compliant devices including DVD devices Supports PCI native and ATA compatibility modes
Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant Complete software driver support
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Compliant with System Management Bus (SMBus) revision 2.0 I2C devices compatible Supports SMBus Address Resolution Protocol (ARP) by using host commands through software Supports slave interface for external SMBus masters to control resume events Supports alert on LAN II through a SMBus-interfaced register
Sophisticated mobile power management
Supports Intel enhanced SpeedstepTM with dedicated pins Supports PCI Express WAKE suspend resume event
Supports CPU clock throttling and clock stop during ACPI C0 / C1 / C2 / C3 states Supports PCI clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control Supports multiple system suspend types: power-on suspends (POS) with flexible CPU/PCI bus reset options,
suspend to DRAM (STR), and suspend to disk (soft-off), all with hardware automatic wake-up
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t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close 32 general purpose input ports and 32 output ports
Multiple internal and external SMI sources for flexible power management models Enhanced integrated Real Time Clock (RTC) with date alarm, month alarm, and century field Thermal alarm on external temperature sensing circuit I/O pad leakage control
Plug and play functions
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Integrated DS12885-style real time clock with extended 256 bytes CMOS RAM and day/month alarm for ACPI Integrated DMA, timer, and interrupt controller
Serial IRQ for docking and non-docking applications Fast reset and gate A20 operation
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Supports dual channel UXGA panel display Supports 2D dither for 18-bit Panel
Supports DVO input mode with 25 to 165 MHz input clock Programmable input clock and strobe select Narrow bus reduces cable size and cost PLL requires no external components
2.5 V core power for low power consumption 48-pin LQFP package (7x7x1.4 mm) Available for lead-free package
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Available in a 20-pin TSSOP, a 20-pin QFN, or 24-pin power PAD HTSSOP (Single) Fully Satisfies the express card implementation guidelines Supports systems with wake function TTL-logic compatible inputs
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1 stereo DAC supports 16/20/24-bit PCM format with 44.1/48/96/192 KHz sample rate
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External PCBEEP input is applicable, and internal BEEP generator is integrated Power-off CD mode supported (Only in ALC268 & ALC268-LF) Power management and enhanced power saving features Power support: digital: 3.3 V; analog: 3.8 V/5.0 V Selectable 2.5 V/3.75 V VREFOUT
Two jack detection pins (Each designed to detect 4 jacks) Supports 44.1/48/96/192 KHz S/PDIF output Supports 44.1/48/96 KHz S/PDIF input
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Software optional with LPC interface Primary programmable I/O address communication port in LPC mode
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Support four timer signal with three pre-scalars Timer 1 and 2 shard the same pre-scalar and are free-running only
event counter and pulse width measurement PWM
Timer X and Y have individual pre-scalar and support up to four control modes, free. Running, pulse output,
PWM 0 and 1 are 8-bits and programmable frequency from 62 Hz to 7.5 KHz PWM 2 and 3 are 16-bits and programmable frequency from 6 Hz to 3 MHz
Fan Tachometer
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Support 104 useful GPIO pins totally and bitaddressable to facility firmware coding
Flash
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Uniform 4 KByte sectors Uniform 64 KByte overlay blocks Chip-erase for PP mode only
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Endurance: 100,000 cycles (typical) Greater than 100 years data retention
Low power consumption
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Low Pin Count (LPC) interface mode forin-system operation Parallel Programming (PP) mode for fast production programming
LPC interface mode
5-signal LPC bus interface supporting byte read and write 33 MHz clock frequency operation
WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block Block locking registers for individual block write-lock and lock-down protection JEDEC standard SDP command set
Data# polling and toggle bit for end-of-write detection 5 GPI pins for system design flexibility 4 ID pins for multi-chip selection
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Meet all applicable IEEE 802.3, 10Base -T and 100Base -Tx standards On chip wave shaping no external filters required Adaptive equalizer
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Mute off/on Panel off/on Suspend to DRAM/HDD
Volume down Audio volume down Volume up Audio volume up LCD/external CRT switching Rotate display mode in LCD only, CRT only and simultaneously display Brightness down Decreases the LCD brightness Brightness up Increases the LCD brightness
Toggle mute on/off Toggle panel on/off Force the computer into either suspend to HDD or suspend to DRAM mode depending on BIOS setup
At ACPI mode, windows power management control panel set power button behavior. You could set "standby", "power off or "hibernate (Must enable hibernate function in power management) to power button function.
Continue pushing power button over 4 seconds will force system off at ACPI mode
System automatically provides power saving by monitoring cover switch. It will save battery power and prolong the usage time when user closes the notebook cover
At ACPI mode there are three functions to be chosen at windows XP power management control panel
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System has six status LED indicators to display system activity, which include six above keyboard
From left to right that indicates WLAN, power status, battery charge status, caps lock status, num lock status, HDD/ODD status
On: System power on Off: Suspend to RAM power management mode (Flash rate: 1 Hz)
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Green: Battery was fully charged (AC mode) Orange: Battery was under charging (AC mode) Red (Flash): Battery low (Under 10%, battery mode, flash rate: 1 Hz)
CAPS lock status
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Battery warning: Capacity below 10%, battery capacity LED flashes per second, system beeps per 2 seconds
After battery warning state, and battery capacity is below 5%, system will generate beep sound for twice per second
When the battery voltage level reaches 7.4 volts, system will shut down automatically in order to extend the battery packs' life
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There is a standard CR2032 3 V 220 mAh lithium coin battery to supply RTC power. When AC in or system main battery inside, CMOS battery consumes no power to save coin batterys life cycle
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Support 2.5" 60 GB/80 GB/100 GB/120 GB HDD (9.5 mm) 5400/7200 rpm, PATA, SATA I/F
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In this mode, each device is running with the maximal speed. CPU clock is up to its maximum
Doze Mode
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling.
This can save battery power without loosing much computing capability. The CPU power consumption and temperature is lower in this mode Standby Mode
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For more power saving, it turns of the peripheral components. In this mode, the following is the status of each
device
The most chipset of the system is entering power down mode for more power saving. In this mode, the
following is the status of each device
- CPU: Off
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All devices are stopped clock and power-down. System status is saved in HDD. All system status will be
restored when powered on again
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r q
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p n o q r]
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o n
2 mm
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Tooling Auto Screwdriver Tor. 2.0-2.5 kg/cm2 Bit Size #0
Bit Size #0
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NOTEBOOK
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Modular Components LCD Assembly Components Base Unit Components
2.3.1 Battery Pack 2.3.2 Keyboard 2.3.3 CPU 2.3.4 DDR2-SDRAM 2.3.5 HDD Module 2.3.6 ODD Drive 2.3.7 LCD ASSY 2.3.8 LCD Panel 2.3.9 Inverter Board 2.3.10 System Board 2.3.11 Modem Card
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Reassembly
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n n
Figure 2-1 Remove the battery pack
1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound.
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o n
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Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place. 2. Replace the keyboard cover and secure with one screw. 3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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Figure 2-4 Remove the keyboard
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Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU. 2. Connect the fans power cord to the system board, replace the fan and heatsink, then secure with seven screws. 3. Replace the CPU cover and secure with four screws. 4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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Figure 2-7 Remove the CPU
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Figure 2-8 Remove the SO-DIMM
Reassembly 1. To install the DDR2, match the DDR2's notched part with the socket's projected part and firmly insert the SODIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR2 into position 2. Replace the CPU cover and secure with four screws. 3. Replace the battery pack. (See section 2.3.1 Reassembly)
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Figure 2-9 Remove HDD module
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Reassembly
1. Attach the bracket to hard disk drive and secure with four screws. 2. Slide the HDD module into the compartment and secure with one screw. 3. Replace the CPU cover and secure with four screws. 4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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Figure 2-10 Remove hard disk drive
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Figure 2-11 Remove the ODD drive
Reassembly 1. Push the ODD drive into the compartment and secure with one screw. 2. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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Reassembly
1. Attach the LCD assembly to the base unit and secure with six screws. 2. Reconnect the LCD cable and replace two hinge covers. 3. Replace the CPU cover and secure with four screws. (Refer to section 2.3.3) 4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)
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Figure 2-14 Free the LCD assembly
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Reassembly
1. Reconnect the LCD cable to the LCD panel. 2. Attach the LCD panels bracket back to LCD panel and secure with four screws. 3. Replace the LCD panel into LCD housing, fasten the LCD panel by six screws. 4. Replace the LCD cover and secure with two screws. 5. Replace the LCD assembly, keyboard, battery pack. (See sections 2.3.7, 2.3.2 and 2.3.1Reassembly)
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Reassembly
1. Fit the inverter board back into place and secure with three screws. 2. Replace the LCD Panel, LCD assembly, keyboard and battery pack. (Refer to sections 2.3.8, 2.3.7, 2.3.2 and 2.3.1 Reassembly)
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Figure 2-19 Remove three screws
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Reassembly
1. Replace the system board back into the housing, secure with two screws and reconnect two speakers cables. 2. Replace the top cover into the housing. 3. Secure with fifteen screws and two hex nuts fasten the housing. 4. Replace the LCD assembly, DDR2, ODD, HDD, CPU, keyboard and battery pack. (Refer to previous section reassembly)
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Figure 2-22 Free the system board
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Figure 2-23 Remove the modem card
Reassembly 1. Replace the modem card back into the system board and secure with two screws, then reconnect the cable. 2. Replace the system board, the LCD assembly, ODD, HDD, DDR2, CPU, keyboard and battery pack. (Refer to previous section reassembly)
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PJ501 J506
J503
J501
J504
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J512 J514 J510 J513,J515 J518 J516 J519 PJ502 J511
PJ501 : Power Jack PJ502 : Battery Connector J501 : CRT Connector J502 : RJ11 & RJ45 Connector J503, J506 : USB Port J504 : USB Port*2 J505 : MDC Jump Wire Connector J507 : MDC Connector J510 : SATA HDD Connector J512 : HP Jack J514 : External MIC Jack J513, J515 : DDR2 SO-DIMM Socket J516 : Mini Express (Wireless) Connector J518, J519 : Stereo Speaker Connector
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J4
SW6
SW7
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SW5 J1 SW2 SW3 SW4 J3 J2
J1 : LCD Inverter Connector J2 : Internal Keyboard Connector J3 : Touch-Pad Connector J4 : Express Card Socket
SW2 : Mail Button SW3 : Internet Button SW4 : P1 Button SW5 : Power Button SW6 : Touch-Pad Left Button SW7 : Touch-Pad Right Button
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U507
U513
U512 U506
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U514
U506 : LAN Controller VT6103L U507 : Intel Merom Socket U512 : Clock Generator ICS953009 U513 : VIA VN896 North Bridge U514 : VIA VT8237A South Bridge
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U21
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U10
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A20M#
ADS#
I/O
ADSTB[1:0]#
I/O
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BPM[2:1]# BPM[3,0]# I/O BPRI# I BR0# I/O BSEL[2:0] O COMP[3:0] Analog
BCLK[1:0]
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DBR#
DBSY#
I/O
DEFER#
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DPRSTP# DPSLP# I I DPWR# I DRDY# I/O DSTBN[3:0]# I/O
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FERR#/PBE#
GTLREF
HIT# HITM#
I/O I/O
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INIT# I LINT[1:0] I
IERR#
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O I I/O
PSI#
PWRGOOD
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RS[2:0]# RSVD SLP# SMI#
REQ[4:0]
I/O
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VID[6:0]
I I O
Other Other O
TMS TRDY#
I I
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Vss_sense O
I I I I
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IO
HD[63:00]# HDBI[3:0]#
IO IO
HDSTB[3:0]P# HDSTB[3:0]N#
IO
IO IO IO IO
HHITM# HLOCK#
IO IO
Hit. Indicates that a caching agent holds an unmodified version of the requested line. Also driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified. Asserted by the CPU to indicate that the address is modified in the L1 cache and needs to be written back. Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the negation of HLOCK# must be atomic.
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HRS[2:0]# O HDPWR# O HBREQ0# HBPRI# IO O HBNR# IO HDEFER# O CPURST# O
HTRDY#
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IO IO I I I O O O
HCLK+
I I
O O I I
V-Link Clock. This signal receives the 66 MHz clock used to generate the internal clocks required by V-Link interface between the North Bridge and South Bridge. Host Clock. This signal receives the host CPU clock (100/133/166/200 MHz). This clock is used by all VN896 logic that is in the host CPU domain. Host Clock Complement. Used for Quad Data Transfer on host CPU bus. PCI Express Differential Clock. These signals receive the 100 MHz clock used by the internal PCI Express logic. Multiplied up to 2.5 GHz onchip for use by the integrated PCI Express PHY to transmit/receive data. Memory (SDRAM) Clock. Output from internal clock generator to external memory interface clock buffer (if required for fanout) Memory (SDRAM) Clock Complement. Memory (SDRAM) Clock Feedback. Input from MCLKO. Dot Clock (Pixel Clock) In. Used for external EMI reduction circuit if used. Connect to GND if external EMI reduction circuit not implemented. Dot Clock (Pixel Clock) Out. Used for external EMI reduction circuit if used. NC if external EMI reduction circuit not implemented.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
O MCS[3:0]# O MDQM[7:0]# MCKE[3:0] O MDQS[7:0]+/IO O MEMDET I
Description
MODT[3:0]
AI IO IO
Reference Resistor. Tie to GND through an external resistor to control the RAMDAC full-scale current value. DVPSPCLK is typically used for I2C communications DVPSPD is typically used for I2C communications Serial Port Clock and Data. Clock for serial data transfer. Data signals used for serial data transfer. It is typically used for CRT display DDC communications.
DISPCLKO
82
O O O O O O O I O
Display Detect. For DVP1 in 12-bit mode. Clock Output. For DVP1 in 12-bit mode.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
VCCA33DAC[2:1] GNDADAC GNDAPEX[2:0] GNDAPEXCK P P P P VCCA33PEX[2:0] VCCA33PEXCK P P
Signal Name Type P VTT
Ground for DAC. Connect to main ground plane. Ground for PCI Express Ports. Ground for PCI Express Clock. Power for PCI Express Port.
Description
VCCMEM VCC15VL
VCC33PEX VCC15
Power for Graphics Display I/O Logic. 3.3V 5% Suspend power. 1.5V 5% Digital Ground. Connect to main ground plane.
VSUS15PEX
T r u s t e d P la t fo r m M id u le S ig n a l D e s c r ip tio n s
S ig n a l N a m e TCSEN # Ty p e I D e s c r ip tio n T r u s te d C o n f ig u r a tio n S p a c e E n a b le .
83
I I I
CPUSLPIN# BUSY#
I O
O O OD
PEXPMESCI#
OD
PEXHPSCI#
OD
PEXINTR#
OD
O I I
General Output Port. When SR1A[4] is cleared, this pin reflects the state of CR5C[0]. PCI Express Wake. Indicates that a system wake event has occurred on the PCI Express bus. Used to waken the chip from deep sleep mode (S3/S4/S5 states). Wire-OR with other system WAKE# signals (including PEWAKE# on the PCI Express bus connector) and connect to the South Bridge PME input. PCI Express PME SCI. System Control Interrupt to indicate Power Management Event. Connect to South Bridge SCI input (GPIO pin). PCI Express Hot-Plug SCI. System Control Interrupt to indicate Hot Plug occurred. Connect to South Bridge SCI input (GPIO pin). PCI Express Interrupt. Connect to South Bridge interrupt input to indicate that an interrupt condition was detected on PCI Express bus or the internal APIC. Interrupt. PCI interrupt output (handled by the interrupt controller in the south bridge). PCI Express Detect. Used to determine the presence of an external PCI Express device Test Enable. This signal is used for testing.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
AI AI AI AI AI AI
Signal Name Type P HGTLVREF[1:0] MEMVREF[1:0] VLVREF P P
D escription
O I O
PC I Express Port G D ifferential R eceive D ata [15:00]. These signals are multiplexed w ith D igital V ideo Port Signal. PC I Express Port G D ifferential Transmit D ata [15:00]. PC I Express Port 0 D ifferential Transm it D ata 0.
84
FERR#
VPAR
IO
IO I O I O O I I
General Purpose Output 0. General Purpose Output 1. General Purpose Output 2. General Purpose Output 4.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
IGNNE# INIT# OD OD INTR NMI OD OD SLP# OD SMI# OD STPCLK# OD I THRMTRIP#/GPI1
System Management Interrupt. SMI# is asserted by the VT8237A to the CPU in response to different Power-Management events. Stop Clock. STPCLK# is asserted by the VT8237A to the CPU to throttle the processor clock. Thermal Detect Power Down. This signal is to indicate a thermal trip from the processor.
Description
Description
O O I
General Purpose Output 3. General Purpose Output 5. General Purpose Output 6. General Purpose Output 7. General Purpose Output 9.
SATA Crystal In. SATA Crystal Out. SATA LED SATA External Resistor.
O O AI
85
CBE[3:0]#
IO
DEVSEL#
IO
FRAME#
IO
IO IO IO I
PERR#
PAR INTA# INTB# INTC# INTD# INTE#/GPI12,/ GPO12, INTF#/GPI13,/ GPO13, INTG#/GPI14,/ GPO14, INTH#/GPI15,/ GPO15
IO I
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
O O I CLKRUN# IO
PCI Grant. These signals are driven by the VT8237A to grant PCI access to a specific PCI master.
PCI Reset. This signal is used to reset devices attached to the PCI
PCI Clock. This signal provides timing for all transactions on the PCI bus. PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped (high) or running (low). The VT8237A drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping.
Description
SMB/I2C Channel 1 Clock. Mater Mode. SMB/I2C Channel 1 Data. Mater Mode. SMB/I2C Channel 2 Clock. Slave Mode. SMB/I2C Channel 2 Data. Slave Mode.
OD OD I
SMB SMB Alert. Enabled by System Management Bus I/O space. When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event.
86
OD OD OD I
AGPBZ#/GPI6
S er ia l IR O In te r fa c e S ig n a ls
S ig n a l N a m e S E R IR Q Ty p e I
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
MRXC MRXD[3:0] MRXDV MRXER MTXC I I I I MTXD[3:0] MTXEN O O PHYRST# O
Description
MII Receive Data. Parallel receive data lines driven by the external PHY synchronous with MRXC. MII Receive Data Valid.
MII Receive Error. Asserted by the PHY when it detects a data decoding error. MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by the PHY. MII Transmit Data. Parallel transmit data lines synchronized to MTXC. MII Transmit Enable. Signals that transmit is active from the MII port to the PHY. External PHY Reset. PHY Power Down. Output when PHY is in power state as D1 hot, D2 hot or D3 hot with no PME and WOL enable.
PHYPWRDN#
Description
D es cr ip tio n
O O
PC/PCI Grant A.
PC/PCI Grant B.
87
USB Port 0 Over Current Detect. Port 0 is disabled is disabled of low. USB Port 1 Over Current Detect. Port 1 is disabled is disabled of low. USB Port 2 Over Current Detect. Port 2 is disabled is disabled of low. USB Port 3 Over Current Detect. Port 3 is disabled is disabled of low. USB Port 4 Over Current Detect. Port 4 is disabled is disabled of low. USB Port 5 Over Current Detect. Port 5 is disabled is disabled of low. USB Port 6 Over Current Detect. Port 6 is disabled is disabled of low. USB Port 7 Over Current Detect. Port 7 is disabled is disabled of low. USB External Resistor.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
I I I I GPI16/ INTRUDER# GPI17/CPUMISS GPI18/THRM#/ AOLGPI GPI19/APICCLK I I I I
Signal Name Type IO IO M SCK M SDT KBCK KBDT IO IO
88
PDIOW#/PSTOP
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PDDREQ I SDDREQ I PDDACK# SDDACK# IRQ14 IRQ15 O O I I PDCS1# PDCS3# SDCS1# O O O SDCS3# O PDA[2:0] O SDA[2:0] O PDD[15:0] SDD[15:0] IO IO
Secondary Device DMA Request. Secondary channel DMA request Primary Device DMA Acknowledge. Primary channel DMA acknowledge Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge Primary Channel Interrupt Request. Secondary Channel Interrupt Request. Primary Master Chip Select. This signal corresponds to CS1FX# on the primary IDE connector. Primary Slave Chip Select. This signal corresponds to CS3FX# on the primary IDE connector. Secondary Master Chip Select. This signal corresponds to CS17X# on the secondary IDE connector. Secondary Slave Chip Select. This signal corresponds to CS37X# on the secondary IDE connector. Primary Disk Address. PDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. Strap information is communicated to the north bridge via VD[6:4]. Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. Primary Disk Data. Secondary Disk Data.
89
Description
General Purpose Output 23. General Purpose I/O A/24. General Purpose I/O B/25. General Purpose I/O 26. General Purpose I/O 27. General Purpose I/O 28. General Purpose I/O 29.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
AZSDIN2/PCS0#/ GPIO20 I AZSDIN3/PCS1#/ GPIO21 I
Signal N am e Type AI P V LCO M P V LV REF
GNDAPLL
90
I I
SUSC#
EXTSMI#/GPI2
IO
I I I
I I
RING#/GPI3
I O O I O
SMB Alert. When programmed to allow it, assertion generates an IRQ, SMI, or power management event. Notebook Computer Display Lid Open / Closed Monitor. Used by the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high or high-to-low transitions to generate an SMI#. LID# can optionally be used as GPI4. Intrusion Indicator. INTRUDER# can optionally be used as GPI16. Thermal Alarm Monitor. This signal is to enable the throttling mode for the duty cycle control of stop clock. AOLGPI is multiplexed with this pin. THRM# can optionally be used as GPI18. Ring Ondicator. May be connected to external modem circuitry to allow the system to be re-activated by a received phone call. RING# can optionally be used as GPI5. Battery Low Indicator. BATLOW# can optionally be used as GPI5. CPU Clock Stop. Signals the system clock generator to disable the CPU clock outputs. Not connected if not used. PCI Clock Stop. Signals the system clock generator to disable the PCI clock outputs. Not connected if not used. For a Wake-up Event. Connect to PCI Express PEWAKE# signal. Suspend Plane A Control. Asserted during power management POS, STR, and STD suspend states. Used to control the primary power plane.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SUSST#/GPO3 O SUSCLK O I CPUMISS/GPI17 AOLGPI/GPI18/ THRM# I
Signal Name Type I PWRGD PWROK O PCIRST# OSC O I RTCX1 RTCX2 TEST TPO I O I O Test.
PCI Reset. Active low reset signal for the PCI bus. The VT8237A will assert this pin during power-up or from the control register. Oscillator. 14.31818 MHz clock signal used by the internal Timer. RTC Crystal Input: 32.768 KHz crystal or oscillator input. RTC Crystal Output: 32.768 KHz crystal output.
91
P P P P P P
P P P P P
Suspend Power. 3.3V 5%. Always available unless the mechanical switch of the power supply is turned off. If the soft-off state is not implemented, then these signal balls can be connected to VCC33. MII Power. 3.3V 5% I/O Power for LAN Media Independent Interface (interface to external PHY). MII Suspend Power. 2.5V 5%. USB Power. 3.3V 5%. USB Ground.
USB PLL Analog Voltage. Connect to VCC through a ferrite bead. 2.5V 5%. USB PLL Analog Ground. Connect to GND through a ferrite bead.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Description
92
USB 0/1/2/3
NEW CARD
Mini-PCIE Wireless
12 MHz
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
DDR2 400/533/667 MHz
VIA VT1637
LVDS
LCD PANEL
RGB
CRT
USB
PCI-EXPRESS/USB
PCI-EXPRESS/USB
32.768 KHz
CD ROM
PATA
SATA/PATA
HDD
AZALIA
LPC BUS
MII BUS
PHY
25 KHz
MDC Module
SYSTEM
BIOS 512 K
AMPLIFIER APA2056
EXT MIC HP SPEAKER SPEAKER JACK
PS/2
I-LIMIT
TOUCH PAD
93
7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error 7.7 Hard Disk Drive Test Error 7.8 ODD Drive Test Error 7.9 USB Port Test Error 7.10 Audio Test Error 7.11 LAN Test Error
7.12 Mini Express (Wireless) Socket Test Error 7.13 Express Card Socket Test Error
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
94
Check whether no CPU power will cause system cant leave S5 status.
If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending out the PG signal. If yes, we should add the effected analysis into no power chapter.
Base on the digital IC three basic working conditions: working power, reset, Clock. We define the no display as while system leave S5 status but cant get into S0 status.
Base on these three conditions to analyze the schematic and edit the no display chapter.
Keyword:
S5: Soft Off S0: Working For detail please refer the ACPI specification.
95
No Power
No
No
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Where from power source problem (first use AC to power it)? AC Power Replace Motherboard Battery
Parts:
Signals:
+PWR_VDDIN +DVMAIN ADINP LEARNING ADEN# I_LIMIT
U10 PU501 PU506 PF1 PQ1 PQ2 PD4 PD2 PR5 EL545
96
P27
POWER IN
PF1
PR5 PQ1
PJ501
PD2
P27
+PWR_VDDIN
U9,F2
P21
+VDD3_ALW
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PF501,EL534,PQ516,PL505 PU506,PD512 P26
PU502,EL523,PQ509,PQ507,PQ508,PQ510 PQ511,PQ512,PL503,PL504
P25
+CPU_CORE
BATT
Charge
PQ520,PR45,PR46, PQ8,PQ7
Discharge
P27
P27
ADINP
PD4
EL514,PU503
+DVMAIN
PQ504A,PQ504B PL501
P24
+3V_P
P24
PQ503,PQ505 PL502
+5V_P
Discharge
PD501
P19
EL544,PU3
PQ519,PQ518,PL506
P23
EL524
+VDD3_KBC_AVREF
P21
+1.8V_P
Q502
P21
+VDD3_AVREF
P11
Q507
+VDD3S
Q504
P21
PR37
P23
+3V
+0.9V_P
EL6
P12
D11
+VDD3S_SB
P19
+VDD3_RTC
EL525
+VDD3S_KBC
P21
U510
+VDD2.5S
NOTE :
P30 : Page 30 on M/B circuit diagram. PD708 : Through by part PD708.
97
PD2 EC10QS04 A K
+PWR_VDDIN
PD4 PDS1040 3 PC579 1000P PC583 PC577 1000P 1000P
POWER IN
1 2
PF1 6.5A/32VDC
EL545 120Z/100M
PJ501
EC1 18P
EC560 18P
P19
35
LEARNING
PR6 0
110
I_LIMIT
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PQ1 AO4419 3 2 1 8 7 6 5 PR5 0.01
ADINP
+DVMAIN
PR45 100K PC587 1000P
PC589 1000P
PR3 470K
PR1 4.7K
3 4
PR2 4.7K
GND
PC29 470P
PR44 226K
GND
PR4 100K
GND
ADEN#
3 2 1 S PQ520 AO4409 D 8 7 6 5 G
PQ7 DTC144WK
PQ2 2N7002K
PJO1 OPENSMT4
GND
BATT
PC582 1000P PC580 1000P
GND
PR7 1M
PR502 10
4 5 6
RS+ RS-
P27
VCC
GND
GND
OUT1
PU501
GND1 2 1 GND0
PC504 0.1U
PR62 0
PR501 10
GND PC502 1U
GND
98
Charge
PQ516 AO4419
P26 ADINP
PF501 TR/3216FF-3A
EL534 120Z/100M
PC556 1000P
PC557 1000P
PC563 1000P
PR566 10K
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
D G S PC558 4.7U PR556 4.7K PR558 4.7K PC569 4.7U PC571 4.7U PC573 4.7U PD509 B340A PQ514 MMBT2222A PR564 100K PD508 BAS32L BATTERY_TYPE To P19 U10 D G PQ4 DTA144WK S I_CTRL From P19 U10 8,11 PR568 0 12 13 C1,C2 VCC
3 2 1
8 7 6 5
PL505 33UH
BATT
PC570 4.7U PD512 B340A PR24 20K
PC574 1000U
PR22 23.7K
PR21 13.7K
PR20 332K
PQ6 2N7002K
D G S PQ5 2N7002K
P26
2IN+
16 2
2IN+
CHARGING
PR571 47K
OUTPUTCTRL CT RT
1IN-
5 6
PU506
TL594C
2IN15
FEEDBACK
PR573 6.19K
PR572 2.49K
14
REF
DTC
PJS2 SHORT-SMT3
PR570 10K
PC10 0.01U
PC566 0.1U
REF
PC567 0.1U
99
Discharge
+PWR_VDDIN
8 7 6 5
PD501 EC10QS04
+DVMAIN
3 2 1
ADEN#
+VDD3S_KBC P19
3
U10
1 107 BAT_TEMP BAT_VOLT C68 0.1U 2
Keyboard BIOS
111
+VDD3S_KBC
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
D S PC29 470P PQ520 AO4409 G 4
PR45 100K
ADINP
PR44 226K
PQ7 DTC144WK
PR46 33K
PJ502
PQ8 2N7002K
P27
BATT
+VDD3_KBC_AVREF
PR41 4.99K
PC33 0.1U
D9 BAV70LT1
PR576 499K
Battery Connector
R61 22
BATT_T
5 PR43 0
BATT_V
C69 0.1U
R63 22
PC28 0.1U
PR42 20K
PC575 0.1U
PR575 100K
W83L951D
41 42
R42 2.7K
PR48 0
3 4
100
No
Make sure that CPU module, DIMM memory are installed Properly.
Display OK? No
Yes
Correct it.
1.Try another known good CPU module, DIMM module. 2.Remove all of I/O device ( HDD, ODD.) from motherboard except LCD or monitor.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
System BIOS writes error code to port by Mini PCI-E debug card? No Board-level Troubleshooting Parts: Replace Motherboard
U507 U10 U21 U516 U513 U512 U514 U511 J511 X504 SW5 Q10A Q10B Q17A Q17B J4 J516
Display OK? No
Yes
1. Replace faulty part. 2. Connect the I/O device to the M/B one at a time to find out which part is causing the problem.
101
+VDD3S_SB
Q10B 2N7002DW R98 4.7K R582 4.7K SMBDATA Q10A 2N7002DW
+3.3VS_CLK
1,3.. 48
R84 4.7K
R83 4.7K
+3VS
C573 22U
VCLK_NB
22 33 33 33 33 22
P5 P6
GUICLK
PCIECLK_NCARD+ PCIECLK_NCARDPCIEREQ_NCARD#
R137 R140
P15
18 16
J4
P15
13
PCIECLK_MINI+ PCIECLK_MINIPCIEREQ_MINI#
R624 R628
11
J516
C579 10P
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
31 27 44 43 54 23 5 R631 22 R589 22 27 R636 22 22
P11
SMBCLK
P12
P8
11
R608
53 4
34
CPU_STOP#
VIA VT8237A
U512
33
STOP_PCI#
33 33
42 41
36
Clock Generator
51
R600
33
HCLK_CPU+
P3
33 33
38
ICS953009
37
50
R605
33
HCLK_CPU-
35
17
R623
22
PCICLK_KBC
51
U21
System BIOS
102
+VDD3_ALW
R17 1K
P19
U10
50 KBC_RESET# R541 100K 2 1
U508
RESET# GND VCC
KBC W83L951D
29 37 30 53
P21
MN
IDE_PCIRST#
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SW5 P11 P12
1 3 2 4 5 ZJO14
JL506 JP_NET10
FWM_PCIRST#
R508 100
P20
22
U514
+3VS
5
U511 AHC1G08DBV 1 2
P6
SB_PWRGD
+VDD3S_KBC
South
PCI_RESET#
JL505 JP_NET10
NB_PCIRST#
R544 10K
Bridge
C548 0.01U
VIA
JL502 JP_NET10
R286 0
MINIPCIE_PCIRST#
22
P15
J516
Wireless LAN Card Connector
VT8237A
JL504 JP_NET10
+5VS
Q17B DDC144TU Q17A DDC144TU R218 10K R211 33
+5VS
J511
5
R204 10K
P13
ODD Connector
103
1. Confirm LCD panel or monitor is good and check the cable are connected properly. 2. Try another known good monitor or LCD module.
Display OK? No
Yes
Remove all the I/O device & cable from motherboard except LCD panel or extended monitor.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts Replace Motherboard
U513 U504 U514 U10 U6 J1 EL540 EL541 EL542 EL543
Yes
Re-soldering.
One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals
LCD_A_TXD0+/LCD_A_TXD1+/LCD_A_TXD2+/LCD_A_CLK+/LTX0+/LTX1+/LTX2+/LCLK+/ENVDD_NB PANEL_ID0/1 LCD_SPCLK LCD_SPD +DVMAIN BLADJ ENABKL_LCD H8_ENABKL +3VS
Display OK? No
Yes
Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.
104
J1
P6
ENVDD_NB
U513
LCD_SPCLK
LCD_SPD
P9
U504
16,18,21,24 15,17,20,23
U514
PANEL_ID0 PANEL_ID1
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
LCD_SPD LCD_A_TXD[0..2]-,LCD_A_CLKChange to LCD_A_TXD[0..2]+,LCD_A_CLK+ Change to
ENVDD_NB
1,2
LCD_SPCLK
P10
8
LTX[0..2]-,LCLK-
9,15,21,27
LCD
11,17,23,29
LTX[0..2]+,LCLK+
LCD/Inverter Connector
PANEL_ID0 PANEL_ID1
5 4
Inverter Board
14,16
+D/VMAIN
P19
U10
H8_ENABKL
Change to
ENABKL_LCD
22
KBC W83L951D
BLADJ
BLADJ
24
105
1. Confirm monitor is good and check the cable are connected properly. 2. Try another known good monitor.
Display OK? No
Yes
Remove all the I/O device & cable from motherboard except monitor.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts:
U513 U517 U518 J501 Q1A/B EL501 EL502 EL505 EL506 EL507 EL22 EL28
Yes Re-soldering.
No
One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals:
+5VS +3VS CON_DDDA CON_HSYNC CON_VSYNC CON_DDCK CON_RED CON_GREEN CON_BLUE CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_DATA CRT_DDC_CLK CRT_VSYNC CRT_HSYNC CRT_IN#
Replace Motherboard
Display OK? No
Yes
Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.
106
CRT_DDC_DATA
P6
CRT_DDC_CLK
U513
CRT_VSYNC
CRT_HSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
P19
CRT_IN#
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Change to Change to Change to Change to Change to Change to Change to
J501
CON_DDDA 12
P10
CON_DDCK 15
CON_VSYNC
14
CON_HSYNC
13
CON_RED
CON_GREEN
CON_BLUE
CRT_IN#
11
107
1. Check the extend SO-DIMM module is installed properly. ( J513, J515) 2. Confirm the SO-DIMM socket (J513, J515) is ok, no band pins.
Test OK? No
Yes
If your system host bus clock running at 533/667 MHZ then make sure that SO-DIMM module meet require of PC4200/PC5400.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts: Correct it. Replace Motherboard
U513 U19 U514 J513 J515 Q10A/B R249 R250 R251 R252 R254 R253 R256 R255
One of the following components or signals on the motherboard may be defective ,Use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals:
DDR_A_DQ[0..63] DDR_A_DM[0..7] DDR_A_BS[0..2] DDR_A_MA[0..13] DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_CS#[0..3] DDR_CKE[0..3] DDR_ODT[0..3] DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_CLK[0..3]+ DDR_CLK[0..3]SMB_DATA SMB_CLK +1.8V +3VS
Test OK? No
Yes
108
P5
J513
DDR_A_DQ[0..63], DDR_A_DQS[0..7], DDR_A_DQS#[0..7] DDR_A_DQ[0..63], DDR_A_DQS[0..7], DDR_A_DQS#[0..7] DDR_A_MA[0..13], DDR_CKE[0..3], DDR_CS#[0..3]
P8
DDR_CLK[0,1]+, DDR_CLK[0,1]-
U19 ICS9P956
DDR_CLK[2,3]+, DDR_CLK[2,3]-
P12
SMBCLK SMBDATA
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SMB_DATA SMB_CLK Change to SMB_CLK Change to SMB_DATA
P7
DIMM1
DDR_CLK[0,1]+, DDR_CLK[0,1]-
J515
P7 DIMM0
DDR_CLK[2,3]+, DDR_CLK[2,3]-
DDR_A_DQ[0..63], DDR_A_DQS[0..7], DDR_A_DQS#[0..7] DDR_A_MA[0..13], DDR_CKE[0..3], DDR_CS#[0..3] DDR_A_RAS#, DDR_A_CAS#, DDR_A_WE# DDR_A_DM[0..7], DDR_A_BS[0..2], DDR_ODT[0..3]
109
No
Yes
Test Ok? No
Yes
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Correct it. Replace Motherboard Parts
U514 U10 J2 J3 SW6 SW7 EL30 EL31 EL26
Yes Re-soldering.
No
One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals
+5V KI[0..7] KO[0..15] T_CLK T_DATA TP_CLK TP_DATA TP_LEFT TP_RIGHT LPC_AD[0..3] LPC_FRAME#
110
P11 P12
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
95..102 79..94 77 KI[0..7]
J2
3..10
P19
P19
KO[0..15]
11..26 2
KBD_US/JP
U10
52
54
56..59 30
Keyboard BIOS
W83L951D
J3
11,12 9,10
48 47
T_CLK
Change to
TP_CLK
T_DATA
Change to
TP_DATA
P20
SW6 SW_LEFT
2 4 5
1 3
TP_LEFT
7,8
TP_RIGHT
5,6
SW7
+5V
1,2
1 3
2 4 5
SW_RIGHT
Touch-Pad
111
Re-boot OK? No
Yes
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts: Replace Motherboard
U514 J510 J509 R269 R268 R267 R266
One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals:
SATA_RX0+/SATA_TX0+/HDD_DD[0..15] IDE_PDD[0..15] HDD_DA[0..2] IDE_PDA[0..2] IDE_PDCS[1,3]# HDD_DCS[1,3]# IDE_PDACK# HDD_DACK# IDE_PIRDY HDD_IRDY IDE_PIRQ HDD_IRQ HDD_DIOR# IDE_PDIOR# HDD_DREQ IDE_PDREQ IDE_PDIOW# HDD_DIOW#
Re - Test OK? No
Yes End
112
P12
U514
South Bridge
VIA VT8237A
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SATA_RX0+ SATA_RX0SATA_TX0+ SATA_TX0-
J510
P13
113
P11
HDD_DD[0..15] HDD_DREQ
HDD_DCS3# HDD_IRQ
HDD_DIOW# HDD_DIOR#
HDD_DACK#
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Change to Change to Change to Change to Change to Change to Change to Change to Change to Change to
J509
3,4
+5VS
IDE_PDD[0..15] IDE_PDREQ IDE_PDA[0..2] IDE_PDCS1#
P13
27~42 24 9,10,12 8 18 7 14 22 20 20
114
1. Try another known good compact disk. 2. Check install for correctly.
Test OK? No
Yes
Re - Test OK? No
Yes
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts:
U514 U511 J511 R648 Q17A Q17B
One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals:
+5VS +3VS ODD_DD[0..15] ODD_DA[0..2] ODD_DCS[1,3]# ODD_DIOR# ODD_DIOW# ODD_DACK# ODD_IRDY ODD_DREQ ODD_RST# ODD_LED# ODD_IRQ
Replace Motherboard
End
115
ODD_DD[0..15]
P12
U514
ODD_DA[0..2] ODD_IRQ
ODD_DACK#
South Bridge
ODD_DIOR#
ODD_DIOW# ODD_DREQ
VIA VT8237A
ODD_IRDY
ODD_DCS[1,3]#
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
D5 CL-190G
J511
+5VS
32
D7 BAT54A
+3VS
ODD_LED# 37
P13
ODD_DD[0..15]
6..21
ODD Connector
5 31,33,34 29 28 24 25 22 27 35,36
116
Test OK? No
Yes
Correct it.
Re-test OK? No
Yes
Correct it.
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts:
U514 U505 U4 J504 J506 J503 EL509 EL510 EL521 EL508 EL2 EL516 EL3 EL515
Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals:
USBP0+/USBP1+/USBP2+/USBP3+/+5V_USB_1 +5V_USB_2 +5V_USB_3 +5V_USB_4 USB_OC0 USB_OC1 SW_VDD3
Replace Motherboard
117
J503
USBP3USBP32
USB Port
USBP3+
P11
USB_OC1
USBP2-
U514
USBP2+
South Bridge
USBP0USBP0+
VIA VT8237A
USBP1USBP1+
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
U10
Page 19
USBP3+
3 1
+3V U505
VOUT 5 3
+5V_USB_4
+5V
VIN CE
SW_VDD3
P14
GND
FLG
P14
J506
+5V_USB_3 1
USB Port
USBP2-
USBP2+
J504
USBP02 USBP0+ 3
USBP1-
A2
USBP1+
A3 1 A1
+3V U4
VOUT 5 3
+5V_USB_1 +5V_USB_2
U10
Page 19
+5V
SW_VDD3
4 1
VIN CE
P14
GND
FLG
USB_OC0
118
1. Check if speaker cables are connected properly. 2. Make sure all the drivers are installed properly.
Yes
Correct it.
Re-test OK? No
Yes
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting 1.If no sound cause of line out, check the following parts & signals: Parts: Signals:
U10 U14 U17 J519 J518 J512 EL537 EL536 EL539 EL538 EL24 EL27
Check the following parts for cold solder or one of the following parts on the motherboard may be defective,use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement. 2. If no sound cause of MIC, check the following parts & signals: Parts:
U17 U514 U10 U14 J514 EL34 EL35 R236 R231 R238 R226
Signals:
+5VS +3VS MIC1_VREFR MIC1_VREFL MIC1_R MIC1_L MIC_SENSE# ACZ_RST# ACZ_SYNC ACZ_SDIN0 ACZ_BITCLK ACZ_SDOUT
Replace Motherboard
Correct it.
119
+3VS P12
ACZ_SDIN0 ACZ_SDOUT ACZ_SYNC
ACZ_RST# ACZ_BITCLK
P19
U10
72 KBC_BEEP Change to
KBC W83L951D
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
13 SENSE_A Change to 1,9 DVDD1,2 32 MIC1_VREFR MIC1_VREFL 8 5
P17
J514
5 4 3 6 2 1 7 8
P17
28
10 11 6
U17
21
MIC1_L
22
MIC1_R
External MIC
Audio Codec
36
AMP_RIGHT
ALC268
35
AMP_LEFT HP_RIGHT
41
39
HP_LEFT
PC_BEEP
12
PCBEEP
120
+5V
AMP_LEFT
AMP_RIGHT
HP_RIGHT HP_LEFT
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
19 HVDD
P18
ROUT+ ROUT-
22 21
ROUTP
J519
1 2
ROUTN
P18
U14
J518
1 2
LOUT+ LOUT-
8 9
LOUTP
INL_A
LOUTN
P18
INR_A
Audio
4 6
Amplifier APA2056
P18
INR_H INL_H
J512
5 4 3 6 2 1 7 8
17 18
HP_OUTR HP_OUTL
SPK_OFF#
26
HP Jack
121
1.Check if the driver is installed properly. 2.Check if the notebook connect with the LAN properly.
Yes
Correct it.
Re-test OK?
No
Yes
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts: Replace Motherboard
U514 U506 U503 J502 EL518 EL519 X501 R519 RP503
Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals:
RJ45_PJ7 RJ45_PJ4 PJRX+/PJTX+/LAN_TXP/N LAN_RXP/N LAN_DATAIO LAN_DCLK LAN_MTXC LAN_MRXD[0..3] LAN_MTXD[0..3] LAN_MTXE LAN_COL LAN_CRS LAN_MRXC LAN_MRXDV LAN_MRXER +3V
Correct it.
122
LAN_DATAIO
LAN_DCLK
P11
LAN_MRXDV
LAN_MRXC
U514
LAN_MRXER
LAN_MRXD[0..3]
South Bridge
LAN_COL
LAN_CRS
VIA VT8237A
LAN_MTXC
LAN_MTXD[0..3]
LAN_MTXE
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
43 20,21,22,23
+3V
44
P16
J502
PJTX+ PJTXPJRX+ PJRX8 7
35
LAN_TXP
10 9 16 15
P16
34
LAN_TXN
6 3
27
LAN_RXP
U506
U503
45..48
26
LAN_RXN
NS681680P
11
R506 75
R503 75
RJ45_PJ4
4,5
15
LAN
EL520 130Z/100M
16
+3V_LAN
14
R504 75
RJ45_PJ7 1,2
Controller
C526 0.1U
40
XI
11..14
39
10
VT6103L
XO
R519 300K
R518 300
C529 22P
X501 25MHZ
C533 22P
123
1. Check if the wireless card device is installed properly. 2. Confirm wireless driver is installed ok.
Yes
Correct it
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Replace Motherboard Parts:
U512 U513 U514 J516 C605 C605 C606 R653. R654 R655 R656 R657 R658 R659 R624 R628
Board-level Troubleshooting
Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals
+3VS PCIEREQ_MINI# PCIECLK_MINI+/SIO_48M PCI_EXP_RX0+/PCI_EXP_TX0+/LPC_AD[0..3] LPC_FRAME# LPC_DRQ#0 SERIRQ LPC_DBG_CLK WLAN_PD# USBP4+/SMB_CLK SMB_DATA
Re-test OK? No
Yes
124
J516
P8
24 35 37 38 31 48 SIO_48M PCIEREQ_MINI# PCIECLK_MINI17 7 11 13 30 32
U512
Clock Generator
ICS953009
P11
U514
P12
South Bridge
VIA VT8237A
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PCIECLK_MINI+ SMB_CLK SMB_DATA MINIPCIE_PCIRST# Refer Section 8.2(No display-3) PCI_EXP_TX0PCI_EXP_TX0+ PCI_EXP_RX0PCI_EXP_RX0+ LPC_AD[0..3] LPC_FRAME# LPC_DRQ#0 SERIRQ WLAN_PD# USBP4USBP4+
P15
22
31 33 23 25
37..43 45 47 49 20 36 38
1. Check if the express card device is installed properly. 2. Confirm express card driver is installed ok.
Yes
Correct it
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Replace Motherboard Parts:
U512 U513 U514 U516 U20 J4 C322 C333 R278 R693
Board-level Troubleshooting
Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals
+3V +3VS +3.3VS_CARD USBP5+/SMB_CLK SMB_DATA PCIEREQ_NCARD# PCIECLK_NCARD+/PCI_EXP_RX16+/PCI_EXP_TX16+/CPUSB# CARD_RST# CPPE# PCIE_WAKE_UP# NCARD_TX16+/-
Re-test OK?
Yes
No
126
J4 U512
P8
36 41 42 31 48 PCIEREQ_NCARD# PCIECLK_NCARDPCIEREQ_NCARD# PCIECLK_NCARD16 18 19 7 8
Clock Generator
ICS953009
P11 P12
U514
South Bridge
t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PCIECLK_NCARD+ SMB_CLK PCIECLK_NCARD+ SMB_CLK SMB_DATA SMB_DATA PCI_EXP_TX16Change to Change to NCARD_TX16PCI_EXP_TX16+ PCI_EXP_RX16NCARD_TX16+ PCI_EXP_RX16+
P15
24
25 21 22
+3V
5
U516 AHC1G08DBV 1 2
4 SB_CARD_PCIRST# 1
P15
13 4 17
PCI_RESET#
U20
11 12
G577D5U
PCIE_WAKE_UP# USBP5-
PCIE_WAKE_UP# USBP5-
11 2 3
USBP5+
VIA VT8237A
USBP5+
127
Reference Material
Intel Merom Processor VIA VN896 North Bridge VIA VT8237A South Bridge 8515 Hardware Engineering Specification System Explode Views Intel.Inc VIA.Inc VIA.Inc Technology.Corp./MITAC Technology.Corp./MITAC
8515
Publisher : MiTAC Technology Corp. Address : No.269, Road 2, Export Processing Zone, Kunshan, P.R.C Tel : 086-512-57367777 Second Edition : Oct.2007 E-mail : Ally.Yuan @ mic.com.tw Web : http: //www.mitac.com http: //www.mtc.mitacservice.com Fax : 086-512-57385099