Forward-Error-Control-Assisted Detection

Petra Deutgen and Frode Randers

Luleå University of Technology

Div. of Signal Processing
S-951 87 Luleå
Sweden

Ericsson Radio Systems AB

S-164 80 Stockholm
Sweden

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Abstract
In the North American Digital Cellular Mobile Telephone System, D-
AMPS, described by the standard TIA/EIA IS-54, only a part of the digi-
tal speech information is protected against transmission errors by an
error correcting code. This thesis considers a scheme that uses coded bits
to decrease the bit error rate of both uncoded bits and time-delayed
coded bits during detection. The detection scheme has been imple-
mented in a simulation environment for D-AMPS.

A performance gain of up to 3 dB of C/I has been experienced for the

unprotected speech data on a frequency selective fading channel for a
residual bit error rate of 1%. Correcting time-delayed coded bits is not as
successful as correcting uncoded bits; coded bits showed only a very
small decrease in bit error rate.

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Acknowledgements
The first part of the Master’s thesis, written as a conference contribu-
tion, could not have been written without the generous help of Karim
Jamal of Ericsson Radio Systems, department of Radio Access and Sig-
nal Processing Research and Håkan Eriksson and Per Ödling both of
Luleå University of Technology, division of Signal Processing. The
opportunity to write such kind a paper gave us great inspiration and joy.
We are most grateful to them for their help.

We also want to thank our adviser, Johan von Perner of Ericsson Radio
Systems, department of Radio Base Station Development, he gave us
valuable support, when we were developing the reference simulator. As
the new detection scheme was developed, we experienced a large
amount of inspiration and help from our adviser Karim Jamal. Therefore
we want to thank him once more, for his excellent guidance.

It has been a stimulating and pleasant time at Ericsson Radio Systems.

We especially want to thank Omar Ryde and Erol Incenacar, both of Eric-
sson Radio Systems, department of Radio Base Station Development,
who have contributed to this.

Petra Deutgen and Frode Randers

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Introduction
This Master’s thesis project was performed at Ericsson Radio Systems
in Kista, Sweden, as a partial fulfillment of the degree of Master of sci-
ence in computer science and electrical engineering at Luleå University
of Technology. This project is a result of a cooperation between two
departments of Ericsson Radio Systems: the department of Radio Access
and Signal Processing Research (section of Radio Access Research ERA/
T/UR) and the department of Radio Base Station Development (section
of Digital Modem Design AR/RB).

The aim of this thesis has been to evaluate the substance of a re-detec-
tion scheme herein denoted the multi-pass re-detection scheme, pro-
posed by Paul Dent, of Ericsson-GE Mobile Communications Inc., RTP,
NC. In order to measure the performance gain of the above-mentioned
method, we have implemented a multi-pass re-detection scheme in the
SysSim1 simulation environment. We have been able to simulate the per-
formance of both the original receiver (a product simulator of TRX884, a
part of a base station for the D-AMPS system) and the multi-pass
receiver, run under actual conditions. Through these simulations, we
have been able to study various facets of the performance of the multi-
pass receiver.

This thesis comprises four parts, of which part I is intended to be a

self-contained conference contribution. The other parts, parts II-IV,
describe the multi-pass re-detection scheme and the implementation of
it in greater detail. Another possible application of the method than doc-
umented in part I is described in part III.

Part I is written in the form of a conference paper that presents the

results of our work with re-detection of uncoded bits by means of a multi-
pass re-detection scheme.

Part II considers the possibility of using the multi-pass re-detection

scheme with different schemes of signalling. We concentrate on coherent
Quadriphase Shift Keying (QPSK) modulation and Differential Quad-
riphase Shift Keying (DQPSK) that is used in D-AMPS.

Part III investigates the possibility of using error corrected bits to

decrease the bit error rate for the time-delayed coded bits.

Part IV is a documentation of the parts of the software simulator of the

multi-pass re-detection receiver. Part IV will be more informative for
readers already familiar with the SysSim simulation environment. An
explanation of the implementation of the multi-pass re-detection
receiver is given with linkage to source code. The source code itself is,

1. SysSim is a simulation environment developed at Ericsson Radio Systems

that allows system simulation.

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however, not included.

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Part 1
 Forward-Error-Control-Assisted Detection of Uncoded Bits in IS-54
Petra Deutgen and Frode Randers
Ericsson Radio Systems AB
S-164 80 Stockholm
Sweden
Abstract—In the North American Digital Cellular
Mobile Telephone System, D-AMPS, described by the
standard EIA/TIA IS-54, only a part of the digital speech
information is protected against transmission errors by an
error correcting code. We evaluate a method, suggested in
[1], that uses coded bits interleaved among uncoded bits to
decrease the bit error rate among the uncoded bits. In this
method information about error-corrected data bits is fed
back to aid a subsequent re-detection of the uncoded data
bits.
Simulations indicate that a decrease in the bit error rate
for unprotected speech data bits is achievable. A perfor-
mance gain of up to 3 dB of C/I has been experienced on a
frequency selective fading channel for a residual bit error
rate of 1%.
I. INTRODUCTION
In this paper, the detection of blocks of binary data in digi-
tal cellular telephone systems is investigated. Many contem-
porary communication systems use unequal Forward Error
control Coding (FEC) [2], that is, some bits are protected by
more error correcting codes than other bits. This gives the
receivers access to more information about some bits than
about others. We investigate the potential of a scheme that
takes advantage of this.
We will focus on applying a re-detection method to the
North American D-AMPS system, specified by the standard
EIA/TIA IS-54 [3]. In the D-AMPS transmission format, the
bursts consist of both coded and uncoded bits, and the coded
bits are interspersed among the uncoded. This implies that
after having decoded the surrounding coded bits, an enhanced
re-detection of the uncoded bits could be possible.
Assuming that the protected bits have been decoded cor-
rectly, these bits are used as known bits when re-detecting the
burst. Due to the memory in the modulation (differential
modulation), the re-detection can improve the Bit Error Rate
(BER) for the uncoded bits. Memory induced by the channel
(ISI) also allows for improvement, as does the use of decision
directed channel tracking.
Within a burst, the bits from the current frame are mixed
with bits from the next frame, due to interleaving. Therefore
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Luleå University of Technology
Div. of Signal Processing
S-971 87 Luleå
Sweden
it could also be possible to improve the BER for both the
uncoded and coded bits belonging to this next frame [8].
The speech distortion known as “warbling”, sometimes
encountered in the VSELP speech decoder of D-AMPS, is
mainly due to bit errors among the uncoded bits. A method of
improving the BER for uncoded bits, with either a differential
detector or with a maximum likelihood sequence estimator
(MLSE), has recently been put forward in [1]. With a suitably
chosen interleaving pattern, a significant BER reduction is
claimed for the uncoded bits.Thus it is expected that such a
re-detection scheme would enhance the speech quality notice-
ably. In this paper we evaluate the scheme suggested in [1] for
the transmission format of D-AMPS.
Related work can be found in e.g. [4], [5] and [6] where
decoded data have been fed back to aid the detection process.
However, none of these papers exploits unequal error control
coding.
This paper proceeds as follows: Section II gives a short
description of the channel coder and the interleaver employed
in the reference transmission system. Section III presents the
one-pass receiver. Section IV outlines the re-detection of
uncoded bits with the aid of coded bits. Section V studies an
implementation of the re-detection scheme, denoted multi-
pass receiver, with the one-pass receiver, as a building block.
Depending on the interleaving, three types of multi-pass
receivers are studied, called the two-pass, three-pass and
composite receiver, respectively. The simulation setup is
described together with the simulated performances of the
multi-pass receivers in Sections VI and VII. An assessment of
the increase in complexity of implementing the multi-pass
receivers is given in Section VIII, and finally, conclusions are
presented in Section IX.
II. CHANNEL CODING AND INTERLEAVING
The IS-54 standard discriminates among three levels of
FEC-induced protection, see Figure 1. For the bits with the
lowest significance, referred to as class 2 bits, no protection is
invoked. For the bits at the next level of significance, class 1
bits, a convolutional code has been used. Among the class 1
bits, the partition corresponding to the perceptually most sig-
nificant bits, here denoted class 1a bits, have been addition-
ally protected by means of a cyclic redundancy check code ~
B[k] ^ ^ class 1 bits
(CRC). All other class 1 bits are referred to as class 1b bits. B[k] C[k-1]
detector deinterleaver decoder
^
F[k-1]
^ ^
tail bits
c [k-1] Z-1 c [k]
12 most 2 2
perceptually 5 class 2 bits
significant bits
12 Linear 7
178

voice cipher (optional)

block code Convolutional coded Figure 3. The one-pass receiver structure

2-slot interleaver
(19,12) encoder
speech coder

class 1
(2,1,5) bits 260 260
77
class 1 bits decoder. The sequence estimation is done with a soft output
82
Viterbi detector. After the detection of the current burst, B[k],
class 2 bits de-interleaving is done, creating the frame C[k-1]. The class 1
bits are then decoded, while the class 2 bits are taken directly
from the de-interleaved frame, C[k-1].
Figure 1. The channel coding and interleaving [2]
IV. DETECTION OF UNKNOWN BITS AMONG KNOWN IN IS-54
In the block-diagonal interleaving scheme of D-AMPS,
both coded and uncoded bits of a frame are written column- To take advantage of the unequal protection of the trans-
wise into a bit matrix, able to contain one frame. The bits are mitted bits, the protected bits are, when successfully decoded,
then transmitted row-wise in a burst B[k]. used for restraining the trellis of the Viterbi detector (the
number of valid transitions between the states in a trellis is
reduced) in a subsequent re-detection of the unprotected bits.
C[k-1] C[k] The restraining of the trellis, based upon knowledge of
coded bits, is determined by the method of modulation. With
0 1

2 3
differential phase shift keying, as used in D-AMPS, the infor-
.
.
.
.
.
.
.
.
mation lies in the differential phase shifts, so the restraining
. . . .
will be in terms of transition restraining.

B[k] 10 bits ... π/2 ~ (-1,1)

c 1[k-1] c 2[k] c 1[k-1]
Figure 2. The interleaving
Figure 2 shows B[k] being assembled. The bits are selected
row-wise, alternatingly, from the matrix containing the cur-
rent frame, C[k], and the matrix containing the previous
frame, C[k-1]. Thus, the interleaving depth is one frame. In
terms of C[k] and B[k], the interleaving can be described as
C [ k ] = {c 1 [ k ] , c 2 [ k ] }
B [ k ] = {c 1 [ k − 1 ] , c 2 [ k ] }
where c 1 [ k ] and c 2 [ k ] correspond to the set of even and odd
rows of the interleaving matrix, respectively.
III. THE ONE-PASS RECEIVER
Figure 3 shows the one-pass receiver scheme used in this
work. The detector is an adaptive MLSE with decision feed-
back channel tracking and with a subsequent differential
c 2[k] c 1[k-1]
(-1,-1) ~ 0
I
(1,-1) ~ 3π/2
π ~ (1,1)
Figure 4. A differential symbol representing two bits
Specifically, a set of data bits is associated with a specific
phase shift, see Figure 4, or equivalently a transition in the
trellis of the Viterbi algorithm. Any two parallel paths
through the trellis are equivalent as they give rise to the same
sequence of phase shifts. If the detector has knowledge of
some or all of the corresponding bits prior to detecting a dif-
ferential symbol, the trellis may be restrained, thus reducing
the number of valid transitions.

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 ite receiver, which is a combination of the two- and three-pass
Q Q Q Q receivers, avoids the time delay, but is able to use more pro-
tected bits than the two-pass receiver, see Figure 6.

I I I I A. The two-pass receiver

To extract information about the protected bits, a primary
detection, de-interleaving and decoding are done by the one-
pass receiver, resulting in a complete set of class 1 bits as
contained in the frame F̂ [ k − 1 ] . Given that the CRC check
for the class 1a bits in F̂ [ k − 1 ] is affirmative, all of the coded
class 1 bits of Ĉ [ k − 1 ] , resulting from re-encoding
F̂ [ k − 1 ] , are considered known1. Applying the two-pass re-
detection scheme, we initiate a re-detection of the class 2 bits
(x,y) (-1,y) (1,1) (x,1)
in the received burst B˜ [ k ] by means of the two-pass receiver,
Figure 5. The restraining of the trellis similar to the one-pass receiver. Due to interleaving, only the
fraction of the coded class 1 bits of Ĉ [ k − 1 ] found in
Figure 5 shows different examples of transitions when a B˜ [ k ] are known. Consequently, the re-detection of B˜ [ k ] is
symbol represents two bits; Both bits are unknown, the first only based on these bits. The re-detection is done by restrain-
bit is known, both bits are known, the last bit is known. ing the trellis at the location of these known bits in the Viterbi
Algorithm (VA) of the two-pass detector. The two-pass re-
V. THE MULTI-PASS RECEIVER detection of burst B˜ [ k ] is initiated only when the CRC check
of the class 1a bits corresponding to F̂ [ k − 1 ] , in the one-
This section presents a receiver structure, denoted the
pass receiver, is affirmative.
multi-pass receiver, that uses FEC-assisted re-detection.
B. The three-pass receiver
~ To be able to use all class 1 bits when re-detecting the class
^ Prepare
B[k] One-pass F[k-1] 2 bits, the three-pass receiver imposes an extra delay of one
feedback
receiver burst. The class 1 bits in Ĉ [ k − 1 ] and Ĉ [ k − 2 ] found in
information
B˜ [ k − 1 ] are used to re-detect the class 2 bits in B˜ [ k − 1 ] .
That is, after having received and processed burst B˜ [ k ] ,
^ F̂ [ k − 2 ] is output. The restraining method is analogous to
Two-pass F[k-1]
that used in the two-pass detector. In the three-pass case,
receiver
when re-detecting burst B˜ [ k − 1 ] , there are demands on an
^ affirmative CRC check for the class 1a bits corresponding to
c1[k-1]
F̂ [ k − 1 ] as well as for the class 1a bits corresponding to
^
-1 F[k-1] F̂ [ k − 2 ] .
Z Combiner
C. The composite receiver
^
c2[k-1] The composite receiver selects the bits of F̂ [ k − 1 ] from
^ different detectors. The class 1 bits are selected from the one-
Three-pass F[k-2]
~ receiver pass receiver. The class 2 bits are taken from the two-pass and
B[k-1]
the three-pass detectors. The class 2 bits from the two-pass
detector are found in the set ĉ 1 [ k − 1 ] and the class 2 bits
from the three-pass detector are found in the set ĉ 2 [ k − 1 ],
Figure 6. The multi-pass scheme resulting in no inherent extra delay for the composite receiver.
This receiver was originally suggested in [1].
Three types of multi-pass receivers will be studied, called
the two-pass, three-pass and composite receiver, respectively. VI. SIMULATION SETUP
Due to the interleaving, the two-pass receiver uses some, but
Figure 7 shows the simulated transmission system with
not all, of the coded bits as known in the re-detection. In the
transmitter, interferer, channel and receiver. The receiver uses
three-pass receiver all coded bits are considered as known
when re-detecting the uncoded bits, at the cost of adding a
time delay of one burst in the decoding process. The compos- 1. A study using only coded class 1a bits in the restraining is
found in a related paper [8].

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 in Hz. Receiver antenna diversity is simulated by using two
paths with channel correlation ρ=0.7. White Gaussian noise is
Transmitter Channel Receiver
added to each path, prior to receiver filtering, with a constant
signal to noise ration (Eb/N0) of 35 dB.
TX
RCH
(Carrier)
C. The Receiver
C+I RX

TX Between the transmitter and receiver in Figure 7, the sam-

RCH
(Interferer) pling rate is TS/8. The receiver filters in the simulations are
base band models of actual filters. The other parts of the
receiver are described in section V.
Figure 7. The simulation transmission system
VII. SIMULATION RESULTS
antenna diversity as is indicated in the figure. The simulations were done to compare the performance of
the multi-pass receivers with the one-pass receiver. The per-
A. The Transmitter formance of the one-, two- and three-pass receivers, together
Each transmitter block consists of a random data generator with the composite receiver was examined considering the bit
and, as described by the standard IS-54, a channel encoder, an error rate among 15.000 frames containing 159 data bits each.
interleaver, a burst generator and a modulator. Co-channel For C/I values above 14 dB, 20.000 frames were used.
interference is modelled by a single interference transmitter Only the Residual Bit Error Rate (RBER) of the class 2 bits
which is symbol-synchronized with the desired signal. The is considered, i.e. the rate of bit errors in frames having an
influence of the co-channel interference upon the received affirmative CRC check. To achieve comparable statistics, we
signal is signified by the carrier to interference ratio, C/I. required the same amount of successfully received frames for
each of the four receiver structures. Thus the RBER in the
B. The Channel
three-pass detector will actually be taken from the burst
detected by the one-pass detector if the CRC check of frame
C[k-1] is negative and the CRC check of frame C[k-2] is affir-
Rayleigh mative.
fader, f d
A
Rayleigh
τ α
Transmitter

fader, f d Time dispersion of up to one symbol time has been simu-

ρ
"C/I"
lated. The attenuation of the second path, α, is 0 dB unless
Rayleigh
fader, f d otherwise stated. The simulations have been done on both a
(1−ρ 2)
Rayleigh
τ α
slow fading channel (fd = 7 Hz) and a fast fading channel (fd
fader, f d
= 77 Hz), corresponding to vehicle speeds of 10 and 110 km/
h, respectively, at a carrier frequency of 800 MHz.
Rayleigh
fader, f d

Rayleigh
τ α
A. Analysis of class 2 bit performance
Interferer

fader, f d
ρ
Figure 9 shows the performance gain in C/I at 1% RBER of
Rayleigh
fader, f d
the different receivers, compared to the one-pass receiver,
(1−ρ 2) "C/I"
Rayleigh
B simulated on a fast fading channel for different time disper-
τ α
fader, f d
sions, up to one symbol time (here, time dispersion divided
with the sample rate, 8 samples/symbol). According to the
Figure 8. The simulated channel simulation results shown in Figure 9, the class 2 bit perfor-
mances of the multi-pass receivers are more or less indepen-
Figure 8 shows the simulated channel model, with Ray- dent of the degree of time dispersion.
leigh fading and co-channel interference.
The base band equivalent radio channel is modelled by a
two-path FIR model. The paths being uncorrelated and com-
plex Gaussian, with the second-order statistics described by
the isotropic scattering model [7]. This model is characterized
by the parameters (τ,α,fd), where τ is the delay interval, i.e.
the distance between the paths in fractions of the symbol
time, TS, see Figure 8. The relative attenuation of the second
path is α, and fd is the Doppler spread of the Rayleigh fading

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 3.5
0
10
x FER
3
One−pass
−1 Two−pass
2.5 10
Composite
Performance gain (dB)

2 Three−pass
−2
10
1.5

RBER
1 Three−pass −3
10
Composite

0.5 Two−pass
One−pass
−4
10
0

−0.5
0 1 2 3 4 5 6 7 8 −5
Time dispersion (tau) 10
4 6 8 10 12 14 16 18 20
C/I (dB)

Figure 9. Performance Gain in C/I at 1% RBER, for time dis-

persion in the range [0,TS], fd=77 Hz Figure 11. Class 2 RBER; fd=77 Hz, τ=0

Performance simulations with fading channels without composite receiver is as good as the three-pass receiver.
time dispersion and varying C/I are shown in Figures 10 and
11. VIII. ASSESSMENT OF THE COMPLEXITY
The computational complexities of the multi-pass receivers
are higher than the complexity of the one-pass receiver (due
10
0 to the re-detection). About 75% of the computations in the
x FER detector, such as the decision directed channel tracking, have
One−pass to be performed separately for each detector. This adds sub-
10
−1 Two−pass stantially to the increase in complexity. However, because of
Composite the restraining, not all transition metrics of the Viterbi algo-
Three−pass
rithm need to be computed. This will limit the increase in
−2
10 complexity. The fact that the synchronization has to be done
only once for all detectors will also limit the complexity.
RBER

10
−3 The increase in computational complexity for the two- and
three-pass detectors is about 80%. The composite detector
(including all three detectors) has an increase in complexity
10
−4 of about 160% compared to the one-pass detector.
Furthermore, algorithm-specific computations, e.g. the cal-
−5
culation of feedback data, will contribute to an additional
10
4 6 8 10 12 14 16 18 20 increase in complexity that is difficult to estimate, but we
C/I (dB)
assess this as small.
Figure 10. Class 2 RBER; fd=7 Hz, τ=0 Memory usage is also a consideration. An additionally
received burst has to be stored; interleaver memory must be
The Frame Erasure Rate (FER) is measured as the number added to contain restraining information between bursts;
of erased frames per total number of simulated frames. In the memory for detector-specific restraining information must be
simulations, the performance gain of the re-detection scheme provided, etc.
tends to increase with the Doppler spread. The figures shows The main reason for the high complexity of the multi-pass
that the three-pass receiver has a higher performance gain receiver is that decision-directed channel-tracking is used in
than the two-pass receiver. At 1% RBER, the composite each detectors. If this can be avoided, e.g. by channel interpo-
receiver has a performance gain of about 2 dB compared to lation, complexity will decrease substantially. In systems
the one-pass receiver but about 1 dB performance loss com- where the channel can be considered stationary, e.g. the
pared to the three-pass receiver. At very low C/I values, the

5(6)
GSM, or systems where differential detection may be used, Radio,” IEEE Transactions on Vehicular Technology, Vol. 42, No. 1,
e.g. the PDC, the complexity is expected to be less of a prob- February 1993, pp. 94-102.
lem. [7] R.H Clarke, “A Statistical theory of Mobile Radio Reception,” Bell
System Technical Journal, 1968, pp. 957-1000.
IX. CONCLUSIONS [8] P. Deutgen & F. Randers, “Forward-Error-Control-Assisted Detection,”
A scheme for FEC-assisted detection of the uncoded bits of Master’s Thesis 1994:149E, Luleå University of Technology, Div. of
Signal Processing, 1994.
the D-AMPS format has been investigated. The performance
at 1% RBER of the uncoded bits is improved by approxi-
mately 2 dB C/I on a fading, time-dispersive channel. The
performance gain is more or less independent of the amount
of time dispersion1. Other simulations indicates that the effec-
tiveness of the FEC-assisted detection of the uncoded bits is
dependent on the interleaving employed. The improvement is
assessed to have a noticeable impact on the speech quality of
the system, since the speech distortion problem known as
“warbling” is largely an effect of bit errors among unpro-
tected bits.
The complexities of the studied multi-pass detectors are
relatively high. Compared to a conventional detector, the
increase in computational load is about 160%. This is mainly
due to the use of equalizers with decision directed channel
tracking. For systems where this is not required, e.g. the GSM
(Global System for Mobile Communication) or the PDC (Per-
sonal Digital Cellular) systems, the total complexity is
expected to be significantly smaller.

ACKNOWLEDGEMENT
We wish to express our gratitude towards Mr. Karim Jamal
of Ericsson Radio Systems AB for his significant contribu-
tions to the present work.

REFERENCES
[1] P. Dent, “Invention Disclosure for Decodulation,” Internal Document
Ericsson-General Electric, RTP/EGE/CT/Y 93:0009, May 1993.

[2] S. Lin and D.J. Costello Jr., “Error Control Coding: Fundamentals and
Applications,” Englewood Cliffs, NJ: Prentice Hall, 1983.
[3] EIA/TIA Interim Standard IS-54-B, “Cellular System Dual-Mode
Mobile Station - Base Station Compatibility Standard,” Electronic
Industries Association, 1992.

[4] R. Mehlan, H. Meyr, “Combined Equalization/Decoding of Trellis-

Coded Modulation on Frequency Selective Fading Channels,” Proc.
5:th Tirrenia Int. Workshop on Digital Communications, pp. 341-352,
Elsevier Science Publishers B.V., 1992.
[5] S. Chennakeshu, R.D. Koilpillai, E. Dahlman, “Enhancing the Spectral
Efficiency of the American Digital Cellular System with Coded
Modulation,” Proc. 44:th IEEE Vehicular Technology Conference, June
8-10, 1994, Stockholm, Sweden, pp. 1001-1005.

[6] R. Sharma, W. D. Grover and W. A. Krzymien, “Forward Error Control

(FEC) Assisted Adaptive Equalization for Digital Cellular Mobile

1. Simulation not reported here shows that the effectiveness of the

FEC-assisted detection of the uncoded bits depends on the inter-
leaving employed.

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Part 2
 Detection of Unknown Bits Among Known Bits.
Petra Deutgen and Frode Randers

Ericsson Radio Systems AB Luleå University of Technology

S-164 80 Stockholm Div. of Signal Processing
Sweden S-971 87 Luleå
Sweden

I. INTRODUCTION symbols. The channel has no memory, therefore a memory-

The knowledge gained by a prior detection and decoding of
protected bits can be used in different ways depending on the
modulation employed. This paper is a continuation of part 1
and will briefly discuss different methods of doing FEC-
assisted re-detection based upon different types of modula-
tion, detection and symbol constellations.
Re-detection issues for the two modulation forms Quad-
riphase shift keying (QPSK) and Differential QPSK
(DQPSK) is discussed in the following section. QPSK modu-
lation produces 4 possible symbols to be transmitted. These
symbols represent 2 bits. One or a both of these bits could be
considered as known during re-detection. Thus we distinguish
between two cases of symbol constellations containing
known bits:
less detector is used in this section. In Subsection A re-detec-
tion of the QPSK modulated fully known symbols is
discussed and in Subsection B re-detection of partially known
symbols is discussed.
A. Fully known symbols
All known bits are grouped into fully known symbols, and
consequently all unknown bits make up the surrounding
unknown symbols. Since there is no coupling between known
and unknown bits, the only gain possible is an enhanced
channel (phase) estimation for the surrounding unknown
symbols.
B. Partially known symbols

• A fully known symbol, where both bits of the symbol Due to the Gray coding normally used, there will be no
are known. decrease in bit error probability, for the unknown bits, see
Figure 1.
• A partially known symbol, where one bit of the sym-
bol is known.
Besides the two different modulation forms and the two M=4
symbol constellations this paper also considers two channel Q Q
cases, with Intersymbol Interference (ISI) and without ISI. In
(-1,1) (-1,-1)
the former case a maximum likelihood sequence estimator
(MLSE) is used, and in the latter case a memoryless threshold
I I
detector is used. The results are presented in a table, consist-
ing of the following sections: (1,1) (1,-1) (1,1) (1,-1)
• QPSK modulation and channel with no ISI
• QPSK modulation and channel with ISI
a) Symbol unknown b) Symol partially known;
• DQPSK modulation and channel with no ISI first bit known to be 1
• DQPSK modulation and channel with ISI Figure 1. The restraining of signal points

II. POSSIBILITES FOR PERFORMANCE GAINS
No estimations of possible gains are made in the following
sections. Only the question if there will be a gain or not in the
detection, using a specific method, is considered.
QPSK MODULATION AND CHANNEL WITH NO ISI
This system exhibits no kind of dependencies between the
The QPSK modulated symbol is equivalent to two inde-
pendent BPSK symbols each representing one bit and the
decision boundary does not change for one of the bits when
knowing the other. The only gain possible is an enhanced
channel (phase) estimation for the surrounding unknown
symbols, as in Subsection A.

1(3)
QPSK MODULATION AND CHANNEL WITH ISI
This system exhibits dependencies between the symbols.
The channel has memory and therefore an equalizer is used in
this section. In Subsection A, re-detection of the QPSK modu-
lated fully known symbols is discussed and in Subsection B
re-detection of partially known symbols is discussed.
A. Fully known symbols
The detection of the unknown symbols will benefit from
the surrounding known symbols due to the ISI. The trellis of a
Viterbi algorithm is forced to go through a single state at each
known symbol, see Figure 2. Thus a gain is possible due to
better ISI-estimation and better channel-tracking because of
more reliable decisions.
M=4 Unknown Fully known Unknown
symbol symbol symbol
Figure 2. A fully known coherent symbol
B. Partially known symbols.
The trellis is forced to go through 2 states at the locations of
partially known symbols, see Figure 3.
Unknown Partially known Unknown
M=4
symbol symbol symbol
Figure 3. A partially known coherent symbol
There is a re-detection gain of the unknown bits in the par-
tially known symbol because of better ISI-estimation and bet-
ter channel-tracking, but there is no re-detection gain attained
by the decreased number of possible symbol-choices.
DQPSK MODULATION AND CHANNEL WITH NO ISI
This system exhibits dependences between the symbols,
2(3)
due to the differential modulation. The channel has no mem-
ory and therefore a detector without equalizer is used in this
section. In this section the re-detection method of the QPSK-
modulated fully known symbols is described.
A. Fully known symbols
The re-detection method applied to this form of detection
will consist of knowing (any number of) phase changes up to
some point and thereafter use an enhanced initial vector for
detecting the following unknown symbol. Based upon a
known phase shift Θ1, i.e. the angle between vector z[k-1] and
vector z[k], a better estimate of the starting vector for the sub-
sequent unknown phase-shift Θ2 is feasible [1]. Figure 4
M=4 Θ 1 = π/2 (Known phase shift)
Q z[k-1]
Θ1
I
~
Θ2
z[k]
z[k+1]
Figure 4. Differential detection
shows three incoming coherent symbols z[k-1], z[k] and
z[k+1]. After detection, the output will be two differential
symbols representing the phase-shifts between z[k-1] and
z[k], and z[k] and z[k+1], respectively. In this case the first
symbol, representing the phase-shift Θ1, is known. The sec-
ond symbol represents the phase-shift Θ2. Due to the known
phase-shift, z[k] could be enhanced, which is explained in
Figure 5. With an enhanced start-symbol z[k], a better esti-
mate of the symbol representing the phase-shift Θ2 could be
gained.
Figure 5 shows the enhancement of the start-vector when
the phase shift is known to be π. In Figure 5, z[k-1] and z[k]
are the incoming coherent symbols when x[k-1] and x[k] are
transmitted. The phase-shift between z[k-1] and z[k] is known
as π. Since the phase-shift is known to be π, z[k-1] shifted π
could be used instead of z[k], but this shifted symbol would
have equal statistics as z[k-1]. An enhanced symbol is
obtained by taking the average of the two symbols, the shifted
z[k-1] and z[k], as shown in Figure 5. Also, known symbols
following an unknown symbol may be used (in reverse) to
enhance the final vector of the unknown phase change (z[k+1]
in Figure 4). If infinitely many preceding phase-shifts to an
unknown phase-shift are known the coherent start-symbol of
 three symbols, first symbol and last symbol are unknown
M=4 z[k]=x[k]+n 2 while the second symbol is fully known. One effect of this
kind of restraining is that the trellis is forced apart at the loca-
tion of a fully known symbol. As in the case of coherent mod-
Q n ulation there is a performance gain possible due to better ISI
1 Fully known
phase shift estimation and better channel-tracking. A performance gain
z[k-1] because of noise averaging is also made possible, due to the
Enhanced differential modulation.
vector

Shifted z[k-1]
(n 1 + n 2) / 2
Figure 5. Symbol enhancement
z[k]
B. Partially known symbols
I
There are 2 transitions out of each state, see Figure 7, lead-
n
2 ing to two possible transitions at the location of the partially
known symbol. A case dealing with both fully known sym-
bols and partially known symbols is studied and simulated in
[2].

this unknown phase-shift would be correct. In this case the Unknown Partially known Unknown
M=4
differential detection would have the same performance as a symbol symbol symbol
coherent detector. The maximum increase is thus less than 3
dB. If an unknown symbol is surrounded by infinitely many Q Q Q
known symbols, the performance increase has no limit.

DQPSK MODULATION AND CHANNEL WITH ISI I I I

This system exhibits dependences between the symbols,

due to the differential modulation and memory in the channel,
therefore an equalizer is used in this section. In Subsection A
the re-detection method of the DQPSK modulated fully
known symbols is described and in Subsection B re-detection
of partially known symbols is described.

A. Fully known symbols

Figure 7. A partially known differential symbol

M=4 Unknown Fully known Unknown III. SUMMARY

symbol symbol symbol
To achieve any performance gain by re-detection of unpro-
Q Q Q tected protected and unprotected bits must be sufficiently
mixed and there has to be a memory of some kind in-between
received bits. This memory can be inherent in the modulation,
I I I e.g. in differentially encoded modulation, or it may be due to
the channel introducing ISI. It may also be a result of how the
detector works; if the detector uses adaptive channel tracking
the unprotected bits could be re-detected with a better channel
estimate, due to more known pilot symbols.

IV. REFERENCES
[1] P. Dent, “Invention Disclosure for Decodulation,” Internal Document
Ericsson-General Electric, RTP/EGE/CT/Y 93:0009, May 1993.

[2] P. Deutgen & F. Randers, “Forward-Error-Control-Assisted Detection,”

Figure 6. A fully known differential symbol
Master’s Thesis 1994:149E, Luleå University of Technology, Div. of
Signal Processing, 1994.
Instead of restraining the trellis to a single state, a single
transition is allowed out of each state, see Figure 6 showing

3(3)
Part 3
 Re-Detection of Coded Bits for IS-54

Petra Deutgen and Frode Randers

Ericsson Radio Systems AB Luleå University of Technology

S-164 80 Stockholm Div. of Signal Processing
Sweden S-971 87 Luleå
Sweden

I. INTRODUCTION receivers considering re-detection of class 1 bits, is worse

than of the one-pass receiver and more or less independent of
This paper is written as to develop some of the ideas that
came up in part 1 and is meant to be a complement. In con- the degree of time dispersion.
trast to [1], this paper will treat the performance of the multi-
pass re-detection scheme for re-detecting coded bits. Due to
0.5
the interleaving [2], the unknown class 1 bits transmitted in
the current burst, belonging to the current frame, can be Three−pass

helped by the error corrected class 1 bits transmitted in the Two−pass

One−pass
same burst, but belonging to the previous frame.
In Section II the performance of the two-pass receiver is 0
Performance gain (dB)

analyzed, using the fading channel in [1]. In Section III fur-

ther studies on the re-detection scheme, using an AWGN
channel, are done. Three probable effects on the performance
of the re-detection of the coded bits will be discussed: −0.5
1) How the use of information, on incorrectly received bits,
in the re-detection affects performance of the multi-pass
receiver.
2) How the adaptive channel tracking influences the re-
−1
detection. 0 1 2 3 4
Time dispersion
5 6 7 8

3) How the soft information provided to the channel

decoder during detection influences the multi-pass receiver.
II. SIMULATIONS ON A FADING CHANNEL WITH CO-CHANNEL
INTERFERENCE
The simulations are done in order to compare the perfor-
mance of the multi-pass receivers with the one-pass receiver.
The performance of the one-, two- and three-pass receivers,
together with the composite receiver is examined considering
the bit error rate among 15.000 frames containing 159 data
bits each. For C/I values above 14 dB, 20.000 frames were
used in the simulations. Time dispersion of up to one symbol
time has been simulated. The attenuation of the second path,
α, is 0 dB. The simulations have been done on a fast fading
channel (fd = 77 Hz) [1].
Figure 1 shows the performance gain in C/I at 1% RBER of
the class 1 bits, of the different receivers, in comparison with
the performance of the one-pass receiver, simulated on a fast
fading channel for different time dispersions [1]. The simula-
tion results indicate that the performance of the multi-pass
Figure 1. Class 1 performance gain in C/I at 1% RBER, for
time dispersion in the range [0,Ts], fd=77 Hz
A. Analysis of class 1 bit performance for the three-pass
receiver.
Figure 2 shows the RBER [1] for the class 1 bits experi-
enced with the one- and three-pass receiver respectively.
According to the simulation results, the three-pass receiver
exhibits no improvement in class 1 bit performance compared
to the one-pass receiver. This confirms the theory that since
all class 1 bits are considered known (and correct) and the
three-pass receiver in consequence is forced to detect the
class 1 bits in compliance with this information, no improve-
ment will occur. According to the simulations the three-pass
receiver is slightly worse than the one-pass receiver for low
C/I values. This may have an explanation in that for low C/I
values, an entire new (valid) CRC code word can be formed
resulting in an affirmative CRC check from the one-pass
receiver, although bit errors are found among the class 1a bits.

1(4)
 could decrease the performance gain of the re-detection
10
0 scheme when utilized to restrain the trellis. The effect of
using incorrect bits in the pruning of the trellis is analyzed in
x FER
One−pass
Subsection A.
−1
10 Three−pass 2) The influence of the channel tracking on the perfor-
mance of the re-detection scheme is discussed in Subsection
10
−2 B.
3) Differences in performance of the multi-pass scheme
RBER

when supplying soft information to the decoder versus sup-

−3
10 plying hard information is discussed in Subsection C.

−4
A. Simulations with all class 1 bits used in the restraining
10
compared with simulations with only class 1a bits used in the
restraining.
10
−5
Incorrectly received bits will introduce error-propagation
4 6 8 10 12 14 16 18 20
C/I (dB) when they are used to prune the trellis in the re-detection.
Simulations are performed with two different definitions of
Figure 2. Class 1 RBER, fd=77 Hz, τ=0 which bits may be considered known:
B. Analysis of class 1 bit performance for the two-pass 1) All class 1 bits are considered as encompassed in the
receiver. CRC check and thus known in a subsequent re-detection.
2) Only coded class 1a bits are considered known in a sub-
Figure 3 shows the RBER experienced with the one- and
sequent re-detection. This demands a strict classification of
two-pass receivers [1]. The two-pass receiver has a perfor-
coded class 1a bits.
mance loss compared to the one-pass receiver.
The classification of coded class 1a bits is necessary since
all class 1 bits are convolutionally encoded and a coded bit
10
0 may have been computed based upon information on both
class 1a bits and class 1b bits. The strict classification regards
x FER
the constraint length of the encoder and refers to the coded
One−pass
10
−1
Two−pass class 1 bits which have been computed only based upon infor-
mation on class 1a bits, parity bits produced by the block
−2
coder and tail bits (known bits) [2].
10
Simulations are done to compare the one-pass and the two-
RBER

pass receivers. In these simulations the one-pass and the two-

−3
10 pass detectors provide soft information to the channel decod-
ers.
−4
Figure 4 shows the performance of the two-pass receiver
10
when using all class1 bits and when using only class 1a bits,
respectively, together with the performance of the one-pass
10
−5
receiver. It is shown in the figure that the performance of the
4 6 8 10 12 14 16 18 20
C/I (dB) two-pass receiver is better when using only class 1a bits in the
re-detection. However, the one-pass receiver is still better
Figure 3. Class 1 RBER, fd=77 Hz, τ=0 than the two-pass receiver using only the class 1a bits.
Other simulations, not documented in this report, shows
III. SIMULATION OF THE MULTI PASS SCHEME ON AN that for C/I values higher than 1 dB all class 1a bits, which are
ADDITIVE WHITE GAUSSIAN NOISE (AWGN) CHANNEL used as known in the re-detection, are correct. Therefore the
The simulation results considered in this chapter are pro- decrease in performance during re-detection, using these bits
vided using an AWGN channel with no time dispersion and only, is probably not due to error propagation in the re-detec-
several signal to noise ratios (Eb/No). Three probable causes tion.
to a decrease in performance for re-detection of class 1 bits
are analyzed:
1) Only the class 1a bits are encompassed by the CRC
check. This implies that incorrectly received class 1b bits

2(4)
 1 1
One-pass
Two-pass, class 1a+1b
Two-pass, class 1a
0.1
RBER
0.01
0.001
0.0001
0 1 2 3 4 5 6 0
SNR (dB)
Figure 4. Class 1 RBER, AWGN, soft decision, [all class1,
class 1a] used
B. Simulations with and without channel tracking
In the two- and three-pass detectors, the paths in the trellis
are forced to follow predestinated transitions at locations cor-
responding to known class 1 bits. Because the detection is
coherent with a subsequent differential decoding, at least one
transition out from each state will always be allowed (corre-
sponding to a location with a fully known phase shift) [1].
Due to this, the quick merge of nodes in the two- and three-
pass detectors is prevented where the trellises are pruned.
Instead, the paths are forced apart. This side-effect, when
pruning the trellis, might affect the channel tracking, when
the channel-tracking is done according to the coherent states
in the trellis.
Figure 5 shows simulations done with channel tracking and
without channel tracking, using the AWGN channel with the
same conditions as in section C where all class1 bits are con-
sidered as known during the re-detection. According to the
simulations the channel tracking has no negative effect on the
performance of the two-pass re-detection of the coded bits.
Though the side-effect, that the trellis are forced apart, when
pruning the trellis, might still be a cause to the bad perfor-
mance for the re-detection scheme in some other sense than
that the channeltracking is not negatively affected.
3(4)
Two-pass, soft dec., class 1a, no est
Two-pass, soft dec., class 1a, est
0.1
RBER
0.01
0.001
0.0001
1 2 3 4 5 6
SNR (dB)
Figure 5. Class 1 RBER, AWGN, soft decision, [channel-
tracking, no channel-tracking] used
C. Simulations with hard and soft information to decoder
The detectors used in the simulations can produce either
soft or hard information to the decoder. The soft information
provided by the detector depends on the certainty of the deci-
sions during detection [3]. In the re-detection scheme, loca-
tions in the trellis, corresponding to known bits and also
surrounding locations, will produce re-detected bits with a
soft value implying higher certainty than the corresponding
bits have got during the one-pass detection. Thus the decoder
could get erroneously detected bits with soft values indicating
high certainty. The utilization of soft information in this case
may decrease the performance gain of the decoder compared
to when hard information is used, instead of increasing it.
Therefore, differences in performance of the re-detection
scheme when using soft information versus hard information
is analyzed.
Simulations are done to compare the performance of the
two-pass receiver passing soft information versus hard infor-
mation to the decoder. Figure 6 shows the performance of the
two-pass receiver when using soft information, all class 1 bits
used as known or just the class 1a bits used as known and
hard information with the same classification of known bits.
The simulations show that for increasing C/I values, the gain
increases for the two-pass receiver using hard decisions, i.e.
the performance is better than the performance of the two-
pass receiver using soft information. It seams likely that the
current soft decision algorithm is incompatible with this re-
detection scheme.
The comparisons between the performance gain of the two-
and one-pass receiver both using hard information and only
the class 1a bits as known, is shown in Figure 7. According to on class 1a bits only in the re-detection scheme is preferred
the simulations, the gain increases when multi-pass re-detec- before using all class 1 bits. The way the pruning of the trellis
tion is used, even though the increase is almost zero. is done is not affecting the channel tracking negatively, but
might affect the performance of the multi-pass receiver in
some other extent. Comparison of the performance of the
1 one- and two-pass receiver, using hard decision and only the
Soft decision, class 1a+1b
Soft decision, class 1a bits protected by the CRC, indicates that re-detection can be
Hard
Hard
decision,
decision,
class
class
1a+1b
1a
used to increase the performance of the class 1 bit detection.
0.1 The performance gain is negligeable though. The perfor-
mance for different types of interleaving has not been simu-
lated since the interleaving is stipulated by the standard IS-54.
0.01
The performance can probably be increased further by using a
more suited scheme of interleaving.
RBER

REFERENCES
0.001
[1] P. Deutgen & F. Randers, “Forward-Error-Control-Assisted Detection,”
Master’s Thesis 1994:149E, Luleå University of Technology, Div. of
Signal Processing, 1994.
0.0001
[2] EIA/TIA Interim Standard IS-54-B, “Cellular System Dual-Mode
Mobile Station - Base Station Compatibility Standard,” Electronic
Industries Association, 1992
1e-05
0 1 2 3 4 5 6 [3] G. Bottomley, “Soft information in ADC,” Internal Report RTP/EGE/
SNR (dB) CT/Y 93:0024, Ericsson-General Electric, July 1993.

Figure 6. Class 1 RBER, AWGN, [hard, soft decision], [all

class 1, class 1a] bits used

1
One-pass, hard decision
Two-pass, hard decision, class 1a

0.1

0.01
RBER

0.001

0.0001

1e-05
0 1 2 3 4 5 6
SNR (dB)

Figure 7. Class 1 RBER, AWGN, hard decision,

class 1a bits used

IV. CONCLUSIONS
The soft decision algorithm employed today [3] should be
modified if a re-detection of the class 1 bits should be useful.
For low to moderate C/I values, the utilization of information

4(4)
Part 4
 A Functional Description of the Multi-pass
Equalizer

This document is a description of the implementation of the multi-pass

equalizer as proposed by Paul Dent [1]. The program is based on the
REQU, the reference equalizer developed by T/UR, modified in order to
run together with other components of the TRX884 DVC simulator.
Therefore we will describe the REQU core as well.

1(19)
Contents

1 The REQU core 3

1.1 The module Compute R&Phi . . . . . . . . . . . . 4
1.2 The module Process R&Phi . . . . . . . . . . . . 4
1.3 The module Synchronize . . . . . . . . . . . . . 5
1.4 The module Demod . . . . . . . . . . . . . . . 5

2 The Multi-pass Equalizer Scheme 6

2.1 The one-pass demodulator . . . . . . . . . . . . 6
2.2 The channel decoder . . . . . . . . . . . . . . . 6
2.3 The channel encoder . . . . . . . . . . . . . . . 7
2.4 The index calculators . . . . . . . . . . . . . . 7
2.5 The two- and three-pass detectors . . . . . . . . . . 7

3 Calculation of bit errors 11

4 Parameters defining multi-pass operation 11

5 References 12

6 The SysSim simulation model 13

6.1 The top layer . . . . . . . . . . . . . . . . 13
6.2 The REQU . . . . . . . . . . . . . . . . . 14
6.3 The multi-pass equalizer . . . . . . . . . . . . 15
6.4 Bit error calculation . . . . . . . . . . . . . . 16

7 Template for simulations 17

7.1 simparam parameters file . . . . . . . . . . . . 17
7.2 simparam template file . . . . . . . . . . . . . 17

2(19)
1 The REQU core

Initial channel estimate

together with position of
known syncword in received
Carthesian complex
sequence of samples.

Feedback information on estimated frequency error

Compute Process
Synchronize
Sequence of R & Phi R & Phi
samples from Demod
diversity
path 1 Polar complex
Adaptive Detected
channel bits
equalizer
based upon
SSVE, FSVE
Compute Process or PFVE
Synchronize
Sequence of R & Phi R & Phi scheme
samples from
diversity
path 2 Feedback information on estimated frequency error

Figure 1. A schematic illustration of the REQU core

As a part of implementing and simulating the multi-pass equalizer we

have adapted the reference equalizer, REQU, created at T/U to the
RBS884 product simulation environment. The REQU itself consists of
four blocks: Compute R&Phi, Process R&Phi, Synchronize and Demod
(Present code is found in mpass_demod), see Figure 1 and Figure 7. The
module Compute R&Phi is intended as a compatibility unit where differ-
ent types of conversion is made between polar complex representation,
cartesian complex representation etc., on samples delivered to the
REQU. Compute R&Phi delivers two flows of data, R and Phi, to Process
R&Phi for scaling and frequency adjustment. A feedback mechanism
exists in order to compensate for frequency error on the received vector
of samples. Synchronize correlates the a priori known synchronization
word with the received vector of samples in order to find the position of
the synchronization word in the received vector of samples. Also the
synchronizer delivers a channel estimate which is used in the demodula-
tor to initiate the adaptive process of channel estimation. Demod is the
demodulator and detector. The term demodulator is used because the
transition from the radio signal, simulated as a complex base band sig-
nal, to binary (soft) bits takes place inside Demod. The detector is an
adaptive maximum likelihood sequence estimator.

1.1 The module Compute R&Phi

Because the REQU is meant to be independent of the environment in
which it is used, a compatibility block exists that performs one of several

3(19)
available conversions. The REQU uses polar complex samples internally
so for instance cartesian complex samples could be converted to polar
complex samples in this block. Compute R&Phi also limits the phase to a
value between 0 and 2π. The samples will at this point be π/4-DQPSK,
see Figures 2.

pi/4 DQPSK
5

1
Quadrature

−1

−2

−3

−4

−5
−5 0 5
Inphase

Figure 2. An example of a signal produced by Compute R&Phi

1.2 The module Process R&Phi

The main function of this block is to subtract the π/4 shifts from the
samples, see Figure 3. As these were introduced in order to enhance the
performance of the linear transmitter filter, they are removed without
affecting the detection of the signal. Thereafter the signal will be ordi-
nary DQPSK. Scaling of the samples may also be done with one of sev-
eral available methods, e.g. scaling to normalize the rout mean square
(RMS) value, scaling with max amplitude or no scaling. We recommend
scaling with RMS because the delta metrics of the Euclidean distance
Viterbi detector may otherwise take on very high values, potentially cre-
ating numerical problems. A feedback loop exist from the demodulator
and detector, Demod, back to this block and thus makes automatic fre-
quency control possible, i.e. automatic adjustments to the phase based
upon information from the demodulator/detector, see Figures 1 and 6.

1.3 The module Synchronize

Synchronize will try to find the beginning of the synchronization word in
the sampled sequence employing a cross correlation method. Since the
synchronization word has an cyclic autocorrelation feature the cross cor-
relation between the sync word in the received sequence and the sync
word itself turns out to be a channel estimate. This estimate will be used

4(19)
 DQPSK
1.5

0.5

Quadrature
0

−0.5

−1

−1.5
−1.5 −1 −0.5 0 0.5 1 1.5
Inphase

Figure 3. An example of a signal produced by Process R&Phi

as an initial value for the adaptive channel estimation scheme, see Fig-
ures 1 and 6.

1.4 The module Demod

Demod is the main block of the REQU, see Figure 1 and Figure 7. It com-
prises different channel estimation schemes, a predictor to be used to
combat problems arising from the decision delay in the equalizer and
the equalizer itself. Demod may be configured in different ways to act as
a symbol spaced Viterbi equalizer, SSVE, with a fractionally spaced pre-
filter also as a prefilter Viterbi equalizer, PFVE and as a fractionally
spaced Viterbi equalizer, FSVE. Demod also takes into account diversity
through two different diversity channels (distance diversity). The infor-
mation from the diversity and the oversampled (fractionally spaced) sig-
nal is combined in the calculation of the delta metrices. For more
information on this confer [2] and [3].

5(19)
2 The Multi-pass Equalizer Scheme

f [.] corresponds to the even rows and

1
f2 [.] to the odd rows in terms of the
interleaving matrix.
F[k] = { f1[k], f2[k]} S[k] = { f1[k-1], f2[k] }
~ ~ ~
B[k] = { b[k]} convolutional S[k] = { f1[k-1], f2[k] }
interleaver "channel"
encoder
-1
f1[k-1] Z f1[k]

~ ^ ^ ^ ^
S[k] F[k-1] = { f1[k-1], f2[k-1] } B[k-1] (Class 1&2)

convolutional
detector 1 de-interleaver
decoder
-1 ^ convolutional
^
f2[k-1] Z f2[k] encoder

^
{ f1[k-1], 0 }
prepare
if CRC[i-1] is OK feedback
~ ~ (Two-pass)
{ f1[k-1], f2[k] } ^ ^
detector 2 { f1[k-1], f2[k]}
(Two-pass) -1 ^
0Z f2[k-1]
^ ^
Z -1 { f1[k-1], f2[k-1] } (Class 2 only)
detector 3
~ ~ (Three-pass) ^ ^
{ f1[k-2], f2[k-1] }
{ f1[k-2], f2[k-1] }
prepare
if (CRC[i-1] is OK & CRC[i-2] is OK) feedback
^ ^
{ f1[k-2], f2[k-1] } (Three-pass)

^ -1 ^
f1[k-2] Z f1[k-1]

Figure 4. The multi-pass re-detection scheme

The multi-pass equalizer consists of a modified REQU with several

instances of the Demod module extended with a channel decoder, a non-
interleaving channel encoder and special routines for extracting class 1
information from the re-encoded sequence. As is, this system simulates
both the two- and three-pass equalizer and a combination of these two,
the composite multi-pass equalizer.

2.1 The one-pass demodulator

The one pass demodulator consists of the Demod module running in
one-pass detector modus, i.e. it makes no use of information on the error
corrected class 1 data bits. Different metrics may be used even though
the Euclidean distance metric (SqViterbi) were used in the simulations.
Thus a prefilter Viterbi equalizer, PFVE, can be used to detect the class 1
data bits together with the first estimated class 2 data bits.

2.2 The channel decoder

We use the usual channel decoder in our implementation. What we are
interested in here is the class 1 data together with the CRC check flag.
Even though we can not prevent the other parts of the multi-pass equal-
izer from being executed in SysSim when the CRC check fails, the gen-
eral idea is to only initiate the multi-pass equalizer scheme when we are
reasonably sure of having detected the class 1 data bits correctly. For this

6(19)
purpose we use the CRC check flag from the decoder. Keep in mind
though that the CRC check involves the class 1a bits only. There is an
inherent problem with this because we may use incorrect information on
class 1b bits when we experience (heavy) garbling of class 1b bits with-
out having a CRC fail situation for the class 1a bits.

2.3 The channel encoder

After decoding a frame from the ordinary demodulator/detector we re-
encode it under the assumption of having received all class 1 bits cor-
rectly. Observe that the usual interleaving is omitted to avoid a time
delay.

2.4 The index calculators

The index calculator codes all channel encoded class 1 data bits, or a par-
tition thereof, received from the channel encoder in such a manner that
all zeros are converted to -1 and all ones are converted to +1 while at the
same time setting all class 2, SACCH and CDVCC bits to zero. Also it
inserts zeros in place of the synchronization word. This results in a 312
bit vector reflecting all data bits in the received frame, i.e. 16 bits UCH,
28 bits SYNC, 122 bits UCH, 12 bits SACCH, 12 bits CDVCC and 122 bits
UCH. When the CRC check is non-affirmative, the index calculator
delivers all zeros, reflecting that no information is supplied for the corre-
sponding frame. The two-pass index-calculator sets every second row to
zero to indicate the lack of knowledge of these bits due to the interleav-
ing. The three-pass index-calculator interleaves the current burst with
the previous to create a frame, which produces a time-delay. The two-
pass index calculator only considers the CRC for the current frame,
while the three-pass index calculator also has demands for an affirma-
tive CRC for the previous frame.

2.5 The two- and three-pass detectors

When re-detecting B[k] consisting of the parts {c1[k-1], c2[k]} the frame
C[k-1] holding {c1[k-1], c2[k-1]} has been produced by the second
encoder, see Figure 4. Thus only the class 1 bits in the fraction c1[k-1] can
be used as known. The three-pass re-detection holds a time-delay which
implies that when re-detecting B[k] both C[k-1] and then C[k] have been
produced by the second encoder. All class 1 bits can be used as known,
where c1[k-1] is taken from C[k-1] and c2[k] from C[k]. See Figures 4 and
7.

The two pass detector makes use of information on class 1 data bits com-
puted in the one-pass detector and converted during the process of
channel encoding and index calculation (see above). Only the Euclidean
distance metric Viterbi is modified to make use of this information and
the two- and three-pass detectors may only be run in this mode. The
idea is that given information on convolutional- and block coded class 1

7(19)
data bits, i.e. data bits that we may check for correctness, we prune the
trellis to reflect that we for some samples know what phase shifts should
occur and thus may increase the ability to detect the intermingling class
2 data bits correctly. In the actual pruning process we use the 312 bit
index vector, that is aligned with the 312 bit information part of the
received frame, while processing the received signal. At all locations in
the index vector where the value differ from zero, i.e. positions held by
known bits, we assume we know these bits with absolute certainty thus
setting the specific ∆-metrics to infinity. This forces the Viterbi algorithm
to exclude all paths not corresponding to the known phase shifts
through the trellis.

In the three-pass case we perform a regular interleaving after having

encoded the data. The received frame on which the re-detection process
is initiated must therefore be delayed one frame. All class 1 bits are con-
sidered to be known in this scheme.

The composite multi-pass detector combines the class 2 bits from the
two-pass detector and the three-pass detector. The class 1 bits are taken
from the one-pass receiver. After having received B[k] by the one-pass
receiver, both a re-detection of B[k] by the two-pass detector and a re-
detection of B[k-1] by the three-pass detector, is initiated. From these two
re-detected bursts the class 2 bits are taken to form the class 2 bits frac-
tion of F[k-1]. B[k], holds {c1[k-1], c2[k]} and B[k-1], holds {c1[k-2], c2[k-1]}
thus the class 2 bits of c1[k-1] are taken from the two-pass detector and
the class 2 bits of c2[k-1] are taken from the three-pass detector, see Fig-
ures 4 and 7.

For a further discussion on this subject, please see [4].

2.5.1 The restraining of the trellis implemented in the two- and

three-pass detectors
The detection is done by means of a coherent Viterbi equalizer with a
subsequent differential decoder, implying coherent symbol detection
with the aid of the trellis, and then differential decoding of the coherent
symbols.

In differential quadrature phase shift keying (DQPSK), as used in D-

AMPS, the information lies in the differential phase shifts rather than in
the absolute phase of the signal. A set of information bits correspond to
a certain phase shift, see Figure 5.

If we, prior to detecting a differential symbol, have knowledge of one

or both of the corresponding bits we may restrain, or prune, the (number
of) transitions in the trellis.
Since some causes to an erroneous detection have been left out by
means of the pruning, we may re-detect a differential symbol with an

8(19)
 Q

π/2 ~ (-1,1)

(-1,-1) ~ 0

I
(1,-1) ~ 3π/2
π ~ (1,1)

Figure 5. A symbol represented by two bits

increased possibility of making the correct decision. In the specific envi-

ronment of IS-54 we experience both fully known and partially known
symbols. Due to unequal protection of transmitted bits, we may use the
protected bits, if they are successfully received, for restraining the trellis
in a subsequent re-detection of bits with no protection. Based upon the
depth of the interleaving scheme employed, such a re-detection may be
performed on the currently received burst, or on previously received
bursts. Also the effectiveness of this multi-pass re-detection scheme is
dependent on the intra-burst interleaving employed. From the point of
view of this method, the performance gain is dependent of the pattern of
interspersing (fully or partially) known symbols among unknown sym-
bols (symbols with a lower degree of error protection).

2.5.2 The influence that the restraining has on the trellis

The detector is a TS/2 fractionally spaced maximum likelihood
sequence estimator (MLSE), with a 4-state Viterbi algorithm (VA). In the
two-pass and three-pass detectors the trellises of the VA are forced to
take predestinated paths corresponding to known class 1 bits. The differ-
ential detection of the DQPSK signal is implemented by a coherent Vit-
erbi detector with a subsequent differential decoder. This implies that
parallel transitions in the trellis are equal since they represent an equal
difference in phase. If bits corresponding to a certain phase shift are
known, the trellis is restrained so that only transitions corresponding to
this known phase shift are allowed. Due to this, the quick merge of
nodes in the two- and three-pass detectors are prevented where the trel-
lises are pruned. Instead, the paths are forced apart.

9(19)
3 Calculation of bit errors
No “physical” speech-frame is assembled in this implementation. Based
on the CRC check from the one-pass channel decoder, we choose to
count bit errors either from the two-/three-pass channel decoder (when
CRC is affirmative) or from the one-pass channel decoders. If, for
instance, this system should be used to produce “physical” frames, e.g.
with “real” speech-coded signals, code would have to be written to
assemble frames. The present code is found in mpass_ber_calc.C.

4 Parameters defining multi-pass operation

A proper template file for simparam execution of the multi-pass equalizer
is found in the file named mpass_dvc.it. See also Section 7.

10(19)
5 References
[1] P. Dent, “Invention disclosure of Decodulation,” Internal Document
Ericsson-General Electric, RTP/EGE/CT/Y 93:0009, May 1993.
[2] K. Jamal, “Equalization for the ADC standard,” Internal report T/U
91:260, 1991.
[3] K. Jamal, “Fractionally Spaced Viterbi Equalization,” Internal report
T/BU 92:075, 1992.
[4] P. Deutgen & F. Randers, “Forward-Error-Control-Assisted Detec-
tion,” Master’s Thesis 1994:149E, Luleå University of Technology,
Div. of Signal Processing, 1994.

11(19)
6 The SysSim simulation model

6.1 The top layer

rndInt rndCarr dcet

rnd_source rnd_source mod_dcet
int RATE=1 int RATE=1 int RATE=1
int seed=564523624 int seed=230547080 bool PartOfDecodulator=FALSE
int blocklength=284 outFrame int blocklength=159 outFrame inFrame int facchFlag=0 outFrameNew
int dvccPar=10
int oblocklength=284
int iblocklength=159 outFrame

dmtCarr rattxCarr
dmt_sim rattx
int RATE=1 int RATE=1
dmtInt float offset_q=0 int blocklength=1584
inFrame float gain_q=1 outFrame inFrame int SAMPLERATE=194400 outFrame
dmt_sim float offset_i=0
float gain_i=1
int RATE=1 int startTA=0
float offset_q=0 int timeAlign=0
inFrame float gain_q=1 outFrame int startGuard=30
float offset_i=0 int dvccPar=10
float gain_i=1 int syncNr=1
int startTA=0 int burst_mode=1
int timeAlign=0 int filter_mode=1
int startGuard=30 int upsa=4
int dvccPar=10 bool imp_model=TRUE
int syncNr=2 float bt=0.2
int burst_mode=1 float window_offset=0
int filter_mode=1 float beta=0
int upsa=4 float alpha=0.35
bool imp_model=FALSE float imp_length=12
float bt=0.2 float ampl=5100
float window_offset=0 SimStr inFileName="dmt/test/wfg_filter.dat"
float beta=0 int oblocklength=1584
float alpha=0.35 int iblocklength=284
float imp_length=10
float ampl=5150
rach
SimStr inFileName="dmt/test/wfg_filter.dat"
int oblocklength=1584 rach
int iblocklength=284
rattxInt
int RATE=1
rattx float SAMPLERATE=194400
rachIn rachOut
int RATE=1
int blocklength=1584
inFrame int SAMPLERATE=194400 outFrame rachIn1 rachOut1

ratrxA dfiltA
ratrx dfilt
pdigtA
int RATE=1 int RATE=1
int SEED=1986921971
pdigt
inFrame int blocklength=1584 rssout rss outFrame
int RATE=1
double maxOut=256
iqout inFrame int outBits=0 outFrame phi
int blocklength=1584

ratrxB dfiltB
ratrx dfilt
pdigtB
int RATE=1 int RATE=1
int SEED=1202277023 pdigt
inFrame int blocklength=1584 rssout rss outFrame
int RATE=1
double maxOut=256
iqout inFrame int outBits=0 outFrame phi
int blocklength=1584

ber_calc
ber_calc
int RATE=1

dequdect source_in
equdec
coded_in
int RATE=1

in_frame_A detected_frame_one detected_frame_one

in_frame_B detected_frame_two detected_frame_two

detected_frame_three detected_frame_three

uch_frame_one uch_frame_one

uch_frame_two uch_frame_two

uch_frame_three uch_frame_three

facch_frame_one facch_frame_one

sacch_frame_one sacch_frame_one

data_crc_flag_one data_crc_flag_one

data_crc_flag_two data_crc_flag_two

This is the top model of the data_crc_flag_three data_crc_flag_three

multi-pass simulation chain,

sacch_crc_flag_one sacch_crc_flag_one
based upon the SysSim chain
for dvc_1.29. dvcc_status_one dvcc_status_one

ber_estimate_one ber_estimate_one

Figure 6.

12(19)
 This is part of the model for the
FEEDBACK
multi-pass simulation chain.
6.2 The REQU

prphiA syncA mpass_equ

processrphi synchronize mpass_equ
crphiA @
int RATE=1 int RATE=1 int RATE=1
computerphi int AFCMode=0 float WeightFactor=1.05 equdec
fe_est_in int AGCMode=1 r_out r float SyncLp=0.02 start_sample start_sample_A fe_est_frame_A
int RATE=1 int blocklength=1584 float MuGainLimit=1000 int RATE=
int ConversionMode=1 float MuSlope=0.08
y int blocklength=1584 r r_in phi_out phi float CorrMin=30 h_init h_init_A detected_frame_one in_frame_A detected_frame_one
int NmbSncWds=1
int SncNmbNxt=2
phi phi_in int SncNmb=1 tap_gains tap_gains_A detected_frame_two in_frame_B detected_frame_two
int MuMapping=0
int MuAlpha=1
int FloatWnd=0 direction direction_A detected_frame_three detected_frame_three
int WndLen=32
int NmbHTaps=
int ExpectedPos=244 in_frame_phi_A uch_frame_one uch_frame_one
int DownSampFactor=1
int CorrelationMode=1
int FseFactor= in_frame_r_A uch_frame_two uch_frame_two
int filterlength=20
int blocklength=1584
prphiB syncB in_frame_r_B uch_frame_three uch_frame_three

13(19)
processrphi synchronize

Figure 7.
crphiB in_frame_phi_B facch_frame_one facch_frame_one
int RATE=1 int RATE=1
computerphi int AFCMode=0 float WeightFactor=1.05
fe_est_in int AGCMode=1 r_out r float SyncLp=0.02 start_sample start_sample_B sacch_frame_one sacch_frame_one
int RATE=1 int blocklength=1584 float MuGainLimit=1000
int ConversionMode=1 float MuSlope=0.08
y int blocklength=1584 r r_in phi_out phi float CorrMin=30 h_init h_init_B data_crc_flag_one data_crc_flag_one
int NmbSncWds=1
int SncNmbNxt=2
phi phi_in int SncNmb=1 tap_gains tap_gains_B data_crc_flag_two data_crc_flag_two
int MuMapping=0
int MuAlpha=1
int FloatWnd=0 direction direction_B data_crc_flag_three data_crc_flag_three
int WndLen=32
int NmbHTaps=
int ExpectedPos=244 sacch_crc_flag_one sacch_crc_flag_one
int DownSampFactor=1
int CorrelationMode=1
int FseFactor= dvcc_status_one dvcc_status_one
int filterlength=20
int blocklength=1584
ber_estimate_one ber_estimate_one

fe_est_frame_B

FEEDBACK
 one_pass_ddt one_pass_dcdt noninterl_dcet
mpass_demod dcdt_sim mpass_dcet
int RATE=1 int RATE=1 int RATE=1
float ExpectedFeEst=0 int individ=1 bool DECODULATOR=TRUE
index_frame float Afc3=0.1 out_frame_det inFrame int interMix=0 speechFrame inFrame outFrame
float Afc2=0.001 bool facchFlag=FALSE @
float Afc1=0.01 int dvccPar=10
in_frame_r_A int Afc5=3 fe_est_frame_A int softLim=12 facchFrame mpass_equ
int Afc4=50 int noSoftBits=10
int AfcMode=0 int softCh=1
int RATE=
in_frame_phi_A float MuMpl=0.033 fe_est_frame_B int burstMode=1 sacchFrame
float Mu=0.15 int simMode=0 dummy_index
start_sample_A fe_est_frame_A
float Wd=0.02
start_sample_A float Rd=0.995 dataCrcFlag rnd_source
float Gamma=0.0001
h_init_A detected_frame_one
float IsiLp=0.02 int RATE=1
h_init_A int CdvccNmb=10 sacchCrcFlag int seed=1994
int SncNmb=1 int blocklength=1 outFrame
tap_gains_A detected_frame_two
int StartGuard=30
tap_gains_A int FeedbackMode=1 dvccStatus
int PassNmb=1
direction_A detected_frame_three
int ExpandedMode=0
direction_A int AdaptationMode=1 berEstimate
int NmbDivCh=2 three_pass_index_calc in_frame_phi_A uch_frame_one
int DecDelay=4
in_frame_r_B int UpdDelay=2 index_calc
int SLength=1 multi-pass simulation chain. in_frame_r_A uch_frame_two
int NmbHTaps=4
int RATE=1
in_frame_phi_B int FseFactor=2
This is part of the model for the

int IndexData=1
bool VDD=FALSE
inCRCFromOnePass
int PassSelector=3 outIndexBitsFrame in_frame_r_B uch_frame_three
bool Soft=TRUE
int oframelength=312
start_sample_B bool Weighting=TRUE
int iframelength=284
bool Prediction=TRUE
inCodedBitsFrame in_frame_phi_B facch_frame_one
6.3 The multi-pass equalizer

int oblocklength=284
h_init_B int filterlength=20
int iblocklength=1584
two_pass_index_calc start_sample_B sacch_frame_one
int indexlength=1
tap_gains_B
index_calc
h_init_B data_crc_flag_one
direction_B int RATE=1
int IndexData=1
tap_gains_B data_crc_flag_two
inCRCFromOnePass
int PassSelector=2 outIndexBitsFrame
From model input
int oframelength=312
int iframelength=284
direction_B data_crc_flag_three
inCodedBitsFrame

14(19)
Figure 8.
three_pass_ddt sacch_crc_flag_one
two_pass_ddt two_pass_dcdt
ddt mpass_dcdt ddt
three_pass_delay dvcc_status_one
From model input
int RATE=1
int RATE=1 int RATE=1 three_pass_delay int PASS_SELECTOR=3
int PASS_SELECTOR=2 int PASS_SELECTOR=2 ber_estimate_one
indexFrame int EXPANDED_MODE=3 outFrameDet
indexFrame int EXPANDED_MODE=3 outFrameDet detected_frame decoded_frame
int RATE=1 int INDEX_LENGTH=312
int INDEX_LENGTH=312
int filterlength=20
fe_est_frame_B
inFrameRA int blocklength=1584 outFrameRA inFrameRA
inFrameRA data_crc_flag

inFramePhiA outFramePhiA inFramePhiA

inFramePhiA

instartSampleA outstartSampleAstartSampleA
startSampleA

inhInitA outhInitA hInitA

hInitA

intapGainsA outtapGainsA tapGainsA

tapGainsA

indirectionA outdirectionA directionA

directionA three_pass_dcdt
inFrameRB outFrameRB inFrameRB mpass_dcdt
inFrameRB
int RATE=1
inFramePhiB outFramePhiB inFramePhiB int PASS_SELECTOR=3
inFramePhiB
detected_frame decoded_frame

instartSampleB outstartSampleBstartSampleB
startSampleB
data_crc_flag

inhInitB outhInitB hInitB

hInitB

intapGainsB outtapGainsB tapGainsB

tapGainsB

indirectionB outdirectionB directionB

directionB

From model input

6.4 Bit error calculation

one_pass_ber_calc
ber_calc_xl
int RATE=1
int dvccPar=10
sourceIn int burstMode=1
bool facchFlag=0
int statInterval=200
codedIn int skipNr=100
int errDataOut=0

modemIn

decodedIn

facchIn

This is part of the model for the

sacchIn
multi-pass simulation chain.
dataCrcFlag

sacchCrcFlag

dvccStatus

berEstimate

@
ber_calc
two_pass_ber_calc
int RATE=
mpass_ber_calc
source_in
int RATE=1
int PassSelector=2
coded_in sourceIn int burstMode=1
int statInterval=200
int skipNr=100
detected_frame_one codedIn int errDataOut=0

detected_frame_two modemInOne

detected_frame_three modemIn

uch_frame_one decodedInOne

uch_frame_two decodedIn

uch_frame_three dataCrcFlagOne

facch_frame_one dataCrcFlag

sacch_frame_one berEstimate

data_crc_flag_one

data_crc_flag_two

data_crc_flag_three

sacch_crc_flag_one

dvcc_status_one
three_pass_delay three_pass_ber_calc
ber_estimate_one
ber_calc_delay mpass_ber_calc
int RATE=1 int RATE=1
int PassSelector=3
sourceIn sourceOut sourceIn int burstMode=1
int statInterval=200
int skipNr=100
codedIn codedOut codedIn int errDataOut=0

modemIn modemOut modemInOne

decodedIn decodedOut modemIn

dataCrcFlag dataCrcFlagOut decodedInOne

berEstimate berEstimateOut decodedIn

dataCrcFlagOne
Eat_CRC
dummysink_i dataCrcFlag

int RATE= 1
bool debug=FALSE berEstimate
inFrame int blocklength=1

Figure 9.

15(19)
7 Templates for simulation

7.1 The simparam parameters file

FADE 7 77
TAU 0 2 4 8
CIR 4 5 8 10 12 14 16 18
SNR 35
FREQ_ERR 0
CH_SEP 0
STEP 3101

7.2 The simparam template file

sim build

/* Set RATE */

set **/RATE 1

/* Set simulation parameters */

set **/DOPPLERFREQ FADE

set **/dopplerFreq FADE
set **/snrDb SNR
set **/cOverIdB1 CIR
set **/delay TAU
set **/ST1/freqErr FREQ_ERR
set **/channelSep1 CH_SEP

/* Set other parameters */

set /LogStat/SimName SIM_NAME
set /LogStat/SimRunName SIM_RUN_NAME
set /LogStat/ResultPathName RESULT_PATH_NAME

set /mpass_dvc/ratrx?/mf1/INFILENAME “rat/filter/

butt4_165e2_194e3.hz”
set /mpass_dvc/ratrx?/mf2/INFILENAME “rat/filter/
iir2gaus3_194e3.hz”

cd /mpass_dvc/dfiltA
source dfilt/dfilt.ini
cd /mpass_dvc/dfiltB
source dfilt/dfilt.ini
cd /

/*---------------------------------------------------
Parameters used to force dfilt to produce (i,q)
samples,i.e. carthesian complex samples instead of any
obfuscated (rss,phi) samples that we would have to

16(19)
invert anyway.
*--------------------------------------------------*/
set /mpass_dvc/dfiltA/t2/bypass TRUE
set /mpass_dvc/dfiltA/t2/eqmode FALSE
set /mpass_dvc/dfiltB/t2/bypass TRUE
set /mpass_dvc/dfiltB/t2/eqmode FALSE

/*---------------------------------------------------
Parameters used to force dfilt to skip the suspicious
“ladder”-mode. Instead we use a simple filter which
only amplifies the signal with a constant gain = b0
*--------------------------------------------------*/
set /mpass_dvc/dfilt?/mf22/bypass FALSE
set /mpass_dvc/dfilt?/mf22/ladderMode FALSE
set /mpass_dvc/dfilt?/mf22/b0 1000

/*---------------------------------------------------
The correlation between the carrier and the interferer
in the two ray model. This together with the amplitude
of the interferer relative the carrier ‘amplitude’ may
be used to simulate a flat non fading channel
(correlation=1, amplitude=”-200”).
See below for FADE == 0.
*--------------------------------------------------*/
set **/CORR/correlation 0.7

/*---------------------------------------------------
Statistical interval is now set to 200. That means
that the number of simulations will be broken down
into small pieces on which we may build more robust
statistics
*--------------------------------------------------*/
set **/statInterval 200
set **/COVERICHA/skipNr 100
set **/COVERICHB/skipNr 100
set **/TXCMOD/skipNr 100

/*---------------------------------------------------
Since dmt comprises a program written in pascal as
well as one written in C++, neither one being possible
to instantiate, we must choose different models for
the modulator of the carrier and the modulator of the
interferer. For the carrier we choose the C++ model
(implementation model TRUE) and for the interferer the
Pascal program (implementation model FALSE).
*--------------------------------------------------*/
set /mpass_dvc/dmtCarr/imp_model True
set /mpass_dvc/dmtCarr/imp_length 12
set /mpass_dvc/dmtCarr/ampl 5100
set /mpass_dvc/dmtInt/ampl 5150

/* Set dequdect parameters */

cd /mpass_dvc/dequdect

17(19)
set crphi?/ConversionMode 1
set prphi?/AGCMode 1
set sync?/FseFactor 2
set sync?/ExpectedPos 244
set sync?/CorrelationMode 1
set sync?/WndLen 32
set sync?/WeightFactor 1.5

/* Set mpass_equ parameters */

cd /mpass_dvc/dequdect/mpass_equ/one_pass_ddt
set Weighting TRUE
set IsiLp 0.02
set FeedbackMode 1
set FseFactor 2
set NmbDivCh 2
set ExpandedMode 0
set SLength 1

cd /mpass_dvc/dequdect/mpass_equ/two_pass_ddt/demod
set Weighting TRUE
set IsiLp 0.02
set FeedbackMode 1
set FseFactor 2
set NmbDivCh 2
set ExpandedMode 3
set SLength 1

cd /mpass_dvc/dequdect/mpass_equ/three_pass_ddt/demod
set Weighting TRUE
set IsiLp 0.02
set FeedbackMode 1
set FseFactor 2
set NmbDivCh 2
set ExpandedMode 3
set SLength 1

cd /

/* BER calculation */

set **/errDataOut 0
set **/statInterval 200
set **/skipNr 100

cd /mpass_dvc/ber_calc
set one_pass_ber_calc/skipNr 100
set two_pass_ber_calc/skipNr 100
set three_pass_ber_calc/skipNr 101
cd /

#if FADE==0
set **/CORR/correlation 1.0
set **/amplitude “-200”

18(19)
 set **/statInterval 200
#endif

#if FADE==7
set **/statInterval 500
#endif

#if FADE==77
set **/statInterval 200
#endif

sim cons

/* Simulate */
sim start
s
s STEP
sim stop
exit

19(19)