Chapt. 11 I/O & DMA p.

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Chapter 11. I/O - DMA

The purpose of a processor is to perform actions on data. This data should be send to the CPU and
the result should be stored somewhere.
The microprocessor only has the CPU on the chip: the input and output elements, as is the memory,
are located externally. It is obvious that all data transferts with the external world will be carried
over the data, address and control busses.



The microcontroller not only contains the CPU, but also the input/outputs elements are on the same
chip. The external world is directly coupled to the pins of the microcontroller.

CPU
I/O Control
and Status
registers
ROM
RAM
EEPROM
I/O Data
registers
I/O Ports
V
DD
Control Lines
Clock
Microcontroller Chip - Single Chip Mode
Internal Data Bus



Control
Sequencer
ALU
Instruction Decoder
CPU Registers
Program Counter
Address Register
Data Driver
Control Signals
Clock
External Address Bus External Data Bus
Microprocessor
CPU Block
Diagram
Chapt. 11 I/O & DMA p. 2 / 8

The combination of microprocessor and microcontroller is also possible : the chip contains, apart
from the CPU, a (small) amount of memory and input/output. For the easier jobs the device can be
used as a microcontroller. The heavy jobs (more memory requirements) will require to put the chip
into microprocessor mode : the address and data bus now appears on the pins of the chip (thereby
removing the input/output pins) and large external memory can be accessed.

Control Lines
CPU
I/O Control
and Status
registers
ROM
RAM
EEPROM
I/O Data
registers
V
DD
V
SS
Clock
Microcontroller Chip - Expanded Mode
Internal Data Bus
Data Buffer
Address Latch

To save in the number of pins the databus will have a double use. In principle an 8 bit processor re-
quires an 8 bit databus and a 16 bit addressbus. To save pins, only one 8 bit address bus will be im-
plemented. Due to the von Neumann and the pipelining concepts one can transfert the 8 highest ad-
dressbits over the address bus while the 8 lowest addressbits are sent over the databus ! The lowest
addressbits should be externally saved into a latch. The processor is generating the ALE (address
latch enable, Intel) or the AS (address strobe, Motorola) signal to control the activity of this exter-
nal latch. Afterwards, the effective data byte will be transferred.

Chapt. 11 I/O & DMA p. 3 / 8



The combination of stand-alone or extended mode requires that the externally available memory
fits into available memory areas. As an example consider the case where intenal RAM is located
at address $0000-$00FF, internal EPROM is at $B600-$B7FF and internal ROM is at $E000 -
$FFFF. A lot of decoding is required to fit the external memory in the available locations.
A PAL22V10 is urgently needed for address decoding.

$0000
$00FF
$1000
$103F
$B600
$B7FF
$E000
$FFFF
Memory Map: Single
Chip Mode
Expanded/Multiplexed
Mode
Not Available
External
Not Available External
Not Available External
256 Byte RAM
512 Byte EEPROM
8K ROM


The standard microprocessors dont have directly I/O systems on chip, but as mentioned before, the
manufactures have tens and tens of external peripheral components which could be directly
plugged on the busses (data, address, control). The newer generation of microcontrollers have these
peripheral components on-board. As a matter of fact, the programmer doesnt care if his/here pe-
ripherals are internal or external.
Chapt. 11 I/O & DMA p. 4 / 8

Polled vs. Interrupt Driven I/O (vs. DMA)

Polled I/O
In this mode the CPU has to check regulary if an event or whatsover has occurred on the I/O sec-
tion. This event is marked by the setting of a given flag in one register or another. This way of deal-
ing with inputs is cheap in hardware and fits the CPU if its loading is not too high.

Interrupt I/O
The CPU is interrupted by the I/O event. The handling is done directly (if allowed to do so). Extra
hardware is needed for the interrupt logic.

DMA I/O
The 3th possibility will be seen next. It requires minimum CPU overhead but is expensive in hard-
ware.

Memory Mapped vs. Peripheral (I/O) Mapped I/O

Memory Mapped I/O

The control, status and dataregisters of the I/O elements are part of the regular memory. The pro-
grammer only sees memory and can treat the I/O registers just as if they are locations for normal
variables. These registers can be manipulated with the normal instructions. A requirement is that
the accesstime should be similar as the memory access time. If not, wait states

should be generated.
Peripheral Mapped I/O

The control, status and data registers of the I/O elements have their own address space. The CPU
will generate an extra control signal to indicate if the address is to be used for memory or for I/O.
The I/O address range is mostly much smaller than the memory range.
Specific I/O instructions are available to access the I/O registers. The architecture is not orthogo-
nalThe advantage of a separte I/O space is that the shorter I/O address will result in a faster I/O
response. Also, the use of extra wait states is somewhat simplified.

Some processors with memory mapped I/O are able to dynamically change the location of the I/O
area into memory space. If required Page Zero (fast access time) could be used for that purpose.

Wait States
The microprocessor is a synchronous system. Every memory (or I/O) access will normally take a
fixed number of clock pulses. As such, memory or peripherals should be matched to each other. A
fast processor will require fast memory (or peripherals).
Sometimes only slow peripherals (or memory, eg. Flash) are available. One possibility would be to
reduce the clock speed of the processor. That would be most regrettable because eventually the pe-
ripheral would be accessed only from time to time and the whole system would be penalized by
running slower all the time.
A much better solution is to make use of wait states. Practically every microprocessor has a WAIT
input. During every external access the CPU will check if the wait input is active or not. An active
wait input means that the peripheral or memory is not ready yet and the processor will automati-
cally add extra clock cycles during the external access. During these extra clock pulses no other
CPU activity is performed, just waiting. Once the peripheral releases the WAIT input (meaning that
it has accepted the access) the processor will quit the external access and will continue its execution
at high speed.
Chapt. 11 I/O & DMA p. 5 / 8

DMA

The loading or storing of data (from memory or peripheral) occurs under control of the CPU. Load-
ing data means that a read instruction will be executed which copies data from external to the ac-
cumulator. Eventually some actions will be executed on the data before the data is stored in mem-
ory. The transfert of data is passing through the accumulator and requires some instructions.
A lot of I/O elements require the transfert form peripheral to memory without being processed in
between. (cfr reading from hard disk).



Such a transfert could be executed much faster by hardware. This requires that the processor could
completely release the busses to a hardware controller which is now taking care of the busses. This
controller will now generate the required addresses.
This action is performed by a Direct Memory Access (DMA) Controller. This controller typically
contains 3 registers which are setup by the software : the Source Register indicating the address of
the incomming data, the Destination Register indicating the target of the data and a word counter
keeping track of the number of transferts.

Chapt. 11 I/O & DMA p. 6 / 8


A data register is optional. Mostly the DMA controller has to temporary buffer the data (and even-
tually perform some elementary action on it), sometimes no buffering is needed and data is going
directly from source to destination.


Flowthrough DMA
The DMA performs 2 actions: 1. reading data from source
(and buffering in DMA Data register)
2. writing data to destination
(from DMA Data register)

This method is easiest to implement in hardware because it is similar to the normal CPU operation.
Two cycli per transfert are needed (read +write).
But eventually these 2 cycles could be executed in only 2 clock cycles.



Chapt. 11 I/O & DMA p. 7 / 8


Flyby DMA
In one cycle the DMA controller will generate the memory address and data will flow between pe-
ripheral and memory. No data is going through the DMA controller. Because only one address can
be generated in one cycle transferts are between memory (changing addresses) and peripheral
(fixed address).


The DMA could be :

memory <>I/O the memory address will be updated per transfert (+or -)
the I/O address remains fixed

I/O <>I/O both I/O addresses (source, destination) are fixed.

memory <>memory both addresses will be adapted per transfert.
(no flyby possible)

It is obvious that during DMA the CPU will be on non-active, although :

* burst mode : during a short time, the DMA will do a burst of transferts.
This method can always be implemented. The speed of transfert is controlled by the DMA, the I/O
and the memory. The speed of the CPU is of no importance.

* cycle stealing : the DMA controller steals a memory cycle from the CPU. Only one transfert per
DMA interrupt is possible. The DMA is started and will be active during an internal memory cycle.
If the CPU requires the external bus it has to wait till the DMA cycle is finished.

* transparant transfert : the DMA is running simultaneously with the CPU. Some processors allow
that during some cycles per instruction the bus is used by external devices (DMA). The DMA is ir-
regular : some instructions (with sufficinet free memory cycles) allow for DMA, others dont.

The availability of a cache (data, instruction) allows for an easy simultaneous operation of DMA
Chapt. 11 I/O & DMA p. 8 / 8

and CPU.
BUS Arbitration

Normally the CPU has ownership of the busses (address, data, control) . If an external device re-
quires ownership it will need to handshake with the CPU to change ownership. There are a lot of
possibilities for this handshaking. An easy one is explained :
The signals Bus Request (/BREQ) and Bus Acknowledge (/BACK) are needed :


Timing :
1. the DMA controller request the bus : /BREQ ='0'

2. (eventually) the CPU accepts this request : /BACK ='0'

3. DMA has ownership

4. the DMA has finished its action, no bus needed /BREQ ='1'

5. the CPU takes over control /BACK ='1'