Cadence User Tutorial

Version 1.2 September 18, 2004

Modified and Tested by Zhengming Fu Jian Xu Electrical Engineering Department Yale University This is modification and adaptation from JHU Cadence Tutorial at http://bach.ece.jhu.edu/cadence/

Table of Contents

1. Conventions Used in this manual 2. Starting the Cadence software 3. Opening and Using the Library Manager 4. Design Hierarchy 5. Quitting the Session 6. Creating a new library 7. Creating a new Cell: Inverter 8. Schematic Simulation: Transient Analysis with manual stimuli input 9. Printing your Schematic 10. Creating Symbols: Inverter Symbol 11. Schematic Simulation: Creating a Test File for Simulating an Inverter 12. Spice simulation: DC Analysis of The Inverter 13. Schematic Simulation: Transient Analysis of The Inverter 14. Layout: Creating Layout for an Inverter 15. Design Rule Check (DRC) 16. Layout Extraction 17. Layout Versus Schematic (LVS) 18. Layout Simulation: Transient Analysis APPENDIX A APPENDIX B CADENCE SETUP CONFIGURATION LSW Display File Merge

1. Conventions Used in this manual

There will be several conventions used in this manual. The mouse on the Sun machines has three (3) buttons. The following is some terminology I will use in relation to mouse operations: "Click left" - press and release the left mouse button (quickly) "Click right" - press and release the right mouse button (quickly) "Click middle" - press and release the middle mouse button (quickly) "Drag left" - press and hold the left mouse button while moving the mouse. "Drag right" - press and hold the right mouse button while moving the mouse. "Drag middle" - press and hold the middle mouse button while moving the mouse. "<...>" - press the key on the keyboard that corresponds to what is inside the <>'s "type whatever" - you should type (verbatim) whatever is in boldfaced print

2. Starting the Cadence software

Before you run cadence, you need to configure the necessary environment files and techfiles into your loca home directory. The configuration details are listed in the APENDIX A. Please do it when you firstly use Cadence or you want to make a fresh copy of Cadence configuration. When you are ready to run the Cadence software put the mouse cursor into the X-terminal in which you logged in & set your environment by typing csh. After you login with C-shell, go to the ~/cdscad directory then type msfb&. NOTE: All the cadence LINUX environment are set under C-shell. All the cadence default settings are put under ~/cdscad. Those files include .cdsinit, .cdslocal, .cdsplot. cdsenv. If you are experienced user, you could use text editor to change the Cadence configuration by change those files. All the techfiles and rules checking files are under ~/cdscad/techfiles. Please do not alter files under this directory. This will start the Cadence design software. If all works well, you will see a window similar to the one below.

Why did we type an '&' after the command? The '&' put the design manager into the background so that you can still use the command window in which you typed the command. If you had not done that, you would not be able to type any new commands in the window. You would have had to open a new window and log into your remote machine through this window to do anything else on that machine. This window is called the Command Interpreter Window (CIW). This window represents the Design Framework II environment, and provides access to Cadence through its menus, or its input line using SKILL commands. The CIW window is the control window for the cadence software,

Opening and Using the Library Manager

One of the simple ways to navigate through the libraries (Both the Cadence defaults, and your own custom ones) is to use the Library Manager. A library is a collection of cells, such as NOT, AND, NAND, etc. By the end of the semester, you should have full representations of most primitive gates and few complex cells. These cells contain several views, including schematic, layout, extracted, symbol, etc. Some added conventions that will be used are as follows: click CIW:Tools -> Library Manager -- This means the following: go to the CIW window, left-click once on the Tools Menu, then left-click once on the Library Manager option in the pop-up menu that will appear. Let's get started...click CIW:Tools -> Library Manager Note: Sometimes, the window you are working in isnt big enough to display everything inside of it. When this happens, scroll-bars appear at the bottom, or the sides to allow you to see all of it. On the other hand, you may also change the size of the windowThere are several ways to do this, depending on which best suits your needs. If you double click (left) on the title bar, the window will "explode" to fill your screen vertically, but it wont get any wider. Double click (left) the menu bar (again) will return it to its original size. If you look closely, you will notice that the corners of the window look different than the rest of its borders. Move the mouse cursor over these corners, until the cursor turns into a bull-eye. Once this happens, left click and drag the corner of the window until it is the size you want it to be.

The library manager window should appear in just a few moments. This window should be similar to the one below:

The left column is a list of the current libraries. From these libraries analogLib is of most importance. This library contains all the components used during vlsi circuit design and it will be used the most. Left click on analogLib in the library browser. Left click on nmos4 to display the cell views of the nmos transistor design. You should be able to see several different cell views. The cell views contain the following information: symbol - contains the symbol representation of the schematic. CdsSpice, HspiceS, Spectre, spectreS contain spice information for the element. Feel free to look at any of the cell views. To do this, click center and hold on the cell view and choose read or you can double click on the particular cell view of interest. A window will open showing the contents of that particular window. In different cells, you may encounter the following cell views: abstract - contains an abstract representation of the layout for use by Cadence place and route software. extracted- contains layout connectivity for use by verification programs. layout- contains the silicon-level representations of the transistors and wiring (you'll do this alot!). schematic - contains the logical design of the device. behavioral contains the VHDL description of the cell

3. Design Hierarchy
A hierarchical design is formed by placing copies or instances of cell inside of other cells. The cell at the top includes the whole design (say, a symbol of an inverter) and the cell at the bottom is the layout (the way things are laid out on the silicon). The top cell is given level number zero, while the bottom cell is given the highest level number. Library. Libraries let you organize design data and perform version access and control. A library is a collection of logical design objects, organized in levels as shown: Cell A cell is the basic design object. It forms an individual building block of a chip or system. It is a logical, rather than physical, design object. Each cell has one or more cell views as shown above. Cells can be logically grouped into cell categories. A cell can belong to several cell categories. Cell view A cell view is a virtual data file created in association with a cell and a view. It is a logical, rather than physical, design object.

Note: This hierarchical list may seem confusing, but if you go back to the Library Browser, you will notice that each one correlates to a different level in the libraries. The organization described above can be seen bellow. The Cadence software manages these files transparently. However, because of the relationship between cells, you must use the commands copy, move, and delete within the Cadence software in order to manipulate the different cells. UNIX operating system commands cannot correctly handle these files.

4. Quitting the Session

Left click CIW:File->Exit A dialog box should appear, and asks to confirm the request. Left click OK to exit Cadence, or left click Cancel to resume. If you have any unsaved work, the save cell view form appears with the library, cell and cell view names. Left click on OK after making all the appropriate choices. All Cadence windows will now close, and the design session will end.

5. Creating a new library

After remote login and setting the display, start the Cadence software (type icfb &) and click CIW:Tools -> Library Manager. In the Library Manager click on: File->New->Library A dialog box should appear and you should fill the appropriate boxes as shown in the picture:

You can choose any name for the library. In this case we have chosen digital_lib for the library name. Also the directory were the library is going to be created is ~/cdscad. The Design Manager Use option should be left to No DM. Since this is going to be your personal library, you choose the No DM option. If you are going to work in a group project and you want to share a common library with other users then you can specify the TDM option. You can refer to the Help for more details. Left click the OK button. A new window will appear asking information about the technology file. The default option, Compile a new techfile, will be used. Click on the OK button.

A new window will appear similar to the one bellow. You have to specify the whole path where the technology file is located. The correct path is: ~/cdscad/techfiles/mosis.tf

Click on the OK button. The new technology file will be compiled and placed in the directory where your library is located. Your library is created now and you should be able to locate the new library called digital_lib in your Library Manager. Before you do anything else, you need to define the "lambda" parameter for this library. CIW:Tools: CDF -> Edit Select "Library" and enter "digital_lib" as the Library Name. Select "Base" as the CDF Type. Then click "Add" under Component Parameters. The following window should pop up.

Fill out the form as shown. You need to select "Float" as the paramType, select "Yes" for storeDefault, enter "lambda" as the name, and enter "0.35e-6" as the defValue. Then click OK. The "Edit Component CDF" window should now look like the one below.

Click OK and you have finished creating the library.

6. Creating a new Cell: Inverter

From now on (in mouse operations) we will refer to MC&H for "Middle Click & Hold" for navigating through the Browser menus. Click: Library Manager:New -> Cellview... The create new file form should appear:

Note: The "Library path file" will vary based on your configuration. We will be making an Inverter, so type inv in the Cell Name block. In the View Name block type schematic or from the Tool menu choose Composer-Schematic and the View Name Block will be automatically filled. Left click the OK button. The Virtuoso-Schematic Editing window should be showing on your screen (big & black): Left click: Schematic Editing:Add ->Instance... Type analogLib in the Library Name box. Type nmos4 to choose a four terminal NMOS transistor in the Cell Name box and symbol in the View Name box.. Note that you can use the Browse button in order to browse through the libraries and find the cell you want. The size of the transistor is specified in terms of lambda: the width is 4*lambda; the length is 2*lambda. (M: meter)
1

Shortcuts: You may notice letters by some of these menu choices. Rather than clicking through all the menus, you can just hit that button on the keyboard to the same effect. These are called hot-keys.

Move the cursor into the editing window. Notice that there is an NMOS transistor there instead of the normal cursor. Position it where you want to put the transistor, and left click to place it. You can right click to rotate the transistor if you want it to face a different direction (this is especially useful with pins). Press <Esc> to return to a normal cursor after you have finished placing all the transistors you want. For this inverter example, place it on the bottom half of the screen on the right side of the center-line. Click Editing:Add ->Instance Follow the same steps as before, but choose a pmos4 transistor. Use the same values for length and width. Place the pmos4 transistor somewhere above the nmos4 transistor. To make life easier? Before trying to place a component, left click the Hide button on the Add Component window. This will move it into the background so it?s out of your way. Now, we' II add the pins for the inverter. Click Editing:Add->Pin The Add Pin dialog box comes up. In the Pin Names box enter all the pins: vdd, vss, in and out. Ensure that Direction is set to inputOutput. The Add Pin window should look as follows:

Note that the order of the pin names is not important. You can also name one pin at the time, place the pin on the schematic and repeat the same procedure several times for placing the other pins. The end result will be the same. Following typical electronics conventions, place the vdd pin somewhere near the top of the editing screen, above the PMOS transistor. Then place the vss pin somewhere below the NMOS transistor. Place the in pin somewhere towards the left of the editing window, between the transistors. Place the out pin somewhere towards the right side of the editing window, between the two transistors Now, we'll add all the wires to make this thing work. Click Editing: Add -> Wire(narrow). The Add Wire form should appear. Just click its Hide button. You can refer to the figure on the next page to see how everything is connected together. Notice that as you get closer to one pin than another (including those on devices), a small diamond will show up inside of or around that pin. That is where you want to click to connect a wire. Also, when wiring schematic, leave the wire width at 0, Route method at full, and (usually) Draw Mode as route. This tells that software to auto-route the wires for you. For the first wire, left click on the gate terminal of the pmos4 transistor , and left click again on the gate terminal of the nmos4 transistor. You have just connected the gates. Now, move the mouse until the little square is inside the diamond on the in pin. Left click in the diamond. Move the cursor over to the wire you connected the two gates together with. A diamond will form around the cursor, as long as it's on the wire. Left click. You have just connected the input to the gates of both transistors. Move the cursor up near the vdd pin. Left click inside the pin. Move the cursor to the source (the end with the arrow) of the pmos4 transistor (the end with the arrow). This will add the power line to the circuit. Repeat the last paragraph with the vss pin, and the source of the nmos4 transistor. This gives current a return path to the power supply. The body of the nmos4 and pmos4 transistors are the center pins. On the pmos4 transistor, connect this pin to vdd. On the nmos4 transistor, connect the body to vss. If you put a wire where you don't want it to go, you can delete the wire by left clicking Editing:Edit>Delete and then left click on the object you want to delete (wire, pin, component, etc. ) There should now only be one pin left on each transistor (the sources of both transistors). Connect these two pins together. Finally, connect this last wire to the out pin. A picture of what this should all look like is

shown below.

Once you are done editing, left click the "check mark" icon on the left side of the screen. This will check your work for connection errors and will save your work in the library. You can accomplish the same thing by left clicking Editing:Design -> Check and Save

7. Transient Analysis with manual stimuli input

The Affirma Spectre circuit simulator is a modern circuit simulator that uses direct methods to simulate analog and digital circuit at the differential equation level. The basic capabilities of Spectre circuit simulator are similar in function and application to SPICE, but the Spectre circuit simulator is not descended from SPICE. The Spectre and SPICE simulators use the same basic algorithms, such as implicit integration methods,- but every algorithm is newly implemented. Spectre Algorithms, the best currently available, give you an improved simulator that is faster, more accurate, more reliable, and more flexible than previous SPICE-like simulators. Open the inv_test file from the digital_lib_test library. In the schematic of inverter, left click Editing:Tools -> Analog Environment. The spectre window should appear.

Firstly, change the simulator to spectre by left click Analog Environment:Setup>Simulator/Directory/Host... and choose spectre as the simulator. Always choose spectre for all simulations. Also left click model libraries->/home/your netid/cdscad/techfiles/ami05.scs Secondly, Left click Analog Artist: Setup->Stimuli. The form should appear as follows.

In function choose dc, also press enable button. In DC Voltage field enter 3. After press change, the field in definition box should be ON Vin /gnd! Voltage dc DC voltage=3 ; also set up the Vdd and Vss correspondingly. Also be sure to add the variable of lambda as 3.5e-7. Thirdly, Left Click Analog Artist: Analyses-> Choose. Then the following dialog form appears. Click on the tran button for Analysis. In stop time field enter 10u, which orders spectre simulator to run 10u second transient analysis.

Finally, Left Click Analog Artist: Outputs->To be Plotted->Select on Schematic. Select the input and output of the inverter. Refer to the previous section, DC analysis, for the necessary steps. The analogArtist window should look like the on the next page. Run the simulation by pressing on the green traffic light icon. After few seconds you should be able to see the results of the transient analyses like the ones below.

Run the simulation by pressing on the green traffic light icon and observe the results of the transient analysis. Now you can edit your results and print them out.

8. Printing your Schematic

Now that the schematic is complete, you'll want to print it out. To do this, left click Editing:Design->Plot>Submit... The submit plot window should appear.

Left click Submit Plot: Plot Options. The Plot Options subwindow appears.

Check the "Send Plot Only To FIle" and type in a descriptive name about the plot. Be sure to end the name with the ".ps" extension, as seen above. Also, ensure that the "Header" button is NOT selected in the "Submit Plot" window. The header option will produce an extra page with general information of your plot such as the name of the plot, size and etc. Left click OK in the "Plot Options" window and also in the "Sumit Plot" window. What you are plotting is a postscript file. When the machine is done creating the file, it will send you mail telling you that it completed successfully. To prevent this, you can uncheck "Mail Log To". You can now use the print tool to plot your schematic.

9. Creating Symbols: Inverter Symbol

The symbol editor lets you create a "black box" description of a cell using labels, pins, shapes, notes, and a selection box. Symbols make your design more readable, as you can use them in more complex designs, instead of individual transistors. In the Library Manager click once on the digital_lib library. Then left click Library Manager:File->New Cell. In the Cell Name type inv and in the View Name box type symbol. You can also click on the Tool box and select Composer-Symbol and the View Name box will be automatically filled.

Left click OK The Virtuoso Symbol Editing window should appear. You are ready to draw a symbol for the inverter. First, we will draw a triangle to represent the inverter body. Left click Editing: Add -> Shape -> Polygon

The Add Symbol Shape window appears. Left click Hide for now. To draw a polygon, click at a start point, and then click at the corners of the shape you want to create. To finish the polygon, click again on the start point. Since we are drawing an inverter, we need a sideways triangle, so make one of those. Look at the final picture at the bottom for guidance to draw. The inverter needs a negation circle at the sideways corner of the triangle, so left click Editing:Add>Shape->Circle. Hide the Add Symbol window again. Left click at the point you want to be the center of the circle. Move the mouse until the circle is the size you want, and left click again.

Hint: Rather than invoking the Add Symbol Shape box every time and having to go through the menus, leave the Add Symbol box in the foreground. When you are done drawing a shape, just left click on the appropriate radio button for the new shape you want to draw. When you are done, left click on Cancel to get rid of the box. Now, you want to add pins to the symbol. Left click Editing:Add -> Pin In the Pin Names box type the following pin names: vdd, vss, in and out. Also change the direction of the pins to InputOutput. Change the type to Square from actHi. After these changes the Add Pin window should look like this (except that the Type should be Square):

Click on the Hide button and you will return to the editing window. You are going to start placing the pins in the symbol in the order specified in the Pin Names box, i.e. first you will place the vdd pin, then vss and so on. The pins look a little different than the ones in the schematic, so be careful. You will notice that it is a box with a line attached. The end of the line will have the pin name. The box is the actual pin, so it must point AWAY from the rest of the symbol. Now place all the pins around the symbol. Put the vdd pin on the top of the symbol and the vss pin on the bottom of the symbol. Add the out pin on the right and the in pin on the left of the symbol. The pins in ALL cell views of a single cell must have the same attributes and names. In other words, the input to the inverter in the schematic was called in and was an input/output pin. Therefore, the input pin on the symbol must also be named in and must also be an input/output pin. When you save your symbol, any differences between the pins of the symbol and the pins of the schematic will be reported as warnings. Following these warnings you can figure out where the inconsistency in the design has occurred. Once you place the pins, the pin names may be hard to read for a variety of reasons. You can therefore move the pin name by clicking on the pin text label and then left click on Editing:Edit->Move. Now you can move the label and place where ever you want to. Next we want to add label to the symbol. Left click Editing: Add -> Label...The Add Symbol Label dialog box should appear.

We will add two labels to the symbol. The first one is an instance label. Just left click the Hide button, and place the label somewhere near the symbol of the inverter. Now, we need to add the normal label to the symbol. Left click Editing: Add -> Label... Left click on the Label Type and select normalLabel and now type in the name of the device in the Label field. Hide the Add Label window, and place the label inside of the symbol. The first label was an instance label. Later, when you use symbols to build schematic, the software needs to know which symbol is which. It does this by looking at the symbol label, to see which kind of symbol it is. It them looks at the instance label to see which one of those it is. If you put multiple symbols into a schematic window, they will be labeled U1, U2, etc. The last thing to add is a selection box. This will tell the software how much of the symbol is actually used. Left click Editing: Add -> Selection Box... Left click the Automatic button. The symbol is now finish and you can save it by left clicking Editing:Design->Save. The symbol should look like the one below.

10. Schematic Simulation: Creating a Test File for Simulating an Inverter

Now that we have built an inverter, we need to simulate it to show that our design is valid. Before proceeding with simulating the inverter circuit, we should create a new library for testing our digital circuits. This way we can separate out the primary digital cells from the test schematics. Create a new library called digital_lib_test in your ~/cdscad/ directory. Follow the same steps as describe earlier when creating the digital_lib library. First we need to create a new cell in digital_lib_test library for testing our inverter. It is a good practice to keep separate your cell with your test files. In the Library Manager, highlight the digital_lib_test library and left click on Library Manager:File->New->Cell View. In the Cell Name type inv_test and in the View Name type schematic. Left click on OK.

A new schematic editing tool will appear. You are going to instance the inverter that was previously created and connect its input and vdd pin to voltage sources. The output pin will be connected to a capacitor while the gnd pin will be grounded. Left click Editing:Add->Instance. Click on the Browse button and using the Library Manager select from the digital_lib library, the inv cell, with symbol view. Then close the Library Manager. The Add Component window should look like this:

Place the inverter in the middle of the editing window. Now we want to add voltage DC sources. Left Click Editing: Add->Instance. In the Library Name field type analogLib; in the Cell Name type gnd and then place the symbol bellow the inverter. Left Click Editing:Add->Instance. In the Library Name field type analogLib; in the Cell Name type vdc; in the Cell View type symbol. In the DC Voltage field enter 5V. This window should appear as such:

Place one copy of the voltage source above the inverter and one next to the input of the inverter. The value of the voltage source which will be connected to the input of the inverter is not important because this voltage source will be swept during the DC analysis. We want to add capacitor to the output pin in order to simulate a load (other circuits) that our inverter has to charge or discharge. Left click Editing:Add->Component. From the analogLib library choose a cell named cap and specify its value to be 1f F. Next we will add an output pin in the schematic. Left click Editing:Add->Pin?. Name the pin out and specify it as an input/output pin. Place the pin next to the output of the inverter. Connect all the elements as shown in the figure bellow. To connect different elements use Editing:Add>Wire

Save the schematic and you are ready to simulate the inverter.

11. Spectre simulation: DC Analysis of The Inverter

The Affirma Spectre circuit simulator is a modern circuit simulator that uses direct methods to simulate analog and digital circuit at the differential equation level. The basic capabilities of Spectre circuit simulator are similar in function and application to SPICE, bt the Spectre circuit simulator is not decended from SPICE. The Spectre and SPICE simulators use the same basic algorithms, such as implicit integration methods,- but every algorithm is newly implemented. Spectre Algorithms, the best currently available, give you an improved simulator that is faster, more accurate, more reliable, and more flexible than previous SPICE-like simulators. Open the inv_test file from the digital_lib_test library. In the schematic of inv_test, left click Editing:Tools -> Analog Artist. The spectre window should appear.

First, change the simulator to spectre by left click Analog Artist:Setup->Simulator/Directory/Host... and choose specre as the simulator. Always choose spectre for all simulations. We want to specify the type of analysis we want to perform. We are going to select a DC analysis. Left click Analog Artist:Analyses->Choose Click on the dc button for Analysis. Click Component Parameter button for sweep variable. In the Sweep Range, fill 0 and 5V for the start and stop. Left click on the Select Component. Now go back to the schematic and select the voltage source you want to sweep. Click on the vdc that is connected to the input of the inverter. This will pop-up a small window. Click on dc to sweep the voltage. Go back to your Analysis Choose window, which should look like the one below, and click on OK.

Second, we want to select which output voltages to be plotted. Left click on Analog Artist: Outputs->To be Plotted->Select on Schematic. Click on the wire between your vdc source and the in pin of your inverter. Then click on the wire between the out pin of the inverter and the out pin. Both wires should change color indicating that these voltages will be plotted. Be sure to select appropriate model file before running the simulation. Also set up all the necessary variables. Note: If you want to select a current to be plotted, then click on the square of a symbol where the current is flowing through. There will be a circle around the square node indicating that a current is selected. Your Analog artist window should appear similar to:

You are ready to run the simulation. Left Click Simulation->Run or click on the green traffic light icon in the Analog Artist window. The result window, as the one bellow will appear shortly. Explore the pull down menus in this window in order to customize your results. For instance, left click Axes->Strip in order to separate the different curves.

To plot the results left click Waveform Window: Window->hardcopy. Select the option to Send Plot Only to File and also don't forget to disable the header option in order not to waste paper. You might also disable Mail Log To to prevent it from mailing you about the status of printing. Now exit the Cadence Spice. Left click on Analog artist:Session->Quit. Remember NOT to save the current state. If you choose to save the current state, several hundreds of megabytes will be used in order to save your last simulation.

12. Schematic Simulation: Transient Analysis of The Inverter

Bring up the schematic of inv_test. We need to replace the dc voltage input source with a pulse source. Click on the vdc source that is connected to the input of the inverter. The vdc should have a yellow box around it. Go to Editing:Edit->Delete or press the Del button. Left Click Add->Instance and select Cell Name: vpulse from Library Name: analogLib and View Name:symbol. Fill the rest of the boxes as shown in the figure on the next page. The input pulse that we have specified is bounded between 0 and 5V. It has an initial delay of 1ns, rise and fall time of 1ps and high/low duration of 2ns.

Place this symbol such that the positive end is connected to the input of the inverter. Refer to the next page for the end result.

Save the schematic. Left Click Editing:Design->Check and Save. After we have made these changes we are ready to run a transient analysis on the inverter. Left Click Editting:Tools->Analog Artist. In the Analog artist window go to Analysis->Choose... Set the transient analysis with Stop Time as 8n. We have specified a transient analysis from 0 to 8ns. Left Click Analog Artist: Outputs->To be Plotted->Select on Schematic. Select the input and output of the inverter. Refer to the previous section, DC analysis, for the necessary steps. The analogArtist window should look like the on the next page. Run the simulation by pressing on the green traffic light icon. After few seconds you should be able to see the results of the transient analyses like the ones below.

Run the simulation by pressing on the green traffic light icon and observe the results of the transient analysis. Now you can edit your results and print them out.

14. Layout: Creating Layout for an Inverter

The tool for layout creation is called VIRTUOSO. In the Library Manager highlight the inv cell in the digital_lib library. Left click Library Manager:File->New->Cell View In the cell view of the inv type layout and click OK. NOTE: If the layout-drawing tools are not correctly shown in the LSW window, an error information shows up as follows.

Check your display.drf file, using CIW: Tools display resource manager to merge the display file. For details, s ee APENDIX B Merge LSW Display File Two windows should have appeared. The Virtuoso Layout Editing window, and the LSW window. The LSW window is the one you will use to choose the different layers of the IC design. The LSW window is divided in three main categories which are: color, layer and purpose. Color - Matches the color in the Editing window. Each layer has its own color and pattern. Layer- What is the type of layer (Active, Metal1, Poly, Metal2, etc) Purpose - dg =drawing, pn = pin. Each layer has two colors associated with it; a fill color and an outline color. These colors can be changed to fit your taste by editing the technology file. Now we are going to build the layout of the inverter. An inverter has an NMOS and a PMOS transistor. First we will build an NMOS transistor. Left click Editing: Window -> Zoom Out Left click LSW: Active dg Left click Editing: Create -> Rectangle Left click: Hide Notice that when the mouse is inside of the Editing window that the X and Y coordinate values (found between the title bar and the menu bar) change. These are very handy in making layouts. Also, notice the

dX and dY items. When creating shapes, these show how far in each direction you have moved the cursor (since the last click). From this point on, when I want you to click at a certain point in the Editing window, I will give you the X and Y coordinates in standard Cartesian form: (X,Y). If you make a mistake at any time you can left click on Editing:Edit->Undo. Also you can use move, copy, stretch and delete. Take some time to play with these controls and see how they work. Click at (3,2) to draw the first corner of the rectangle. Click at (19,6) to finish the rectangle. Left click LSW. ActX dg Left click Editing: Create -> Rectangle Handy tip: When drawing many of the same things (rectangles, polygons, etc) you can just right click the mouse to repeat the last operation (draw rectangle, draw polygon, etc.) Click (4,3) to start the rectangle. Click (6,5) to finish it. Now that you know how to draw a rectangle, I will tell you to draw a rectangle from (X1,Y1) to (X2, Y2). Draw a rectangle from (8,3) to (10,5). Draw a rectangle form (16,3) to (18,5). What are these little yellow squares? These are what are known as vias. A via connects the active region to a metal1 layer. A via can not go through more than one layer. There are three different types of vias. ActX connects the active region to metal1, P1Con connects poly to metal1 and ViaX connects metal1 to metal2. Left click LSW. Metal1 dg Draw a rectangle from (3,2) to (11,6). Draw a rectangle from (15,2) to (19,6). What you just created is the metal1 contacts to the NMOS transistor. These are the attachment points to the power and PMOS section of the circuit (in this case). Remember that the body is connected to the lowest available potential. That's why we have metal connecting to both the source and the body. Left click LSW. Pselect dg Draw a rectangle from (1,0) to (7,8). What's Pselect?

Everything (that's visible) inside the Pselect (active) region will be doped as a P-type semiconductor (excess of holes). Since the transistor is of the N-type, it creates a diode junction between the N-doped regions and the P-substrate (The silicon wafer is P-type). This gives a direct connection into the substrate so that we can ensure that the diodes are reverse biased (no current will flow). Left click LSW: Nselect dg Draw a rectangle from (7,0) to (21,8). Left click LSW: Polyl dg Draw a rectangle from (12,0) to (14,8). You have just finished a NMOS transistor. Poly crossing active is a transistor. In this case, the active region is of N type, so it is an NMOS transistor. Where the poly actually crosses is the gate of the transistor. Everything we are doing is called scalable architecture. This means that the units are some unknown lambda. Notice that the gate is 2l wide. If l is 1mm, then the gate is 2mm wide. The smallest possible width of the gate is the technology being used. We have built our first NMOS transistor. Now, it?s time to build a PMOS transistor. Once that's done we'll connect them together to build an inverter. Left Click Editing: Window -> Zoom Out by 2 Left click LSW: Active dg Draw a rectangle from (3,19) to (19,23). Left click LSW: ActX dg Draw a rectangle from (4,20) to (6,22). Draw a rectangle from (8,20) to (10,22). Draw a rectangle from (16,20) to (18,22). Left click LSW: Metal1 dg Draw a rectangle from (3,19) to (11,23). Draw a rectangle from (15,19) to (19,23). Left click LSW: Nselect dg Draw a rectangle from (1,17) to (7,25). Left click LSW: Pselect dg Draw a rectangle from (7,17) to (21,25) What is the difference in Nselect and Pselect?

The two are reversed because this is a PMOS transistor and the other is an NMOS transistor. The Pselect region of the transistor serves the same purpose as the Nselect region of the other. Left click LSW. Nwell dg Draw a rectangle from (0,14) to (24,28). Left click LSW: Polyl dg Draw a rectangle from (12,17) to (14,25). You have just laid out your first PMOS transistor. Now we can connect the two transistors together to make an inverter. Left click LSW: Polyl dg Draw a rectangle from (12,8) to (14,17). You have just connected the gates. The point is that there is no special way to make the connections. All a poly has to do is touch another poly to make a connection. Likewise, with all other layers. This is important to remember when making more complex designs. In your later designs, you will copy instances of your inverter (or other circuits), and you must remember this important fact. Not only that, but you also have to worry about minimum spacing allowed by MOSIS. Left click LSW: Metal1 dg Draw a rectangle from (15,6) to (19,19). You've just connected the drains, and built the inverter. Now it is time to add pins. Left click LSW: Metal1 pn Left click Editing: Create -> Pin... The Create Pin form should appear. Ensure that I/O Type is set to inputOutput. Also make sure that Create label option is checked or otherwise the label names will not appear in the design. Ensure, also, that the Display Pin Name box is checked. Type vdd in the Terminal Names box. Left click Hide. In the Editing window, left click at (3,19). Click again at (7,23). Click one last time at (5,21) to place the label. Left click Editing: Create-> Pin... Make sure all the right buttons are selected, and type vss in the Terminal Names box. In the Editing window, left click at (3,2). Click again at (7,6). Click one last time at (5,4) to place the label. Left click Editing: Create -> Pin... Type out in the Terminal Names box. In the Editing window, left click at (15,13). Click again at (19,9). Click one last time at (17,11) to place the label. Left click LSW: Poly1 pn

Left click Editing: Create -> Pin... Ensure all the switches are properly set and type in in the Terminal Names box. In the Editing window, left click at (12,9). Click again at (14,13). Click one last time at (13,11) to place the label. You have just finished the layout phase of the inverter. Save your design. Be sure to save early and often. It's a guarantee that the first time you forget to save (especially in a big design after a lot of changes), the machine will crash and you will lose all your work. Your layout should look like the one below.

15. Design Rule Check (DRC)

You've created a layout. Now, you need to check that you didn't violate any design rules (Metal1 to close to Metal1, etc.). Left click Editing: Verify -> DRC... The DRC window should open.

Ensure that the window looks exactly like the one above. First specify the whole path in the Rules File which is: ~/cdscad/techfiles/divaDRC.rul . Also disable the box next to Rules Library. Now, you can set the Switch Names box by left clicking the Set Switches button. A menu should appear. Double click (left) on AMI05. The menu should disappear. Left click OK in the DRC window. AMI05 stands for AMI 0.5 which is the 0.5um process. We will do all of out design on the 0.5um scale.

If there are no errors, the CIW window will display "Total errors found: 0" (this may take a few seconds). If any errors are found, they will be displayed in the CIW output window, and will also be highlighted in the Editing window. Read the MOSIS rules (included at the end of this manual or you can download them from www.mosis.com) and correct all mistakes. If you would like to know which rule was violated, left click Editing: Verify -> Markers -> Explain. Then left click on the marker. An explanation window should appear. If you do not want to see these annoying blinking markers, left click Editing: Verify -> Markers -> Delete All... A dialog box will appear. Just left click OK.

16. Layout Extraction

In order to do post-layout simulation and layout versus schematic comparison (LVS), you need to do a layout extraction first as an intermediate step. Left click Editing: Verify -> Extract... The Extractor dialog box should appear. Ensure that you have specified the whole path of the rule file (~/cdscad/techfiles/divaEXT.rul) and the Switch Names is set to AMI05. Left click OK.

If there are no errors, the CIW window will display "Total errors found: 0" (this may take a few seconds). Now you should be able to see another cell view of the inv named extracted in your Library Manager

17. Layout Versus Schematic (LVS)

Layout Versus Schematic comparison compares the layout and schematic cell views. It can also be used to compare one schematic to another (or layout to layout). LVS is used to ensure that your layout is identical to your schematic. LVS works by generating a new net list for each circuit. It then compares the two net lists. If any discrepancies are found, LVS will display them. Before LVS can be run on layouts, the layout must be extracted. In your layout window of the inverter left click Editing: Verify -> LVS...

The LVS form should appear. Type the cell upon which you are working in the Cell Name (i.e. inverter). Set the left column of view to schematic, and the right to extracted. Ensure that Rewiring in LVS Options is NOT selected. Type ~/cdscad/techfiles/divaLVS.rul in the Rules File. Left click LVS: Run A small dialog box may appear, if you have made any recent changes. If so, left click the Save option. LVS usually takes a while, so relax for a bit. When LVS is finally complete, a window will appear telling you that it either succeeded or failed. Left click OK. If it succeeded, it only means that LVS has succeeded. It doesn't mean your schematic and extracted views matched. For this, you got to look at the Output. Left click LVS: Output The result output window should appear. Look through the log file. Check that the net-lists match, and that the comparison program completed successfully. If the net-list don't match, then you need to go back and fix your layout. After fixing the layout, run LVS again. Keep doing this until the net-lists match. When debugging your problem you can use Monitor in your LVS window. You will need to open both the schematic and the layout of the inverter. You can then double click on the error messages and the errors will be highlighted in both schematic and layout. This way you can identify your errors faster.

18. Layout Simulation: Transient Analysis

The actual simulation on the layout will be performed on the Extracted cell view of the inverter. This cell view contains all the information necessary for Spice Simulation. In the Library Manager, double click on the Extracted cell view of the inv. A new editing window with the analog extracted version of your inverter should appear. Left click Editing:Tools->Analog Artist. The analog Artist window will appear. We will perform a transient analysis on the layout of the inverter and the steps are very similar to the ones we described earlier. Then change the simulator to spectre by left click Analog Environment:Setup>Simulator/Directory/Host... and choose spectre as the simulator. Always choose spectre for all simulations. Also left click model libraries->~/cdscad/techfiles/ami05.scs In addition, Left click Analog Artist: Setup->Stimuli. In the prompted window, set: vdd=5V dc, vss=0v dc; vin as pulse, shown as the following chart:

After that, Left Click Analog Artist: Analyses-> Choose. Then the following dialog form appears. Click on the tran button for Analysis. In stop time field enter 10n, which orders spectre simulator to run 10n second transient analysis.

Finally, Left Click Analog Artist: Outputs->To be Plotted->Select on Schematic. Select the input and output of the inverter. Run the simulation by pressing on the green traffic light icon. After few seconds you should be able to see the results of the transient analyses like the ones below.

APENDIX A

CADENCE SETUP CONFIGURATION

Before we discuss how to build a custom library, you should make a directory in you account. To do this, do the following steps: 1. copy the c shell script to your local directory. cp /usr/local/cad/cfg/cadence_newuser/cshrc.cfg.fzm ~/.cshrc

2. copy the cadence configuration package to your home directory.

cp /usr/local/cad/cfg/cadence_newuser/cad_cfg.tar ~/

3. then tar xvf cad_cfg.tar , this will unzip config.tar into your home directory (this creates a
directory by the name of ~/cdscad/). This way you can have your library in a separate directory.

4.

Use ls liah ~/cdscad to see all the config files under that directory. It should be drwxr-xr-x 5 zf5 drwx------ 54 zf5 -rw-rw-r--rw-rw-r--rw-rw-r--rw-rw-r-1 zf5 1 zf5 1 zf5 1 zf5 zf5 zf5 zf5 zf5 zf5 zf5 zf5 zf5 zf5 4096 Aug 20 17:58 . 4096 Aug 20 18:03 .. 0 Aug 20 17:58 ams.env 8258 Aug 20 17:58 .cdsenv 2894 Aug 20 17:58 .cdsinit 1480 Aug 20 17:58 cds.lib 4096 Aug 13 15:50 libraries 4096 May 17 14:16 scripts 4096 May 19 17:36 techfiles

drwxr-xr-x 3 zf5 drwxr-xr-x 2 zf5 drwxr-xr-x 2 zf5 z z

The techfiles sub-directory keeps all the technical files for CMOS. The libraries subdirectory will keeps your future designs. Now the environmental variables are readily configured for ~/cdscad/ directory.

APENDIX B LSW Display File Merge If the layout-drawing tools are not correctly shown in the LSW window, an error information shows up as follows.

Check your display.drf file, using display resource manager to merge the display file.

In above figure,the LSW does not include any layout definition What you need to do is merging the display.drf. Go to CIW, choose Tools Display Resouces Managers. The display Resources Toolbox shows up as follows.

Select Merge . Button. The Instructions pop up.

In the following dialog box, enter ~/cdscad/techfiles/display.drf in From File. Then press Add button.

In Destination DRF enter display2.drf. ( you can not use the same name with display.drf because it is being used now)

Press OK. When you create a new Virtuoso cellview, you should be able to see all the LSW layers such as follows.

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