SIMULATION PROJECTS(ECE) DIGITAL SIGNAL PROCESSING (ADSP & TEXAS) IMAGE PROCESSING

SBIMP04 SBIMP07 SBIMP10 SBIMP18 SCIMP03 SCIMP05 SCIMP07 SCIMP08 SCIMP12 SCIMP14 SCIMP17 SCIMP20 SCIMP21 SCIMP22 SCIMP25 SCIMP27 SCIMP28 SCIMP29 SCIMP30 SDIMP09 SDIMP11 Phase adaptive super resolution of mamographic images using complex wavelets Image quality assessment based on multi scale geometric analysis Image segmentation via spline regression Morphological Background detection High Resolution Cerebral Blood Flow Imaging by Registered Laser Speckle Contrast Analysis Scanned Compound Document Encoding Using Multiscale Recurrent Patterns Tracking and Activity Recognition Through Consensus in Distributed Camera Networks TurboPixel Segmentation Using Eigen-Image Image Segmentation by MAP-ML Estimations Fast Query for Exemplar-Based Image Completion Phase Adaptive Super Resolution Of Mammography Images Using Complex Wavelets A Fast Multilevel Algorithm For Wavelet-Regularized Image Restoration Morphological Background Detection And Enhancement Of Images With Poor Lighting High-Fidelity Data Embedding For Image Annotation Upper surface of the diaphragm estimate using 3D CT Images Automatic Exudates Detection from the eyes of Diabetic Patients Image retrieval using Color, Texture and Shape Face Detection Using Adaboost algorithm Color Image Segmentation Boundary Detection in Medical Images Using Edge Following Algorithm Based on Intensity Gradient and Texture Gradient Features Multichannel Image Registration by Feature-Based Information Fusion

DIGITAL SIGNAL PROCESSING SCDSP01 SCDSP02 SDDSP01 Energy Efficient Multi-Object Tracking in Sensor Networks Cooperative Diversity of Spectrum Sensing for Cognitive Radio Systems QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers

COMMUNICATION
SBCM01 SCCM13 SCCM14 SDCM03 SDCM04 SDCM06 Communication coverage for wireless passive networks Channel coding for high-speed links: a systematic Look at code performance and system simulation Training design for repetitive-slot-based CFO estimation in OFDM Symbol-Level Synchronization and LDPC Code Design for Insertion/Deletion Channels Optimized Differential GFSK Demodulator Coded Free-Space Optical Links over Strong Turbulence and Misalignment Fading Channels

VLSI
CORE VLSI
SBVL01 SBVL04 SCVL01 SCVL03 SCVL08 SCVL11 SCVL17 SDVL01 SDVL11 SDVL13 SCVL06 A Fast Hardware Approach for Approximate,Efficient Logarithm and Antilogarithm Computations A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System field programmable gate array prototyping of end around carry parallel prefix tree architectures Accumulator Based 3-Weight Pattern Generation(Testing) Fixed-State Tests for Delay Faults in Scan Designs Mapping Multi-Domain Applications onto Coarse-Grained Reconfigurable Architectures. Fault Secure Encoder and Decoder for Nano Memory Applications

SBVL09 SBVL13 SCVL24

Spread Spectrum Image Watermarking with Digital Designe A Compact AES Encryption Core on Xilinx FPGA An improved RC6 algorithm with the same structure of encryption and decryption

SBVL17 SBVL20 SCVL26 SCVL28 SDVL20

A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter Fault Secure Encoder and Decoder for Nano Memory Applications New Architectural Design of CA-Based Codec Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications