Carrier based Single-state PWM Technique Of Minimised Vector Error In Multilevel Inverter

ABSTRACT In the paper, a novel analysis of carrier based PWM methods for multilevel inverters is presented. The space vector PWM and carrier based PWM correlations in multilevel inverters are investigated in a nominal two-level switching diagram. The obtained results may be applied to design various carrier PWM techniques. In this paper, a carrier based single-state PWM technique, which reduces number of switchings and optimizes active voltage errors will be presented. This PWM technique can be advantageous if there is a large number of levels. The proposed method is mathematically formulated and demonstrated by simulation and experimental results..

Figure 1: 3 phase 5-level NPC inverter

Keywords: Single-switching state, PWM technique, minimised voltage error, multilevel inverter

1. Introduction
Nowadays, for increasing use in practice and fast developing of high power devices and related control techniques, multilevel inverters have become more attractive to researchers and industrial companies. Two common inverter topologies are NPC and cascaded multilevel inverters (Fig.1 and 2) [1-5]. In recent days, for reducing hardware construction cost, it has been shown a try to develop prospective hybrid multilevel inverters. There are basically three PWM schemes for controlling multilevel inverters as: Carrier based PWM, space vector PWM and selective harmonics elimination PWM methods. [6],[7]. Compared to the space vector PWM methods, the carrier based PWM methods [3] can be advantageously utilised in: 1) controlling common mode voltage, 2) controlling of complicated inverter topologies as 4-leg, 5-leg-,... multilevel inverters, 3) compensation of unbalanced dc sources.

Figure 2: 3-phase Cascaded multilevel inverter

The comprehensive correlation between carrier based PWM and SVPWM have been derived in the recent work It will be shown that the carrier PWM technique can become a possible solution for some approximate PWM methods, which use one or two switching states in a switching state sequence and produce reference voltages with certain voltage error. The drawbacks as

nonlinear control characteristics and existence of low-order harmonics of output voltages will be compensated by reduced number of switchings in each sampling time period. A common characteristic of carrier based approximate PWM methods is that the offset function can be properly designed to control the PWM performance. Single state space vector PWM method has been described in some recent paper [2], one of its drawback is the limitation of output voltage range. The methods of selecting the voltage vector in Direct torque control and hysteresis current loop control for AC motor drive systems are some typical and well-known applications of single state PWM technique. In the paper, the carrier based single state PWM will be proposed for minimum voltage error. The only controllable parameter of this method is the offset voltage, which does not influence on the active voltage but able to set approximately common mode voltage and balance switching losses. In the paper, it will be shown that any PWM scheme of multilevel inverter can be centered in a nominal two-level switching state diagram. This makes the PWM study to become more advantageous and comfortable. The proposed method is explained for NPC inverters, its proper modifying can be also applied to cascade topologies.

Where v ref = v aref , vbref , v cref unit vector, and

, I = [1,1,1] is

r v12 = [v a12 , vb12 , vc12 ]T .

(2)

Active voltages, which exist at the three phase load voltages can be determined from the amplitude and phase angle of voltage vector as follows:

v a12 = v ref cos vb12 = v ref cos( 2 3) ; vc12 = v ref cos( 4 3)

Define Max and Min as maximum and minimum values from three phase active voltages as: (3)

Max = Max(v a12 , vb12 , vc12 )

(4)

Min = Min(v a12 , vb12 , vc12 )

Reference common mode voltage can be proposed as a value, varying within the limits of v 0 Max and v 0 Min :

2. Terminology and Nominal switching diagram in Multilevel inverter for balance Dc voltage sources
Assumption: each dc voltage cell is constant and equal to a unit (Vdc=1). Define reference leg voltages between output (A,B,C) and dc-neutral point 0 (Fig.1), consisting of active voltages v x12 , x = a, b, c and

v0 Max = (n 1) Max v0 Min = Min

(5)

Active Low/or High level: each reference leg voltage

v xref is produced by subsequent alternating between the

two lower and higher active levels as

L( x ) and

reference common mode

v0 ref [8] as:

(1a)

H ( x ) (Fig.3a), for which the following conditions will be

satisfied as:

v xref = v x12 + v0 ref

Or in the vector form as:

r r v ref = v12 + v0 ref I

if n( x ) L( x ) = n( x ) 1 if H ( x ) = L( x ) + 1

0 v xref < (n 1) v xref = (n 1) . (6)

(1b)

where n( x ) = Int (v xref ); x = a, b, c . Components of

(7) vector

r L = [ La , Lb , Lc ]T correspond to lower levels of phase

leg voltages in switching state sequence. Nominal switching time diagram: To investigate commutation process in a triangle period, a vertical move of reference three-phase modulating signals by the

The components of vectors s 2 ; s3 can be derived as follows:

r r

x Max 1 if s2 x = 0 else x Mid 1 if s3 x = 0 else

(11) Switching state sequence in multicarrier multilevel

vector L = [ La , Lb , Lc ] is realized and these signals compare with an active carrier as shown in Fig.3b. In the diagram Fig.3b, the commutation instants occur by comparing active carrier wave with nominal modulating signals

, x = a, b, c defined as:

r r

r r

x = v xref L( x ) ; 0 x 1 ;
Or

(8).

inverter S1 , S 2 , S 3 , S 4 :

can

be

easily

r deduced from active low voltage level L and nominal

switching states as

= vref L
Nominal switching states sequence: The nominal two-level switching diagram in Fig.3b shown that character of switching time digram in multilevel inverters is similar to that of two-level inverter. Therefore, in nominal switching diagram, lets define nominal switching states as :

r r r Sj = L + sj

(12)

Switching time duties: Reference voltage vector can be described as:

r r r r r v ref = K1 S1 + K 2 S 2 + K 3 S 3 + K 4 S 4

(13)

r s1 = [0,0,0]T r s 2 = [ s 2 a , s 2b , s 2c ]T . r s3 = [ s3a , s3b , s3c ]T r s 4 = [1,1,1]T

r r

The switching time duties as K1 , K 2 , K 3 , K 4 can be determined easily from nominal switching diagram as: (9)

K1 = 1 Max ; K 2 = Max Mid K 4 = Min K14 = 1 Max + Min K1 + K 2 + K 3 + K 4 = 1

(14) ;

K3 = Mid Min

The first and last states as s1 ; s 4 remind two active zero redundant states in switching

r r two-level inverter. For the remaining two states as s 2 ; s3 ,

the vector components can be determined from relative positions of nominal modulating signals

state sequence of

x .

Define maximum, medium and minimum values of the three phase nominal modulating signals as:

Max = Max( a , b , c ) Mid = Mid ( a , b , c ) Min = Min( a , b , c )

Conventional PWM techniques attain zero active voltage error. For improving output quality, the offset can be regulated within the range of (v0Min,v0MAX). Locally an extra adjustment of the offset within the range defined in (15) can perform different modified PWM methods.

(10)

K 4 v0 add = e0 = 0 add K1

(15)

3. Proposed Single state PWM method

In single-state PWM technique, commutation in a sampling period. there is no The reference

for selecting the vector v ref . For example, the vector

r'

r S1 is selected if r r r r Offset ( S1 v ref ) < Offset ( S 4 v ref ) . (18)

Or by derivation, the condition is:

vector v ref is modified and set equal to some from 4 relevant vectors (Fig.4b):

r r r r S1 , S 2 , S 3 and S 4 , defined as

r r' v ref = S j ; j { 1,2,3,4}

(16)

K 2 + 2K 3 + 3K 4 ( K + 2K 3 + 3K 4 ) (19) <1 2 3 3

Figure 3: a) Switching time diagram deduced in a) new defined coordinates and b) Nominal switching time diagram.

Define function

K Max as the largest from three

Figure 4: a) Reference vector in single-state switching and function Kmax in a triangle, and b) Principle of single-state PWM method.

time duties of K 14 , K 2 and K 3 :

K Max = Max( K14 , K 2 , K 3 )

(17) The value of

Algorithm for Single-state minimum voltage error

PWM

with

K Max depending on vector location in

a triangle area is described in Fig.4a. In sub-area j,

j { 14,2,3} , where the

reference vector Vref

is

From previously described procedure, for given reference vector, and corresponding deduced switching time duties, it is needed to determine area of located vector using (6)-(8),(10),(14) and condition described in Table 1. Related selected vector will then be proposed by (9),(11) and (12). If reference vector is located at the center of the triangle, i.e. K 14 = K 2 = K 3= 1 / 3 , active error can achieve a maximum value of

located, the condition K j = K Max will be valid and the active error

r r' v ref = S j is implemented (Fig.4b). Obviously, if r r K Max = K14 , both vectors S1 and S 4 have the r same active error e12 . To select one of them, criterium
as minimizing the offset error e0 can be considered

will be

minimized if

the vector

e12 Max = 2 (3 3 ) .

(20)

Table 1: Algorithm for single-state PWM method

Conditions

Selected

vectors

AND

Active volta ge error e12

K14 > K2 ; K14 > K3

r r' v ref = S1
2 2 e12 = K2 + K 32 + K 2 K 3 3

K2 +2K3 +3K4 <1.5

v x12,m = (1 )v x12, A + v x12, B

Where

(21) (22)

= (m m A ) /( m B m A ) .

K 2 > K 3 ; K 2 > K14

r r' v ref = S2
e12 =

K3 > K2 ; K3 > K14

r r' = S3 v ref
e12 = 2 2 2 K14 + K2 + K14K2 3

2 3

2 K 14 + K 32 + K 14 K 3

K14 > K2 ; K14 > K3

r r' v ref = S4
e12 = 2 2 K2 + K 32 + K 2 K 3 3

K 2 + 2K 3 + 3K 4 >

Overmodulation in method

single-state

PWM

Compared to limit deduced in [2], the carrier based single-state PWM approach can help to get a maximum modulation index up to that of six-step method. Three limit active modulating signals corresponding to modulation indexes of 1,1.055 and 1.1 correspond to two-mode overmodulation. Control characteristics: The diagrams of nonlinear control characteristics of seven-level inverters are calculated and drawn in Fig.5. Obviously, a better linearity characteristic is obviously obtained for higher level inverters. The single-state PWM demonstrates its benefit for reducing switching losses for higher number of levels and for higher modulation indices. The existing error for non-linearity of control characteristics in open-loop control can be reduced with large number of levels or compensated in close-loop control system.

Because of producing output voltage with nonzero error, the single-state PWM method has a non-linear control characteristic and generates low-order harmonic voltages for the whole modulation range. Compared to conventional PWM methods, overmodulation in single-state PWM method losses its original meaning. However, overmodulation can be supposed to be an approach to extend the reference fundamental voltage

IV. Simulation and experimental results

To validate the theoretical analysis, simulation and experiment were implemented for a system of hybrid and cascaded seven-level inverter, each phase consists of two-H bridge inverters in series. The first H-bridge is supplied by a dc source of 40Vdc and the second supplied by higher voltage of 80Vdc. Three-phase RL load is set as R=10 , L=180mH. Simulation was implemented using PSIM 6.0. Diagrams of the phase leg voltage , phase load voltage, line-line voltages and load current for several modulation indexes as 0.4, 0.85, 1 in undermodulation and 1.04 in over-modulation were calculated and drawn in Fig.6,8 and 10 and 12. The single-state PWM method can be advantageously operated at medium and high modulation index, where harmonic amplitude distortion in normally small and better control characteristics can be obtained. The hardware parameters are as following: IGBT FG60N100BNTD H20, driver with photo-couple PC123, dead-time set by hardware as 3 S. The measuring oscilloscope TDS2014b and Control kit eZdsp TMS320F2812, software CCStudio v3.1. Switching

V(1) mref to a maximum value in six-step mode, i.e.,

attaining a value of 2

VS

, Vs is total voltage on dc

side.That is, the overmodulation happens if the reference fundamental voltage V(1) mref exceeds the value of

Vs / 3 .
The active voltages in single-state carrier overmodulation can be deduced from the principle control between two-limit trajectories [6], for which the active modulating signals

v x12,m corresponding

modulating index of m, m A m m B can be deduced from the active signals of the corresponding limit modulation indexes of m A , m B as:

frequency was selected as 1050Hz. The diagrams of leg voltage, phase-load voltage, line-line voltage and phase current for modulation indexes of 0.4, 0.85, 1 and 1.04 were measured and shown in Fig.7,9,11 and 13. The voltage/current quality can be evaluated through the FFT analysis as shown in Fig.14 and Fig.15. The obtained experimental results, which are similar to simulation results, have proved the proposed PWM algorithm. It is obviously seen that the output voltage/current are less quality for low modulation index, and harmonics distortion can be improved for higher voltage range. In overmodulation range, as known the harmonic situation is still good for lower range (near m=1). In around six-step mode, harmonics content is abruptly increased, similarly as in conventional PWM overmodulation.

levels or compensated in close-loop control system.

References
[1] J.Rodriguez, J. S. Lai and F. Z. Peng, Multilevel inverters: a survey of topologies, controls and applications, IEEE Trans. Industrial Electronics, vol. 49, no. 4, pp.724-738, August 2002 Jose Rodrguez, Luis Morn, Pablo Correa and Cesar Silva,A Vector Control Technique for Medium-Voltage Multilevel Inverters, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002 G. Carrara, S.Gardella,M. Marchesoni,R. Salutari, and G.Sciutto, A new multilevel PWM method- A theoretical analysis, IEEE Trans. Power Electronics, vol.7, pp.497-505 1992 S. Wei, B.Wu, F. L. and C. Liu, A general space vector PWM control algorithm for multilevel inverters pp.562-568, IEEE conf. APEC 2003 B. P. McGrath, D.G.Holmes, Multi-carrier PWM strategies for multilevel inverters, IEEE Trans. Industrial Electronics, vol. 49, pp.858-867, August 2002 N.V.Nho, M.J.Youn, Comprehensive study on Space vector PWM and carrier based PWM correlation in multilevel invertors, IEE Proceedings Electric Power Applications, Vol.153, No.1, pp.149-158, Jan. 2006 N.V.Nho,H.H.Lee, Optimised Discontinuous PWM for multilevel inverter with variable load power factor, IEEE PESC 2006 N.V. Nho and H.H. Lee, Carrier PWM Algorithm For Multi-leg Multilevel Inverters, EPE 2007

[2]

[3]

[4]

[5]

[6]

[7]

[8]

Figure 5: Control characteristics of 7-level inverter

V.CONCLUSION
In the paper, a new single-state PWM with minimum voltage error for multilevel inverter has been proposed. Using a proper voltage model of inverter circuit, it can transform switching state diagram of multi-carrier modulation into that of conventional two-level inverter. The parameters from deduced nominal switching diagram can be used to proposed single-state PWM with minimum voltage error. The proposed method has been verified by simulation and experimental results. The benefit of the method can be more effective if large number of levels is considered. The non-linear control characteristics of method is able to compensate by increasing the number of

Figure 6: Simulation results for m=0.4. Diagrams of a)inverter voltage,b) load voltage, c)line-line voltage and d) load currents..

Figure 8: Simulation result for m=0.85. Diagrams of a)inverter voltage,b) load voltage, c)line-line voltage and d) load currents.

Figure 7: Experimental result for m=0.4. Diagrams of a)inverter voltage,b) load voltage, c)line-line voltage and d) load currents.

Figure 9: Experimental result for m=0.85. Diagrams of a)inverter voltage,b) load voltage, c)line-line voltage and d) load currents.

Figure 10: Simulation for m=1. Diagrams of a) inverter voltage,b) load voltage, c) line-line voltage and d) load currents.

Figure 12: Simulation results for m=1.04. Diagrams of a) inverter voltage,b) load voltage, c)line-line voltage and d) load currents.

Figure 11: Experimental result for m=1. Diagrams of a) inverter voltage,b) load voltage, c) line-line voltage and d) load currents.

Figure 13: Experimental result for m=1.04. Diagrams of a) inverter voltage,b) load voltage, c)line-line voltage and d) load currents.

Figure 14: Experimental results. Diagrams of FFT analysis of load current and voltage for m=0.4 (a,c) and m=0.85 (b,d).

Figure 15: Experimental results. Diagrams of FFT analysis of load current and voltage for m=1 (a,c) and m=1.04 (b,d).