2007 IEEE Nuclear Science Symposium Conference Record

N15-37

A VME module for a fast readout of the monolithics analog front-end chips
Boiano C. , Guglielmetti A., Romoli M..
Abstract A single-slot VME card has been developed to digitalize the multiplexed analogue signals coming out from the analog front-end chips (VA32HDR14.2) used in the EXOTIC experiment. The module has 8 differential channels each one sample by 50 MHz 12-bit ADCs. Other features of the ADC card are the use of a sliding-scale technique to improve the differential linearity, the pedestal individually subtracted for each chip channel, a zero suppression with individual threshold, a multi event storage capability ( up to 256) , a programmable number of chips connected in chain, 8 trigger levels to manage different operations and a Test-Mode functionality to manage and control the VA32HDR14.2 chip. INTRODUCTION

RECENTLY a new line of production for radioactive nuclear beams was developed at INFN Legnaro National Laboratory. Beams of 17F and 8B of up to 106 p/s were produced and used for elastic scattering and break-up studies [1]. For these measurements very efficient, compact and segmented detector apparatus are needed. In this context the Expades system [2], formed by 16 silicon detectors with 32 double sided strips (Fig.1), was developed. The total 1024 strips are readout by means of monolithic analog signal processor VA32_HDR14 (Fig.2) from IDEAS [3]. This chip has 32 electronic chains composed of charge sensitive preamplifier, shaper and hold circuit. A multiplexer controlled by shift register allows to serialize the 32 analogue outputs. For a fast acquisition of this multiplexed signal and also to bring out the logic signal used to control all the chip functionality, we have developed the dedicated VME board EXOTIC-ADC.

Fig. 2 VA32_HDR14 Basic Building block I. FUNCTIONAL DESCRIPTION With an external trigger, the control logic starts the conversion sequence. After a programmed delay time, the hold signals are sent to the chips in order to capture the maximum of a Gaussian peak. Then the module can generate the logic signal to bring out in sequence the 32 amplitudes captured by the hold circuits and acquire it by means of an ADC with sampling rate of 50Mhz (Fig.3). The Clock signal generated from the module controls the multiplexer shift and can reach the maximum frequency of 5 MHz so that the analogue output is sampled by ADC with a frequency 10 time higher. In this way the ADC data can be easily processed to reduce noise means of a FIR filter. At the decimated output of this filter is then subtracted the correspondent pedestal value and the sliding scale value added to the analogue input. The data of all channels are then stored into the Event Buffer Memory if they exceed the respective threshold value. Through the VME bus the data can be read in block transfer mode and at end of Data Event the VME BERR signal is asserted. The board can also handle the test mode functionality of the chip. In this modality an analogue pulse with settable amplitude can be addressed to one of the 32 channels of the chip. Moreover,

FIG. 1 EXOTIC DETECTORS

Boiano C. , are with INFN sez. Milano via G. Celoria, 16 Milano 20133 ITALY (telephone: +39-02-50317282, e-mail: Ciro.Boiano@mi.infn.it). Guglielmetti A. are with Milano University and INFN sez. Milano via G. Celoria, 16 Milano 20133 ITALY Romoli M., are with INFN sez. Napoli via Cintia, I-80126, Napoli, Italy

1-4244-0923-3/07/$25.00 2007 IEEE.

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a monitoring analogue output on the front pannel allows an inspection of one of the 8 analogue input.
CH. . 1 ADC CH. 2 ADC FIR . Mem CH. 8 ADC FIR . Mem FIR . Mem FPGA CONTR. VME INT.

V M E B

settable by means of 4 hexadecimal rotary switch. The board is see from VME in a 16 address bit space. In the first half of space address are located the control registers, and the threshold memory, the second half of the space memory is read only and is reserved to the Data Memory. This is readable in single access or block transfer mode. In this modality the board can be settable to response with a BERR at the end of complete data event read out.

DAC
CHIP CONTR. OUT CHIP CONTR. IN VA DRIVER

TRG. IN CONTR. BUS TRG DRIVER

FIG. 3 BLOCK DIAGRAM OF EXOTIC-ADC

II. MAIN FUNCTIONALITY The module has build in a 1 unit VME Board, and has 8 independent differential analog input channels with a +/- 2V max input voltage. A programmable input offset voltage in a range of +/- 2V , common for all channels allow to mach the full ADC dynamic range to the voltage swing of the chip output. The board also provide all the logic signal necessary to the chip for a complete event processing and acquisition. All of this logic signal are jumper selectable in LVDS or LVTTL standard. Moreover this control signal can be settable as input, in this way the board work as SLAVE and the conversion sequence is external controlled. The zero suppression allow to write in to the FIFO memory only the channels with amplitude over the respective threshold. This threshold value are individually settable. The data valid are organized in a Data Event structure composed by a sequence of Header Word, Data Words, and End Word. In the Header Word is written the board identification number, the count of the valid data word and the number of the chips connected in chain. The Data Word have the data value, the channel of the module, and the chip channel. The End Word have the event counter, and a parity bit. These words are distinguished by means of three identification bit. A trigger Bus on the front of the board allow to connect more ADC and working them synchronized with a single event trigger. Eight trigger level can be accepted to which one can associate different actions, for example one of this is the test mode. In this modality an calibration signal supplied by the board can be sent to a single input channel and his output can be sampled and stored in to the FIFO memory. Moreover an analog monitor output is made with a DAC witch reconvert in analog one of the eight ADC data, allowing to monitor one of input channels . III. VME INTERFACE The Module can be addressed by VME Bus in A24 and A32 mode and D32 data width. The module base address is
[3]

Fig. 4 The EXOTIC-ADC VME Board

IV. PERFORMANCE The main performance of EXOTIC ADC are: 1. ADC Noise < 0.5 LSB RMS 2. INTEGRAL NON LINEARITY < +/- 0,025% 3. DIFFERENTIAL NON LINEARITY < +/- 2%
3300,00 3100,00 2900,00 2700,00 2500,00 2300,00 2100,00 1900,00 0 100 200 300 400 500 600

Fig. 5 The multiplexed output sampled by ADC were the X axis is the sampling number, and the Y axis is ADC Value

REFERENCES
[1] D. Pierroutsakou et al., 17F + 208Pb exclusive break up at Elab = 86 MeV with the EXOTIC beamline facility, LNL-INFN Annual Report 2006 M. Romoli et al., EXPADES: a new detection system for charged particles in experiments with exotic beams, LNL-INFN Annual Report 2006 VA_32HDR14 Data Sheet 16 july 2003 Ideas ASA, Veritasveien 9, Box 315, N-1323 Hvik, Norway

[2]

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