COUNTERS

Counting is frequently required in digital computers and other digital systems to record the number of events occurring in a specified interval of time. Normally an electronic counter is used for counting the number of pulses coming at the input line in a specified time period. The counter must possess memory since it has to remember its past states. As with other sequential logic circuits counters can be synchronous or asynchronous. As the name suggests, it is a circuit which counts. The main purpose of the counter is to record the number of occurrence of some input. There are many types of counter both binary and decimal. Commonly used counters are 1. ! ". #. %. &. (. ing Counter BC$ Counter $ecade counter 'p down Counter )requency Counter Binary ipple Counter

Binary Ripple Counter

A binary ripple counter is generally using bistable multivibrator circuits so that cache input applied to the counter causes the count to advance or decrease. A basic counter circuit is shown in )igure 1 using two triggered *T+type, flip flopstages. -ach cloc. pulse applied to the T+input causes the stage to toggle. The / and output terminals are always logically opposite. 0f the / output is logical 1 *1-T,, the output is then logical 2. 0f the / output is logical 2 * -1T,, then the output is logical 1. The cloc. input causes the flip flop to toggle or change stage once cloc. pulse )igure " *a, shows the cloc. input signal and / output signal. Notice that the circuit used in this case toggles on the trailing edge of the cloc. signal *when logic signal goes from 1 to 2,. eferring bac. to )igure 1 the / output of the first stage *called the "o stage or units position stage, is used here as the toggle input to the second stage *called the "1 or two3s position stage,. The / output from the two successive stage are mar.ed A and B, respectively, to differentiate them. Notice that the output of each stage is mar.ed with a negative bar over the letter designation, so that whatever logical stage A is at, is the opposite logical state. 1ince the / output *A signal, from the first stage triggers the second stage, the second stage changes state only when the / output of first stage goes from logical 1 to logical 2 as shown in )igure "*b,.

Table 1

COUNT FOR 2-STAGE BINARY COUNTER Input Pulses 0 1 2 3 4 or 0 2n Output n 2 Output (A) (B) 0 0 1 1 0 0 1 0 1 0

An arrow is included on the waveform of stage A as a reminder that it triggers stage B only on a trailing edge *1 or 2 logical change,. Notice that the output waveform of succeeding stage operates half as fast as its input. To see that this circuit operates as a binary counter a table can be prepared

to show the / output states after each cloc. pulse is applied. Table 1 shows this operation for the circuit of )igure 1. To see how a counter is made using more stage considers the % stage counter of )igure #. The counter is simply made with the / output of each state connected as the toggle input to the succeeding state. 4ith four stages the counter cycle will repeat every si5teen cloc. pulses. 0n general there are "n counts with an n+stage counter. )or the four stages used here the count goes "% or 1( steps as a rule, for a binary counter. Number of counts 6 N 6 "n 4here, n 6 number of counter stage. A si5 stage counter n 6 ( would be provide a count that repeats every N 6 "( 6 (% counts. A ten+stage counter *n 6 12, would recycle every N 6 "12 6 12"% counts. eturning to the % stage counter )igure #. Arrows are included in the table to act as reminder that a change from 1 to 2 results in a succeeding stage being toggled. Notice in Table " that the " stage toggles on every four cloc. pulses. The "1 stage toggles every two cloc. pulses, the ""stage toggles every cloc. pulses. This implies that we can associate a weighting value to the stage output. The "# stage output can be considered of value eight, the "" output equal four, "1output equals two and " equals one. 4e can see then that the binary state of the counter can be read as a number equals to the pulses input count. After the counter reaches the count 111, which is the largest count obtained using four stages, the ne5t input pulse causes the counter to go to 222 and new count cycle repeats.

Table 2

COUNT UP OPERATION (FOUR STAGES) Input Pulses 0 1 2 3 4 23Output (D) 0 0 0 0 0 22 Output (C) 0 0 0 0 1 21 Output (B) 0 0 1 1 0 2 Output (A) 0 1 0 1 0

5 6 7 8 9 10 11 12 13 14 15 16 or 0

0 0 0 1 1 1 1 1 1 1 1 0

1 1 1 0 0 0 0 1 1 1 1 0

0 1 1 0 0 1 1 0 0 1 1 0

1 0 1 0 1 0 1 0 1 0 1 0

0t should be obvious that the count sequence is an increasing binary count for each input cloc. pulse. Then the counter is also referred to as a count up binary counter the resulting output waveform for each stage is shown in )igure %. The count is called a ripple counter because of the rippling change of state from lower order to higher order stages when the count changes i.e. the " stage toggles the "1 stage, which may toggle the "" stage etc.

Count-Down Counter
A simple four stage count down counter is shown is )igure &. The /+output of each stage is now used as trigger input to the following stage. 0t still use the /+output as indication the state of each stage as shown in the count table *table #,. 1tarting with the counter -1-T /+output of each stage is logical+2, the first input pulse causes stage A to toggle form 2 to 1. The trigger pulse to stage B being ta.en from the /+output of stage A goes from 1 to 2 at this time so that stage B is also toggled. The /+output of stage B going from 1 to 2 causes stage C to be toggled, which then causes stage $ to toggle.

Figure 5: Four Stage Count- own Binary Counter

Ta le !" C#unt-$#%n C#unte& #' F()u&e ! Input Pulse 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 C 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 B 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 De*(+al Output C#unt 0 (or 16) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (or 16) 15

Table & shows, then that the count goes to 1111. The ne5t input puse toggles A. 1ince the signal A *used to toggle stage B, now goes input 2 to 1. 1tage B and C and $ remain the same, the count now being 1112. Thus, the count has deceased as a result of the input trigger pulse. 0n fact the count will countinue to decrease by one binary count for each input trigger pulse applied. Table & shows that the count will decrease to 2222 after which it will go to 1111 to repeat another count circle. 'sing four stage the count down counter provides a full cut off N 6 "n 6 "% 6 1( count but in decreasing count mode of operation.

De!a e Counter

A decade counter is the one which goes through 12 unique combinations of outputs and then resets as the cloc. proceeds. 4e may use some sort of a feedbac. in a %+bit binary counter to s.ip any si5 of the si5teen possible output states from 2222 to 1111 to get to a decade counter. A decade counter does not necessarily count from 2222 to 1221 it could count as 2222,2221, 2212, 1222, 1221, 1212, 1211, 1112, 1111, 2222, 2221 and so on. )igure ( shows a decade counter having a binary count that is always equivalent to the input pulse count. The circuit is essentially, a ripple counter which count up to 1(. 4e desire however, a circuit operation in which the count advance from 2 to 7 and then reset to 2 for a new cycle. This reset is a accomplished at the desired count as follows. 1. 4ith counter -1T count 6 2222 the counter is ready to stage counter cycle. ". 0nput pulses advance counter in binary sequence up to count of a *count 6 1221, #. The ne5t count pulse advance the count to 12 count 6 1212. A logic NAN$ gate decodes the count of 12 providing a level change at that time to trigger the one shot unit which then resets all counter stages. Thus, the pulse after the counter is at count 6 7, effectively results in the counter going to count 6 2.

Figure ": De!a e Counter

Ta le ," De*a$e C#unte& T&ut- Ta le Input Pulses 0 1 2 3 4 5 6 7 8 9 10 D 0 0 0 0 0 0 0 0 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 B 0 0 1 1 0 0 1 1 0 0 1 A 0 1 0 1 0 1 0 1 0 1 0

Ta le ," De*a$e C#unte& T&ut- Ta le Input Pulses 0 D 0 C 0 B 0 A 0

Table ( provides a count table showing the binary count equivalent to the decimal count of input pulses. The table also shows that the count goes momentarily count from nine *1221, to ten *1212, before resetting to 8ero*2222,. The NAN$ gate provides an output of 1 until the count reach ten. The count of ten is decoded *or sensed in this case , by using logic inputs that are all 1 at the count of ten. 4hen the count becomes ten the NAN$ gate output goes to logical 2, providing a 1 to 2 logic change to trigger the one shot unit, which then provides a short pulse to reset all counter stages. The / signal is used since it is normally high and goes low during the one shot timing period the flip flop in this circuit being reset by a low signal level *active low clearing,. The one shot pulse need only be long enough so that slowest counter stage resets. Actually, at this time only the " 1and "# stage need be reset, but all stages are reset to insure that a new cycle at the count 2222.

Ring Counter
The ring counter is the simplest e5ample of a shift register. The simplest counter is called a ing counter. The ring counter contains only one logical 1 or 2 which it circulates. The total cycle length is equal to the number of stages. The ring counter is useful in applications where count has to be recogni8ed in order to perform some other logical operation. 1ince only one output is ever at logic 1 at given time e5tra logic gates are not required to decode the counts and the flip flop outputs may be used directly to perform the required operation.

)igure 9: 1imple ing Counter Note that in the above diagram the eset will reset /", /# and /% but will put /1 to a logic 1 state. This 1 will circulate when cloc. pulses are applied.

Ta le ." R(n) C#unte& T&ut- Ta le Cl#*/ 1 2 01 1 0 02 0 1 03 0 0 01 0 0

Ta le ." R(n) C#unte& T&ut- Ta le Cl#*/ 3 4 5 01 0 0 1 02 0 0 0 03 1 0 0 01 0 1 0

Up-Down Counter
An up down counter is a bi+directional counter and it can be made to count upwards as well as downwards. 0n other words an up down counter is one which can provide oth count up and down counts operations in a single unit. 0n the previous section it was seen that if triggering pulses are obtained from output the counter is a count up and if the triggering pulses are obtained from outputs, the counter is a count down. )igure ; gives an up down counter. 4hen the count up signal is high the AN$ gate connecting / output and count up siganl gives and output 1 which passes through the < gate to trigger the ne5t flip flop. This results in the count up operation. 1imilarly a signal from count down line will result the circuit to act as a down counter.

Figure #: Up Down Counter

BCD Counter
0t is a special case of a decade counter in which the counter counts 2222 to 1221 and then resets. The output weights of the flip flops in these counters are in accordance with ;%"1 code. )or instance, at the end of seventh cloc. pulse, the output sequence will be 2111 *$ecimal euivalent of 2111 as per ;%"1 code is 9,. These counters will thus be different from other decade counters that provide the same count by using some .ind of forced feedbac. to s.ip some of the natural binary counts )igure 7 shows a counter of the BC$ type.

Figure $: BCD Counter

Fre%uen!y Counter
)requency counter is a digital device which can be used to measure the frequency of the periodic waveforms. The bloc. diagram of frequency counter is shown in )igure 12.

Figure 1&: Fre%uen!y Counter A signal having time period t applied at one of the input terminal of AN$ gate. 4hile a un.nown signal is also applied at the other input terminal of the AN$ gate. =ence, it is used as a cloc. for counter indicates the frequency of the un.nown signal in respect to this time period. The time interval of the counter may be called contents. >et us suppose that time period of gate signal is one second and un.nown signal is a square wave of "&2 =ert8. 0n this condition counter counts "&2 at the end of one second. This will be frequency of un.nown signal.

S'i(t Regi)ter)
A register is a device which is used to store information. )lip flops are often used to ma.e a register. -ach flip flop can store 1+bit of information and therefore for storing a n+bit word n+flip+flops are required in the register for e5ample a computer employing 1(+bit word length requires 1( flip+flops to hold the number before it is manipulated. The input to a register or output from it may be either in serial or parallel form depending upon the requirement.

S'i(t Regi)ter
A shift register is a storage device that used to store binary data. 4hen a number of flip flop are connected in series it is called a register. A single flip flop is supposed to stay in one of the two stable states 1 or 2 or in other words the flip flop contains a number 1 or 2 depending upon the state in which it is. A register will thus contain a series of bits which can be termed as a word or a byte. 0f in these registers the connection is done in such a way that the output of one of the flip flop forms in input to other, it is .nown as a shift register. The data in a shift register is moved serially *one bit at a time,. ! The shift register can be built using 1, ?@ or $ flip+flops various types of shift registers are available some of them are given as under. 1. 1hift >eft egister ". 1hift ight egister #. 1hift Around egister %. Bi+directional 1hift egister

S'i(t *e(t Regi)ter

A four stage shift+left register is shown in figure 1. The individual stages are ?@ flip+flops. Notice that the date input consists of opposite binary signals, the reference data signal going to the ? input and the opposite data signal going to the @ input. )or the $+type stage the single data input line is connected as the $+input.

Figure 1: S'i(t Regi)ter) +a, -. +b, D-type The shift pulse is applied to each stage operating each simultaneously. 4hen the shift pulse occurs the data input is shifted in to that stage. -ach stage is set or reset corresponding to the input data at the time the shift pulse occurs. Thus the input data bit is shift in to stage A by the first shift pulse. At the same time the data of stage A is shifted into the stage B and so on for the following stages. At each shift pulse data stored in the register stages shifts left by one stage. New data shifted into stage A, whereas the data present in stage $ is shifted out to the left for use by some other shift register or computer unit. )or e5ample consider starting with all stages reset all /+outputs to logical 2 and applying steady logical 1 input as data input stage A. Table 1 shows the data in each stage after each of four shift pulses. Notice table " how the logical 1 input first shifts into stage A and then left to stage $ after four shift pulses. As another e5ample consider shifting alternate 2 and 1 data into stage A starting with all stages 1. Table " shows the data in each stage after each of four shift pulses. )inally as a third e5ample of shift register operation. Consider starting with the count in step % of table " and applying four more shift pulses with placing a steady logical 2 input as data input to stage A table # show this operation.

Table 1 OPERATION OF SHIFT-LEFT REGISTER Shift Pulse D C B A

0 1 2 3 4

0 0 0 0 1

0 0 0 1 1

0 0 1 1 1

0 1 1 1 1

Table 2 OPERATION OF SHIFT-LEFT REGISTER Shift Pulse 0 1 2 3 4 D 1 1 1 1 0 C 1 1 1 0 1 B 1 1 0 1 0 A 1 0 1 0 1

Table 3 OPERATION OF SHIFT-LEFT REGISTER Shift Pulse 0 1 2 3 4 D 0 1 0 1 0 C 1 1 1 0 1 B 1 1 0 0 0 A 1 0 0 0 0

Consider the data in stage A as least significant *"o, bits *>1B, and those in stage $ as most significant bits A1B shift+left register operation provides data starting with A1B bit. A few points should be made clear in register operation. 1. The number of shift pulses be the same as the number of shift in register stages.Consider the data in stage A as least significant *"o, bits *>1B, and those in stage $ as most significant bits A1B shift+left register operation provides data starting with A1B bit. A few points should be made clear in register operation. ". Changes in the shift stages ta.e place simultaneously but only the shift pulse occurs.

#. $ata shift into a register stage depends only on what logic levels were present at input terminals ? and @ at the time the shift pulse occurred. Changes that then ta.e place resulting from data shifted will not affect the ne5t stage until the ne5t shift pulse occurs.

S'i(t Rig't Regi)ter

1ometimes it is necessary to shift the least significant digit first, as when addition is to be carried out serially. 0n that case a shift right register is used as in )igure " input data is applied to stage $ and shifted right. The shift operation is the same as discussed in 1hift >eft egister e5cept that data transfers to the right. Table % shows the action of shifting all logical 1 inputs into an initially reset shift register. 0n addition to shifting data register, data into a register data is also of a register. Table & shows register operation for an initial value of 1121. Notice that the output from stage A contains the binary number each bit *starting initially with >1B, appearing at the output of each shift step. 0n the present e5ample it was assumed that logical 2 was shifted as input data so that after four shift pulses have occurred the data has passed through the register and the stages are left reset after the fourth shift pulse.

Figure 2: S'i(t Rig't Regi)ter +a, D-type +b, -.

Table

SHIFT RIGHT OPERATION Shift Pulse 0 1 2 3 4 D 0 1 1 1 1 C 0 0 1 1 1 B 0 0 0 1 1 A 0 0 0 0 1

Table ! SHIFTED O"T OF SHIFT RIGHT REGISTER Shift Pulse 0 1 2 3 4 D 1 0 0 0 0 C 1 1 0 0 0 B 0 1 1 0 0 A 1 0 1 1 0

S'i(t /roun Regi)ter

4hen it is required to shift data out of a register with out losing the initial data a shift around register can be used. )igure # shows the ?@ stages in a shift right, shift around register connection. All that was needed was connection of the input of stage A as into the stage $. Then as four shift pulses move the binary data into stage A, the data being shift out of stage A is shift into stage $ and returns into the register.

Figure 0: S'i(t Rig't /roun Regi)ter

Table # ARO"ND ACTION $ITH SHIFT RIGHT REGISTER Shift Pulse 0 1 2 3 4 D 1 1 0 1 1 C 1 1 1 0 1 B 0 1 1 1 0 A 1 0 1 1 1

Table ( shows the result of shifting the binary number 1121 through *and around, the shift register. Notice that after four shift pulses have occurred the initial value is again in the shift register. To see how any action has ta.en place other than Bust shifting the number around there register consider tow shift register stages as in )igure % each register, shows in bloc. form, is a four stage shift right register. -5ternally connecting the A and output of register 1 bac. to the data input of the same register results in it acting as a shift around register. The logic signal appearing at output A and is also shifted into register ". Table 9 shows the operation of starting with 1121 in register 1 and 222 in register " if the shift around of register 1 were not used and data input were left uncommented *logical 2, then after four shift pulses the data originally in register 1 would be in register ", with register 1 then reset.

Figure 1: Two S'i(t Rig't Regi)ter)

Table % OPERATION OF SHIFT REGISTERS OF FIG"RE Shift Pulse 0 1 2 3 4 D 1 1 0 1 1 C 1 1 1 0 1 B 0 1 1 1 0 A 1 0 1 1 1 H 0 1 0 1 1 G 0 0 1 0 1 F 0 0 0 1 0 E 0 0 0 0 1

Bi ire!tional S'i(t Regi)ter

A bidirectional shift register is one which can do both the shift left and shift right operations. The arrangement is shown in )igure & there are two separate sets of flip+flops. The following steps are controlled by a cloc. sequentially. The cloc. and timing arrangements have not been shown in the figure. The lower register is the one in which the data being shifted right or left. The upper register is being used as a temporary storage. The steps are as follows. 1. The contents of the lower register are gated up directly to the upper register, which is assumed to have been cleared previously. This is a parallel transfer of data and is achieved by the first pulse or gate up pulse applied as the gate up terminals. ". All the lower registers are reset i.e. set 62 by giving a pulse at the reset terminals.

#. The contents of the upper register are gate down to the lower register either one position to the right or to the left as desired. This is again a parallel transfer of data. %. The upper register is reset for the ne5t shift operation.

/)yn!'ronou) an Syn!'ronou) S'i(t Regi)ter)

Asynchronous circuits changes state each time the input changes the state, while synchronous circuit changes state only when triggered by a momentary change in the input signal. This momentary change is called triggering. 1hift registers are made of flip flops their operation depends upon the state at the flip flop and their operation depends upon the state at the flip flops. )lip flops changes their states due to triggering when flip flop change their state on the base of input pulse then it is called -dge triggering. 0n edge triggering flip flop change its state on the basses of >eading edge or trailing edge. 4hen flip flop wor.s on the bases of change in $C level, that is called Asynchronous Triggering. And the shift registers wor. on this principle are called Asynchronous shift registers. <n the other hand, shift registers changes their state only when triggered by cloc. pulse are called 1ynchronous shift registers these type of shift registers usually used in counters.

Spee o( 2i!ropro!e))or
The speed of microprocessor indicates that how much it is speedy to e5ecute different programes or instructions. There are different points which are involved in a speed of microprocessor which are e5plained below. Cache built into the CC' itself is referred to as Level 1 (L1) cache. Cache that resides on a separate chip ne5t to the CC' is called Level 2 (L2) cache. 1ome CC's have both >1 and >" cache built+in and designate the separate cache chip as Level 3 (L3) cache. !

13 245S +2illion 4n)tru!tion) 5er Se!on ,

This method e5plains that how much instructions are e5ecuted in one second. This method is not useful and cannot be applied because every program has a different number of instructions from another program.

23 Clo!6 Fre%uen!y o( O)!illator

As we .now that the frequency of microprocessor operates all the functions of the functions of microprocessor so, when this frequency is low its operations will not e5ecute faster and vice verso. The frequency of the microprocessor is indicated in A=8

03 5arallel 5ro!e))ing

0t is the architecture of microprocessor which allows the computing process to divide into two parts and to e5ecute these parts or instructions at a time. 1o as the data is divided and processed by two microprocessors therefore the speed will increase.

13 Co-pro!e))ing

The co processing is same as parallel processing but in co+processing separate 0C is used to perform some special functions. The co+processor is designed for special purpose in such a way that it completes these special functions at very high speed as compared to main processor. 0n this condition as the programs or instructions are e5ecuted by two processors so its speed will increase. The co+processor is connected in parallel with main processor.

53 Ca!'e 2e7ory
A very serious problem that a microprocessor faces is the low speed of main memory. As the main memory cannot give the instructions *which are used frequently, fast enough to the microprocessor, therefore another memory is used which has the capability to deliver or give these instructions very fast. This is a very fast memory which stores those instructions which are used frequently. Now the processor can ta.e or request these instructions at very fast speed from cache memory which increases the speed of processing. 0ts si8e is normally ; @B to &1" @B. Cache memory is of three types or levels 1. >evel <ne ". >evel Two #. >evel Three

"3 5ipe *ining

To increase the speed of the microprocessor other technique is used which called pipe is lining. 0n this technique a number of instruction are e5ecuted at the same time which in increases the speed of microprocessor.

83 9i er Bu)e)
That microprocessor which has wider buses especially data bus automatically speeds up the processing of microprocessors. This is because of pic.ing up many bytes as compared to one byte as in ;2#&.

#3 Serial 4:O +U/RT,

)or the communication with the input and output a circuits or system is used to feed the data to microprocessor and to receive and deliver this data to output. This whole system is called serial 0D<. one of the e5ample of serial 0D< which functions from series to parallel and from parallel to series. The speed of this system indicates the speed of microprocessor greater the speed, greater will be the speed of microprocessor and vice versa.

/ppli!ation) o( Flip Flop)

)lip flops are used in digital electronics some of its main applications are described below.

Data Storage
A flip flop store one bit at a time in digital circuit. 0n order to store more than one bit flip flop can be connected in series and parallel called registers. A register is simply a data storage device for a number of bits in which each flip flop store one bit of information *2 or 1,. Thus a % bit register consists of % individual flip flops, each able to store one bit of information at a time.

! Figure 1: Bit Binary Regi)ter )igure 1 shows a % bit register. Any number from *2222," to *1111," may be stored in it simply by setting or resetting the appropriate flip flops. >et us suppose that flip flop one is 1-T*1, , )lip flop " is -1-T*2,, flip flop # is -1-T*2, and flip flop % is 1-T*1,, the binary number stored in this register is *1221,".

Data Tran)(er

)lip flops can also be used e5tensively to transfer the data. )or this purpose shift register is used. A shift register is a register which is able to shift or transfer it content within itself without changing the order of the bits. 0t may be designed to shift or transfer data either left or right. The data is shifted or transferred one bit at a time, when a cloc. pulse is applied. The shift register can be used for temporary storage of data. The shift register is used for multiplication and division where bit shifting is required. The shift register can be built using 1, ?@ or $ flip flops. A four stage shift right register is shown in )igure ". 0nput data is applied to store $ and shifted right.

Figure 2: S'i(t Rig't Regi)ter -ach flip flop is controlled by the output of the proceeding flip flop. Cloc. signal is applied simultaneously to all flip flops. 4ith each cloc. pulse information is transferred to ne5t flip flop as shown below.

D 0

C 0

B 0

A 0

1&11 /(ter 1)t Clo!6

1 1 0 1

0 1 1 0

0 0 1 1

0 0 0 1

0n the above four bit shift right the information from input could be transferred to output in four cloc. pulses. This is an e5ample of data transfer.

Counter
Another maBor application of flip flops is a digital counter. 0t is used to count pulses or events and it can be made by connecting a series of flip flops. Counter can count up to " n. 4here n is the number

of flip flops. )igure # shows a simplest binary ripple counter made by flip flops. 0t consists of connections of flip flop without any logic gate. -ach flip flop is triggered by the output of its proceeding flip flop.

Figure 0: Four )tage Counter They are used in digital equipments, cloc.s, frequency counters and computers etc.

Fre%uen!y Di;i)ion
)lip flops can divide the frequency of periodic waveform. 4hen a pulse wave is used to toggle an flip flop, the output frequency becomes one half the input frequency, as shown in )igure %

Figure 1: -. Flip Flop U)e a) / Fre%uen!y Di;i)ion The output of each flip flop is half the frequency of an input. 0f the input frequency is 1(2 @=8 then output of each flip flop would be so after first flip flop, %2 after second flip flop and "2 after third flip flop. 0nput frequency 1(2 @=8 )requency of first flip flop ;2 @=8 )requency of "nd flips flop %2 @=8 )requency of #rd flips flop "2 @=8

BOO*E/N /*<EBR/
The circuits in digital computers follow the logic of mind. =ence symbolic logic, invented by Boolean for solving logical problems, can be applied in the analysis and design of digital circuits. This logic is a binary or two valued logic , and resembles ordinary algebra in many respects. =ence this logic is also called Boolean algebra. Boolean algebra permits only two values or states for a variable. 0n logic, these two states represent EtrueE and EfalseE and in circuits they represent EonE and EoffE or the EcutoffE and EsaturationE state of Boolean of an electronic device. The two permitted states of Boolean algebra are usually represented by 2 and 1. <nly three operation are employed in Boolean algebra. These operations are: ! 1. The OR addition represented by a plus *=, sign. ". The AND multiplication represented by cross *>, or a dot *3, sign. #. The NOT operation represented by a bar over a variable. The operations indicated by the symbol = and *3, are not the same in ordinary algebra. The principle of duality is an important concept in Boolean algebra, particularly in proving various theorems. Briefly stated, the principle of duality pronounces that given an e5pression which is always valid in boolean algebra, the dual e5pression is also always valid. The dual e5pression is found by replacing all F operations with *.,, all *., operation with *F, all 1Es by 2Es, and all 2Es by 1Es. As an e5ample given the e5pression. A*BFC,6A.BFA.C The dual of the e5pression is: AF*B.C,6*AFB,*AFC, Now observe that both these were stated as postulates of Boolean algebra. The principle of duality will be used e5tensively in proving Boolean algebra theorem. 4e shall prove that an e5pression is valid. <nce it is proved, by the principle of duality, its dual is also valid. =ence, our effort in providing various theorems is reduced to half. As Boolean algebra deals with a set consisting of only two elements, it is in principle, possible to prove every theorem by considering all possible cases, that is y truth table method. 1ome postulates, laws and theorems are given as under: 1. 4 e7poten!y: *a, A F A 6 A *b, A . A 6 A Cart *a, and *b, of this theorems are dual of each other. 1o it is sufficient to prove either part. >et us prove *b, part. >.=.1 6 A . A 6A.AF2 6A.AFA. 6A.*AF ,

6A.1 6 A 6 .=.1 4e have applied various postulates in proving this theorem. 0n general, proof of Boolean algebra theorem is simple: ". *a, A F 1 6 1 *b, A . 2 6 2 >et us prove part *b, of this theorems: >.=.1 6 A . 2 6A.2F2 6A.2FA. 6A.*2F , 6A. 6 2 6 .=.1 Cart *a, can be similarly proved. 0n any case, part *a, is seen to be dual of part *b,. This theorem is important as it emphasi8es the properties of the unique elements 1 and 2. #. /b)orption: *a, A F A . B 6 A *b, A . * A F B, 6 A >et us prove part *a, >.=.1 6 A F A . B 6A.1FA.B 6 A . * 1 F B, 6A.*BF1, 6 A 6 .=.1. Cart *b, is dual of part *a,. >et us try to prove part *b, by truth table method. 0t is " argument theorem, therefore in all these are four cases. 4e find the e5pression on the >.=.1 and .=.1 is same for all these four cases.

A 0 0 1 1
%. *a, A F .B6AFB *b, A . * F B , 6 A . B

B 0 1 0 1

A2B 0 1 1 1

A 3 ( A 2 B) 0 0 1 1

>et us prove part *a, of this theorem >.=.1 6 A 6 .B 6*AF ,.*AFB, 61.*AFB, 6*AFB,.1 6*AFB, 6 .=.1

Cart *b, of the theorem is dual of part *a,

DECODER ? ENCODER
De!o er
$ecoder is a circuit which converts the digital signal into analog signal. 0ts input will be in digital form while the output will be a continuous sine wave or analog wave.

De!o er Cir!uit Diagra7

#utput 0.0 V

1 1 1 1 1 1 1 1 1 1 1 1 1

0.2 V 0.4 V 0.6 V 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1.8 V 2.0 V

2.2 V 2.4 V

2.6 V 2.8 V

3.0 V

E@planation
As shown in the given diagram there are four resistances connected to the input of the amplifier through switches. 4henever, the input bite is one the switch is closed while it is open for 8ero bite. The ouput is given by ! <utput 6 gain G input 4hile Hain 6
f

D in
f

4here the value of

61212

And is constant while the in is the input resistances which changes every time according to the input bites. The value of in depends upon the number of switches closed. 0f the input is the input resistance are closed while C and $ are open.
in 6 9& @ DD 1&2 @ 6 12,222D&2,222 6 2." G # 62.( I n

becomes 9& @ parallel to 1&2 @. this is because switches A and B

This is the prove for the truth table for the line %

En!o er
-ncoder is a circuit which converts the analog signal in to the digital signal.

En!o er Cir!uit Diagra7

Input 0.0 V 0.2 V 0.4 V 0.6 V 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V 1.8 V 2.0 V 2.2 V 2.4 V 2.6 V 2.8 V

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3.0 V

The above circuit consists of the following parts.

13 Co7parator
0t is used to compare the two input values. 0f A is greater than B the output will be one. <therwise it will be 8ero.

23 Counter
0t is an electronic device which counts the number in binary system. 0t increases by one number whenever high input pulse is given.

03 /ND <ate
The output of the AN$ gate is given to the counter which becomes the pulse for it. This pulse is high whenever the output of the AN$ gate is one.

13 Digital to /nalog Con;erter

The output of the counter is given to digital converter which produces analog output and is given to comparator.

Operation o( En!o er Cir!uit

4hen input A is set it means that the counter is instructed to count up to that level at that time the counter output is 2222. As a result the B signal is 2 volt. The comparator compare A and B signals. As A is greater than B so the output of the comparator is one. This input signal is given to the counter which counts the ne5t number. This is converted to analog signal which is again less than three volt and the same process continuous till the B signal is equal or becomes high then A.