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NAND AND NOR FLASH MEMORY

Kshitij Jain, 2009ME10588, Group 19, EEL201

AbstractAs the demand for lower power, lighter and more robust products is increasing, NAND and NOR flash memory have become the leading storage choice for a broad range of applications. This paper discusses the development of flash memory with emphasis on NAND and NOR flash memory. The functioning of the flash memory is discussed first, followed by details about the NAND and NOR memory architecture, their differences, respective advantages and limitations, and their applications. Index TermsNon-Volatile Storage Memory, Floating Gate, Control Gate, Fowler-Nordheim Tunneling, Memory Block, Wordline, Bitline, Hot Electron Injection

channel, and is surrounded by a thin oxide layer of silicon dioxide (SiO2) all around. The control gate is connected to a wordline which is used to switch on/off all the transistors connected to it at once, while the floating gate is connected to a bitline which is used to perform read and write operation in the memory cell.

I. INTRODUCTION Complimentary metal-oxide semiconductor memories (CMOS) can be divided into two main categories: random access memory (RAM) which are volatile and lose the stored information once the power is switched off, and read only memory (ROM) which are non-volatile and keep stored information even when the power supply is switched off. The non-volatile storage devices market share has been substantially growing since the advent of Programmable ROM (PROM) which could be programmed only once. Due to its lack of flexibility, PROM was replaced by Electrically Programmable ROM (EPROM), which could be erased as well using ultraviolet light. EPROM was then followed by Electrically Erasable and Programmable ROM (EEPROM) which required application of an electric field to erase stored information, which in turn was replaced by the more flexible and less expensive flash memory. Flash memory is a type of non-volatile semiconductor memory device. It is a development over the EPROM and EEPROM and can be electrically programmed and erased. The term flash in it signifies that a large chunk of memory can be erased from it at a time, unlike EEPROM, where each byte is erased individually. II. FLASH MEMORY A. Structure Flash memory stores data in an array of memory cells. These memory cells are made from floating-gate MOSFETs (known as FGMOS), which resemble a standard MOSFET except that the former has two gates instead of one. On top is the control gate as in a standard MOS transistor, with the new gate called floating gate just below it. The floating gate is interposed between the control gate and the MOSFET A FGMOS Transistor B. Working As the floating gate in a memory cell is electrically isolated from all sides, electrons are trapped in the floating gate. The threshold of the memory is decided by the charge on the floating gate. When electrons are present on the floating gate, it is said to be programmed, indicating a logic-0. When electrons are removed from the floating gate, the transistor starts conducting, indicating a logic-1. Fowler-Nordheim tunneling and hot electron injection technologies are used to alter the charge present in the floating gate and perform the required read, write and erase operations. Fowler-Nordheim Tunneling Fowler-Nordheim Tunneling is a process where electrons are transported through a barrier. In FGMOS, the barrier is considered as the thickness of the SiO2 insulator layer surrounding the floating gate. While writing, a high voltage, usually 10 to 13 volts, is applied to the floating. The charge enters the floating gate through the bitline and drains to a ground. This charge causes the floating gate transistor to act like an electron gun. The excited electrons are pushed and get trapped on the other side of the thin oxide layer. These negatively charged electrons act as a barrier between the control gate and the floating gate, breaking the only link of the floating gate to the wordline. This trapped charge is then compared to the threshold of the gate by the cell sensor, and if it is more than 50% of the latter, the cell is said to programmed, indicating a logic-0. While erasing, the flash memory cell needs to be reset to a logical 1, which is its raw and default state because floating gates carry no negative charges. It is achieved by applying a voltage across the source and control gate (word line). The

2 gate voltage is in the range of -9V to -12V, while a voltage around 6V is applied to the source. The electrons in the floating gate are pulled off and transferred to the source by FN tunneling. In other words, electrons tunnel from the floating gate to the source and substrate, restoring the cell to its default state. III. NOR FLASH MEMORY The NOR architecture is currently the most popular flash architecture. NOR flash memory was first introduced by Intel in 1988. Cells in NOR-flash are connected in parallel to the bit lines so that each cell can be read/write/erase individually. This parallel connection of cells closely resembles to the parallel connection of transistors in a CMOS NOR gate, that's how it derives the name as NOR flash. A. Architecture

Writing (FNt)

Erasing (FNt)

Hot Electron Injection (HEI) Hot carrier injection is a phenomenon in solid state electronic devices where an electron or a hole gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. In MOSFETs, HEI refers to the effect where an electron is injected from the conducting channel in the silicon substrate to the gate dielectric, SiO2.This technology is used only for programming a NOR flash cell. While writing a NOR flash cell, a voltage (approx. 7V) is applied to the drain to activate the electrons (hot electrons) around the channel. A voltage, about 12 V, is also applied to the control gate. The activated electrons, then, travel across the oxide layer and get trapped on the other side of the oxide layer, changing the state of the cell to a 0. Aside from active transistors, the largest contributor to area in the cell array is the metal to diffusion contacts. NOR architecture requires one contact per two cells, which consumes the most area of all the flash architecture alternatives. As can be comprehended from the NOR architecture, NOR flash memory supports one-byte random access, which allows machine instructions to be retrieved and run directly from the chip, in the same way that a traditional computer will retrieve instructions directly from main memory, enabling short read times required for the random access of microprocessor instructions. To read the data, a voltage is applied to the control gate, and the MOSFET channel will be either conducting or remain insulating, based on the threshold voltage of the cell, which is in turn controlled by charge on the floating gate. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data. For this purpose, a voltage around 5V is applied to the control gate and around 1V to the drain. C. Types Classification of flash memory is done on the basis of memory array architecture. Some of the types developed till now are DINOR flash memory, AND flash memory, NAND flash memory and NOR flash memory. B. Operations Electron trapping (writing) in the NOR flash cell is done by hot electron injection (HEI), while electron removal (erasing) is done by Fowler-Nordheim tunneling. Reading from the cell has already been discussed above. C. Advantages The biggest advantage of NOR flash is its one-byte random access ability which makes it highly efficient in reading operation. Also, it makes it possible for most microprocessors to use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly from the NOR flash without needing to be copied into RAM first. Also, NOR flash has provisions for byte programming.

3 D. Disadvantages NOR flash is slower than the other alternative flash architectures in programming and erasing operations. Also, it is the largest in chip area, making it the most expensive as well. E. Applications NOR Flash is ideal for lower-density, high-speed read applications, which are mostly read only, often referred to as code-storage applications. NOR flash is extensively used in portable electronics devices, such as cellular phones and PDAs. IV. NAND FLASH MEMORY NAND flash was introduced by Toshiba in 1989. In NANDflash, cells are connected in series resembling a NAND gate, and so the name. The series connection prevents the cells from being programmed individually. These cells must be read in series. A. Architecture

As can be comprehended from the NAND architecture, NAND flash memory supports sequential access unlike NORs random one-byte access. The ability of the NAND to erase and program a block at a time makes it faster than its NOR counterpart in these operations. B. Operations In the NAND Flash the read and program operation takes place on a page basis (i.e. 528 bytes at a time for most of NAND devices) rather than on a byte or word basis like NOR Flash the size of data I/O register matches the page size. The erase operation takes place on a block basis. There are only three basic operations in a NAND Flash: read a page, program a page and erase a block. Electron trapping (writing), as well as electron removal (erasing) in the NAND flash cell is done by Fowler-Nordheim tunneling. Reading is done in the same way as NOR cell. C. Advantages NAND flash is faster than the other alternative flash architectures in programming and erasing operations. Also, it is has a very small chip area, reducing the cost per stored bit information. D. Disadvantages NAND flash is slow in random access of cells. Also, byte programming is very difficult in NAND flash memory. NAND flash cannot be used as a XIP memory. E. Applications NAND Flash is very similar to a hard-disk drive. It is sectorbased (page-based) and well suited for storage of sequential data such as pictures, video, audio, or PC data. NAND Flash is used in virtually all removable cards, including USB drives, secure digital (SD) cards, memory stick cards, Compact Flash cards, and multimedia cards (MMCs).

The NAND Flash array is grouped into a series of blocks, which are the smallest erasable entities in a NAND Flash device. For most NAND Flash devices there are 512 bytes / 256 words in the Cell Array page area (also called data area) and an extra 16 bytes / 8 words in the Spare Cell Array page area (also called spare area). There are total 528 bytes / 264 words per page and such page is called small page. For huge capacities (usually 1 Gbit and more) large page is used. It contains 2048 bytes / 1024 words of data area and 64 bytes / 32 words of spare area (2112 bytes / 1056 words total). NAND architecture requires one contact per block, which makes its cell size 40% of the size of a NOR cell , thus providing the higher densities required for todays low-cost consumer devices in a significantly reduced die area.

V. COMPARISON OF NAND VS. NOR A. Capacity Due to its small size as compared to the NOR flash memory, the capacity of NAND to store information is much

4 more than NOR flash. While NAND flash applications with storage upto 32 GB have been developed, NOR flash has only been used for storing 1GB till now. B. Cost per bit The cost per bit is lower for NAND flash as compared to NOR flash, which, in turn, makes NAND cheaper than or flash. C. Write and read speed The write speed is higher for NAND flash, while NOR flash is faster when it comes to reading. D. Active Power and Standby Power Active power is dependent on how memory is used. NOR is typically slow on writes and consumes more power than NAND, but consumes less power when reading. Standby power required for NOR flash memory is lower than that required for NAND flash memory. E. Code execution NOR flash finds great applications in code execution due to its one byte random access ability, which makes it an XIP memory. F. File storage use NAND flash, due to its ability to store more information in less area, holds a major market share when it comes to file storage use. G. Lifespan NAND flash has about 10 times the lifespan of the NOR flash memory. VI. CONCLUSION Consumer electronics and embedded software devices are using larger amounts of flash memory for nonvolatile storage than ever before. One important decision in designing such devices is what kind of flash memory to use: NAND or NOR? NOR flash memory has traditionally been used to store relatively small amounts of executable code for embedded computing devices such as PDAs and cell phones. NOR is well suited to use for code storage because of its reliability, fast read operations, and random access capabilities. Because code can be directly executed in place, NOR is ideal for storing firmware, boot code, operating systems, and other data that changes infrequently. NAND flash memory has become the preferred format for storing larger quantities of data on devices such as USB Flash drives, digital cameras and MP3 players. Higher density, lower cost, and faster write and erase times, and a longer rewrite life expectancy make NAND especially well suited for consumer media applications in which large files of sequential data need to be loaded into memory quickly and replaced with new files repeatedly. The choice between using NAND and NOR Flash may not be a simple one for the complex embedded devices being developed today. While ever-larger media files are driving increased demand for inexpensive NAND, powerful new operating systems and intricate applications running on fast processors call for the kind of fast-executing code NOR can support. Whichever type of flash is used in a device, there are certain negative performance characteristics that need to be mitigated. Well-designed software strategies can be very effective in increasing the performance and reliability of Flash hardware. The goals of flash memory management software include avoiding loss of data, improving effective performance and increasing media lifespan, and are the challenge ahead. VII. REFERENCES [1] G. Crisenza, R. Annunziata, E. Camerlenghi, and P. Cappelletti, Non volatile memories: Issues, challenges and trends for the 2000s scenario, in Proc. ESSDERC96, G. Baccarani and M. Rudan, Eds. Bologna, Italy: Editions Frontieres, 1996, pp. 121130. [2] S. Wells and D. Clay, Flash solid-state drive with 6 MB/s read/write channel ABS data compression, in Proc. ISSCC Conf., San Francisco, CA, no. WP 3.6, 1993, p. 52. [3] E. Suzuki, H. Hirashi, K. Ishii, and Y. Hayashi, A low-voltage alterable EEPROM with metal-oxide-nitrideoxidesemiconductor (MONOS) structure, IEEE Trans. ElectronDevices, vol. ED-30, no. 2, pp. 122127, 1983. [4] E. Suzuki, K. Miura, Y. Hayashi, R.-P. Tsay, and D. Schroder, Hole and electron current transport in metal-oxidenitrideoxide-silicon memory structures, IEEE Trans. Electron Devices, vol. 36, no. 6, pp. 11451149, 1989. [5] S. T. Wang, On the IV characteristics of floating-gate MOS transistors, IEEE Trans. Electron Devices, vol. ED-26, no. 9, pp. 12921294, 1979. [6] M. Wada, S. Mimura, H. Nihira, and H. Iizuka, Limiting factors for programming EPROM of reduced dimensions, IEDM Tech. Dig., 1980, pp. 3841. [7] A. Kolodny, S. T. K. Nieh, B. Eitan, and J. Shappir, Analysis and modeling of floating gate EEPROM cells, IEEE Trans. Electron Devices, vol. ED-33, no. 6, pp. 835844, 1986. 8] K. Prall, W. I. Kinney, and J. Marco, Characterization and suppression of drain coupling in submicrometer EPROM cells, IEEE Trans. Electron Devices, vol. ED-34, no. 12, p. 2463, 1987.