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Frequently Asked VLSI Interview Questions and Answers

1) What is latch up? Latch up pertains to a !ailure "echanis" wherein a parasitic thyristor #such as a parasitic silicon controlled recti!ier$ or S%&) is inadvertently created within a circuit$ causin' a hi'h a"ount o! current to continuously !low throu'h it once it is accidentally tri''ered or turned on( )ependin' on the circuits involved$ the a"ount o! current !low produced *y this "echanis" can *e lar'e enou'h to result in per"anent destruction o! the device due to electrical overstress #+,S) ( -)Why is .A.) 'ate pre!erred over .,& 'ate !or !a*rication? .A.) is a *etter 'ate !or desi'n than .,& *ecause at the transistor level the "o*ility o! electrons is nor"ally three ti"es that o! holes co"pared to .,& and thus the .A.) is a !aster 'ate( Additionally$ the 'ate leaka'e in .A.) structures is "uch lower( I! you consider t/phl and t/plh delays you will !ind that it is "ore sy""etric in case o! .A.) # the delay pro!ile)$ *ut !or .,&$ one delay is "uch hi'her than the other#o*viously t/plh is hi'her since the hi'her resistance p "os0s are in series connection which a'ain increases the resistance)( 1)What is .oise 2ar'in? +3plain the procedure to deter"ine .oise 2ar'in 4he "ini"u" a"ount o! noise that can *e allowed on the input sta'e !or which the output will not *e e!!ected( 5)+3plain si6in' o! the inverter? In order to drive the desired load capacitance we have to increase the si6e #width) o! the inverters to 'et an opti"i6ed per!or"ance( 7)Let A and 8 *e two inputs o! the .A.) 'ate( Say si'nal A arrives at the .A.) 'ate later than si'nal 8( 4o opti"i6e delay o! the two series .2,S inputs A and 8 which one would you place near to the output? 4he late co"in' si'nals are to *e placed closer to the output node ie A should 'o to the n"os

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that is closer to the output(

9) What is .oise 2ar'in? +3plain the procedure to deter"ine .oise 2ar'in? 4he "ini"u" a"ount o! noise that can *e allowed on the input sta'e !or which the output will not *e e!!ected( :) What happens to delay i! you increase load capacitance? delay increases( ;)What happens to delay i! we include a resistance at the output o! a %2,S circuit? Increases( #&% delay) <)What are the li"itations in increasin' the power supply to reduce delay? 4he delay can *e reduced *y increasin' the power supply *ut i! we do so the heatin' e!!ect co"es *ecause o! e3cessive power$ to co"pensate this we have to increase the die si6e which is not practical( 1=)>ow does &esistance o! the "etal lines vary with increasin' thickness and increasin' len'th? & ? # @l) A A( 11)For %2,S lo'ic$ 'ive the various techniques you know to "ini"i6e power consu"ption? Bower dissipation?%V-! $!ro" this "ini"i6e the load capacitance$ dc volta'e and the operatin' !requency( 1-) What is %har'e Sharin'? +3plain the %har'e Sharin' pro*le" while sa"plin' data !ro" a 8us? In the serially connected .2,S lo'ic the input capacitance o! each 'ate shares the char'e with the load capacitance *y which the lo'ical levels drastically "is"atched than that o! the desired once( 4o eli"inate this load capacitance "ust *e very hi'h co"pared to the input capacitance o! the 'ates #appro3i"ately 1= ti"es)( 11)Why do we 'radually increase the si6e o! inverters in *u!!er desi'n? Why not 'ive the output o! a circuit to one lar'e inverter? 8ecause it can not drive the output load strai'ht away$ so we 'radually increase the si6e to 'et an opti"i6ed per!or"ance( 15)What is Latch Cp? +3plain Latch Cp with cross section o! a %2,S Inverter( >ow do you avoid Latch Cp? Latch up is a condition in which the parasitic co"ponents 'ive rise to the +sta*lish"ent o! low resistance conductin' path *etween V)) and VSS with )isastrous results( 17) Dive the e3pression !or %2,S switchin' power dissipation? %VE-

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19) What is 8ody +!!ect? In 'eneral "ultiple 2,S devices are "ade on a co""on su*strate( As a result$ the su*strate volta'e o! all devices is nor"ally equal( >owever while connectin' the devices serially this "ay result in an increase in source to su*strate volta'e as we proceed vertically alon' the series chain #Vs*1?=$ Vs*- =)(Which results Vth-FVth1( 1:) Why is the su*strate in .2,S connected to Dround and in B2,S to V))? we try to reverse *ias not the channel and the su*strate *ut we try to "aintain the drain$source Gunctions reverse *iased with respect to the su*strate so that we dont loose our current into the su*strate( 1;) What is the !unda"ental di!!erence *etween a 2,SF+4 and 8H4 ? In 2,SF+4$ current !low is either due to electrons#n channel 2,S) or due to holes#p channel 2,S) In 8H4$ we see current due to *oth the carriers(( electrons and holes( 8H4 is a current controlled device and 2,SF+4 is a volta'e controlled device( 1<)Which transistor has hi'her 'ain( 8H4 or 2,S and why? 8H4 has hi'her 'ain *ecause it has hi'her transconductance(4his is *ecause the current in 8H4 is e3ponentially dependent on input where as in 2,SF+4 it is square law( -=)Why do we 'radually increase the si6e o! inverters in *u!!er desi'n when tryin' to drive a hi'h capacitive load? Why not 'ive the output o! a circuit to one lar'e inverter? We cannot use a *i' inverter to drive a lar'e output capacitance *ecause$ who will drive the *i' inverter? 4he si'nal that has to drive the output cap will now see a lar'er 'ate capacitance o! the 8ID inverter(So this results in slow raise or !all ti"es (A unit inverter can drive appro3i"ately an inverter thats 5 ti"es *i''er in si6e( So say we need to drive a cap o! 95 unit inverter then we try to keep the si6in' like say 1$5$19$95 so that each inverter sees a sa"e ratio o! output to input cap( 4his is the pri"e reason *ehind 'oin' !or pro'ressive si6in'( -1)In %2,S technolo'y$ in di'ital desi'n$ why do we desi'n the si6e o! p"os to *e hi'her than the n"os(What deter"ines the si6e o! p"os wrt n"os( 4hou'h this is a si"ple question try to list all the reasons possi*le? In B2,S the carriers are holes whose "o*ility is lessI aprro3 hal! J than the electrons$ the carriers in .2,S( 4hat "eans B2,S is slower than an .2,S( In %2,S technolo'y$ n"os helps in pullin' down the output to 'round ann B2,S helps in pullin' up the output to Vdd( I! the si6es o! B2,S and .2,S are the sa"e$ then B2,S takes lon' ti"e to char'e up the output node( I! we have a lar'er B2,S than there will *e "ore carriers to char'e the node quickly and overco"e the slow nature o! B2,S ( 8asically we do all this to 'et equal rise and !all ti"es !or the output node( --)Why B2,S and .2,S are si6ed equally in a 4rans"ission Dates? In 4rans"ission Date$ B2,S and .2,S aid each other rather co"petin' with each other( 4hat0s the reason why we need not si6e the" like in %2,S( In %2,S desi'n we have .2,S and B2,S co"petin' which is the reason we try to si6e the" proportional to their

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"o*ility( -1)All o! us know how an inverter works( What happens when the B2,S and .2,S are interchan'ed with one another in an inverter? I have seen si"ilar Qs in so"e o! the discussions( I! the source K drain also connected properly(((it acts as a *u!!er( 8ut suppose input is lo'ic 1 ,AB will *e de'raded 1 Si"ilarly de'raded =L -5)A 'ood question on Layouts( Dive 7 i"portant )esi'n techniques you would !ollow when doin' a Layout !or )i'ital %ircuits? a)In di'ital desi'n$ decide the hei'ht o! standard cells you want to layout(It depends upon how *i' your transistors will *e(>ave reasona*le width !or V)) and D.) "etal paths(2aintainin' uni!or" >ei'ht !or all the cell is very i"portant since this will help you use place route tool easily and also incase you want to do "anual connection o! all the *locks it saves on lot o! area( *)Cse one "etal in one direction only$ 4his does not apply !or "etal 1( Say you are usin' "etal - to do hori6ontal connections$ then use "etal 1 !or vertical connections$ "etal5 !or hori6ontal$ "etal 7 vertical etc((( c)Blace as "any su*strate contact as possi*le in the e"pty spaces o! the layout( d))o not use poly over lon' distances as it has hu'e resistances unless you have no other choice( e)Cse !in'ered transistors as and when you !eel necessary( !)4ry "aintainin' sy""etry in your desi'n( 4ry to 'et the desi'n in 8I4 Sliced "anner( -7)What is "etasta*ility? WhenAwhy it will occur?)i!!erent ways to avoid this? 2etasta*le stateM A un known state in *etween the two lo'ical known states(4his will happen i! the ,AB cap is not allowed to char'eAdischar'e !ully to the required lo'ical levels( ,ne o! the cases isM I! there is a setup ti"e violation$ "etasta*ility will occur$4o avoid this$ a series o! FFs is used #nor"ally - or 1) which will re"ove the inter"ediate states( -9)What is FBDA ? A !ield pro'ra""a*le 'ate array is a se"iconductor device containin' pro'ra""a*le lo'ic co"ponents called Nlo'ic *locksN$ and pro'ra""a*le interconnects( Lo'ic *locks can *e pro'ra""ed to per!or" the !unction o! *asic lo'ic 'ates such as A.)$ and O,&$ or "ore co"ple3 co"*inational !unctions such as decoders or "athe"atical !unctions -:) What is "ini"u" and "a3i"u" !requency o! dc" in spartan 1 series !p'a? Spartan series dc"Ps have a "ini"u" !requency o! -5 2>Q and a "a3i"u" o! -5; -;) What are di!!erent types o! FBDA pro'ra""in' "odes?what are you currently usin' ?how to chan'e !ro" one to another? 8e!ore powerin' on the FBDA$ con!i'uration data is stored e3ternally in a B&,2 or so"e other nonvolatile "ediu" either on or o!! the *oard( A!ter applyin' power$ the con!i'uration data is written to the FBDA usin' any o! !ive di!!erent "odesM 2aster Barallel$ Slave Barallel$

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2aster Serial$ Slave Serial$ and 8oundary Scan #H4AD)( 4he 2aster and Slave Barallel "odes -<) )i!!erence *etween FBDA and %BL)? FBDAM a)S&A2 *ased technolo'y( *)Se'"ented connection *etween ele"ents( c)Csually used !or co"ple3 lo'ic circuits( d)2ust *e repro'ra""ed once the power is o!!( e)%ostly %BL)M a)Flash or +B&,2 *ased technolo'y( *)%ontinuous connection *etween ele"ents( c)Csually used !or si"pler or "oderately co"ple3 lo'ic circuits( d).eed not *e repro'ra""ed once the power is o!!( e)%heaper 1=) What are dc"0s?why they are used? )i'ital clock "ana'er #)%2) is a !ully di'ital control syste" that uses !eed*ack to "aintain clock si'nal characteristics with a hi'h de'ree o! precision despite nor"al variations in operatin' te"perature and volta'e( 4hat is clock output o! )%2 is sta*le over wide ran'e o! te"perature and volta'e $ and also skew associated with )%2 is "ini"al and all phases o! input clock can *e o*tained ( 4he output o! )%2 co"in' !or" 'lo*al *u!!er can handle "ore load( 11)What are di!!erent types o! ti"in' veri!ications? )yna"ic ti"in'M a( 4he desi'n is si"ulated in !ull ti"in' "ode( *( .ot all possi*ilities tested as it is dependent on the input test vectors( c( Si"ulations in !ull ti"in' "ode are slow and require a lot o! "e"ory( d( 8est "ethod to check asynchronous inter!aces or inter!aces *etween di!!erent ti"in' do"ains( Static ti"in'M a( 4he delays over all paths are added up( *( All possi*ilities$ includin' !alse paths$ veri!ied without the need !or test vectors( c( 2uch !aster than si"ulations$ hours as opposed to days( d( .ot 'ood with asynchronous inter!aces or inter!aces *etween di!!erent ti"in' do"ains( 11)Su''est so"e ways to increase clock !requency?

%heck critical path and opti"i6e it( Add "ore ti"in' constraints #over constrain)( pipeline the architecture to the "a3 possi*le e3tent keepin' in "ind latency req0s(

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1-)What is the purpose o! )&%? )&% is used to check whether the particular sche"atic and correspondin' layout#especially the "ask sets involved) cater to a pre de!ined rule set dependin' on the technolo'y used to desi'n( 4hey are para"eters set aside *y the concerned se"iconductor "anu!acturer with respect to how the "asks should *e placed $ connected $ routed keepin' in "ind that variations in the !a* process does not e!!ect nor"al !unctionality( It usually denotes the "ini"u" allowa*le con!i'uration( 11)What is LVs and why do we do that( What is the di!!erence *etween LVS and )&%? 4he layout "ust *e drawn accordin' to certain strict desi'n rules( )&% helps in layout o! the desi'ns *y checkin' i! the layout is a*ide *y those rules( A!ter the layout is co"plete we e3tract the netlist( LVS co"pares the netlist e3tracted !ro" the layout with the sche"atic to ensure that the layout is an identical "atch to the cell sche"atic( 15)What is )F4 ? )F4 "eans desi'n !or testa*ility( 0)esi'n !or 4est or 4esta*ility0 a "ethodolo'y that ensures a desi'n works properly a!ter "anu!acturin'$ which later !acilitates the !ailure analysis and !alse productApiece detection ,ther than the !unctional lo'ic$you need to add so"e )F4 lo'ic in your desi'n(4his will help you in testin' the chip !or "anu!acturin' de!ects a!ter it co"e !ro" !a*( Scan$28IS4$L8IS4$I))Q testin' etc are all part o! this( #this is a hot !ield and with lots o! opportunities) 17)When are )F4 and For"al veri!ication used? )F4M R "anu!acturin' de!ects like stuck at N=N or N1N( R test !or set o! rules !ollowed durin' the initial desi'n sta'e( For"al veri!icationM R Veri!ication o! the operation o! the desi'n$ i(e$ to see i! the desi'n !ollows spec( R 'ate netlist ?? &4L ? R usin' "athe"atics and statistical analysis to check !or equivalence( 19)What is Synthesis? Synthesis is the sta'e in the desi'n !low which is concerned with translatin' your Verilo' code into 'ates and that0s puttin' it very si"plyS First o! all$ the Verilo' "ust *e written in a particular way !or the synthesis tool that you are usin'( ,! course$ a synthesis tool doesn0t actually produce 'ates it will output a netlist o! the desi'n that you have synthesised that represents the chip which can *e !a*ricated throu'h an ASI% or FBDA vendor(