Priority Encoders

VHDL
Following is the VHDL code for a 3-bit 1-of-9 Priority Encoder.
library ieee; use ieee.std_logic_1164.all; entity priority is port ( sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0)); end priority; arc itecture arc i o! priority is begin code "# $000$ w en sel(0) # %1% else $001$ w en sel(1) # %1% else $010$ w en sel(2) # %1% else $011$ w en sel(&) # %1% else $100$ w en sel(4) # %1% else $101$ w en sel(') # %1% else $110$ w en sel(6) # %1% else $111$ w en sel(7) # %1% else $((($; end arc i;

VHDL (One-Hot)
Following is the VHDL code for a 3 to 8 line decoder.
library ieee use ieee.std_logic_1164.all; entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec; arc itecture arc i o! dec is begin res "# $00000001$ w en sel # $000$ else $00000010$ w en sel # $001$ else $00000100$ w en sel # $010$ else $00001000$ w en sel # $011$ else $00010000$ w en sel # $100$ else $00100000$ w en sel # $101$ else $01000000$ w en sel # $110$ else $10000000$; end arc i;

VHDL (One-Cold)
Following is the VHDL code for a 3 to 8 line decoder.
library ieee; use ieee.std_logic_1164.all;

entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec; arc itecture arc i o! dec is begin res "# $11111110$ w en sel # $000$ else $11111101$ w en sel # $001$ else $11111011$ w en sel # $010$ else $11110111$ w en sel # $011$ else $11101111$ w en sel # $100$ else $11011111$ w en sel # $101$ else $10111111$ w en sel # $110$ else $01111111$; end arc i; IO pins Description

s!"#$% res

&elector Data '(t)(t

VHDL
Following is the VHDL code.
library ieee; use ieee.std_logic_1164.all; entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec; arc itecture arc i o! dec is begin res "# $00000001$ w en sel # $000$ else (( unused decoder output $))))))))$ w en sel # $001$ else $00000100$ w en sel # $010$ else $00001000$ w en sel # $011$ else $00010000$ w en sel # $100$ else $00100000$ w en sel # $101$ else $01000000$ w en sel # $110$ else $10000000$; end arc i; IO pins Description

s!"#$% res

&elector Data '(t)(t

VHDL
Following is the VHDL code.
library ieee; use ieee.std_logic_1164.all; entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec;

arc itecture arc i o! dec is begin res "# $00000001$ w en sel # $000$ else $00000010$ w en sel # $001$ else $00000100$ w en sel # $010$ else $00001000$ w en sel # $011$ else $00010000$ w en sel # $100$ else $00100000$ w en sel # $101$ else (( 110 and 111 selector values are unused $))))))))$; end arc i;

VHDL Code
Following is the VHDL code for a *-to-1 1-bit +,- (sing an .f state/ent.
library ieee; use ieee.std_logic_1164.all; entity *u+ is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end *u+; arc itecture arc i o! *u+ is begin process (a, b, c, d, s) begin i! (s # $00$) t en o "# a; elsi! (s # $01$) t en o "# b; elsi! (s # $10$) t en o "# c; else o "# d; end i!; end process; end arc i;

4-to-1 MUX Using C !E !t"te#ent

0he following table shows )in definitions for a *-to-1 1-bit +,- (sing a 1ase state/ent.
IO Pins Description

a2 b2 c2 d Data .n)(ts s!1#$% +,- selector o Data '(t)(t

VHDL Code
Following is the VHDL code for a *-to-1 1-bit +,- (sing a 1ase state/ent.
library ieee; use ieee.std_logic_1164.all; entity /(3 is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0);

end *u+;

o : out std_logic);

arc itecture arc i o! *u+ is begin process (a, b, c, d, s) begin case s is w en $00$ #- o "# a; w en $01$ #- o "# b; w en $10$ #- o "# c; w en ot ers #- o "# d; end case; end process; end arc i;

4-to-1 MUX Using $rist"te %&''ers

0his section shows VHDL and Verilog e3a/)les for a *-to-1 +(3 (sing tristate b(ffers 0he following table shows )in definitions for a *-to-1 1-bit +,- (sing tristate b(ffers.
IO Pins Description

a2 b2 c2 d Data .n)(ts s!3#$% +,- &elector o Data '(t)(t

VHDL Code
Following is the VHDL code for a *-to-1 1-bit +,- (sing tristate b(ffers.
library ieee; use ieee.std_logic_1164.all; entity *u+ is port (a, b, c, d : in std_logic; s : in std_logic_vector (& downto 0); o : out std_logic); end *u+; arc itecture arc i o! *u+ is begin o o o o "# "# "# "# a b c d w w w w en en en en (s(0)#%0%) (s(1)#%0%) (s(2)#%0%) (s(&)#%0%) else else else else %.%; %.%; %.%; %.%;

end arc i;

(o 4-to-1 MUX
0he following e3a/)le does not generate a *-to-1 1-bit +,-2 b(t 3-to-1 +,- with 1-bit latch. 0he reason is that not all selector 4al(es were described in the .f state/ent. .t is s())osed that for the s511 case2 6'6 7ee)s its old 4al(e2 and therefore a /e/ory ele/ent is needed. 0he following table shows )in definitions for a 3-to-1 1-bit +,- with a 1-bit latch.

IO Pins

Description

a2 b2 c2 d Data .n)(ts s!1#$% &elector o Data '(t)(t

VHDL Code
Following is the VHDL code for a 3-to-1 1-bit +,- with a 1-bit latch.
library ieee; use ieee.std_logic_1164.all; entity *u+ is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end *u+; arc itecture arc i o! *u+ is begin process (a, b, c, d, s) begin i! (s # $00$) t en o "# a; elsi! (s # $01$) t en o "# b; elsi! (s # $10$) t en o "# c; end i!; end process; end arc i;

Logic"l !)i'ters
E*"#ple 1
0he following table shows )in descri)tions for a logical shifter.
IO pins Description

D!8#$% Data .n)(t &EL shift distance selector &'!8#$% Data '(t)(t

VHDL
Following is the VHDL code for a logical shifter.
library ieee; use ieee.std_logic_1164.all; use ieee.nu*eric_std.all; entity ls i!t is port(/0 : in unsigned(7 downto 0); 123 : in unsigned(1 downto 0); 14 : out unsigned(7 downto 0)); end ls i!t; arc itecture arc i o! ls i!t is begin wit 123 select 14 "# /0 w en $00$,

end arc i;

/0 sll 1 w en $01$, /0 sll 2 w en $10$, /0 sll & w en ot ers;

E*"#ple +
-&0 will not infer a Logical &hifter for this e3a/)le2 as not all of the selector 4al(es are )resented.
IO pins Description

D!8#$% Data .n)(t &EL shift distance selector &'!8#$% Data '(t)(t

VHDL
Following is the VHDL code.
library ieee; use ieee.std_logic_1164.all; use ieee.nu*eric_std.all; entity ls i!t is port(/0 : in unsigned(7 downto 0); 123 : in unsigned(1 downto 0); 14 : out unsigned(7 downto 0)); end ls i!t; arc itecture arc i o! ls i!t is begin wit 123 select 14 "# /0 w en $00$, /0 sll 1 w en $01$, /0 sll 2 w en ot ers; end arc i;

E*"#ple ,
-&0 will not infer a Logical &hifter for this e3a/)le2 as the 4al(e is not incre/ented by 1 for each conse9(ent binary 4al(e of the selector.
IO pins Description

D!8#$% Data .n)(t &EL shift distance selector &'!8#$% Data '(t)(t

VHDL
Following is the VHDL code.
library ieee; use ieee.std_logic_1164.all; use ieee.nu*eric_std.all; entity ls i!t is port(/0 : in unsigned(7 downto 0); 123 : in unsigned(1 downto 0);

14 : out unsigned(7 downto 0)); end ls i!t; arc itecture arc i o! ls i!t is begin wit 123 select 14 "# /0 w en $00$, /0 sll 1 w en $01$, /0 sll & w en $10$, /0 sll 2 w en ot ers; end arc i;

rit)#etic Oper"tions
-&0 s())orts the following arith/etic o)erations#

:dders with#
o o o

1arry .n 1arry '(t 1arry .n;'(t

&(btractors :dders;s(btractors 1o/)arators <52 ;52=2 =52 >2 >5? +(lti)liers Di4iders

:dders2 &(btractors2 1o/)arators and +(lti)liers are s())orted for signed and (nsigned o)erations. Please refer to the 6&igned;,nsigned &())ort6 section of this cha)ter for /ore infor/ation on the signed;(nsigned o)erations s())ort in VHDL. +oreo4er2 -&0 )erfor/s reso(rce sharing for adders2 s(btractors2 adders;s(btractors and /(lti)liers.

dders- !&.tr"ctors- dders/!&.tr"ctors

0his section )ro4ides HDL e3a/)les of adders and s(btractors

Unsigned 0-.it dder

0his s(bsection contains a VHDL and Verilog descri)tion of an (nsigned 8-bit :dder 0he following table shows )in descri)tions for an (nsigned 8-bit :dder.
IO pins Description

:!8#$%2 @!8#$% :dd ')erands &,+!8#$% :dd Aes(lt

VHDL

Following is the VHDL code for an (nsigned 8-bit :dder.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(5,6 : in std_logic_vector(7 downto 0); 178 : out std_logic_vector(7 downto 0)); end adder; arc itecture arc i o! adder is begin 178 "# 5 9 6; end arc i;

Unsigned 0-.it dder 1it) C"rry In

0his section contains VHDL and Verilog descri)tions of an (nsigned 8-bit adder with 1arry .n. 0he following table shows )in descri)tions for an (nsigned 8-bit adder with carry.
IO pins Description

:!8#$%2 @!8#$% :dd ')erands 1. 1arry .n &,+!8#$% :dd Aes(lt

VHDL
Following is the VHDL code for an (nsigned 8-bit adder with carry in.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(5,6 : in std_logic_vector(7 downto 0); :0 : in std_logic; 178 : out std_logic_vector(7 downto 0)); end adder; arc itecture arc i o! adder is begin 178 "# 5 9 6 9 :0; end arc i;

Unsigned 0-.it dder 1it) C"rry O&t

0he following table shows )in descri)tions for an (nsigned 8-bit adder with carry
IO pins Description

:!8#$%2 @!8#$% :dd ')erands &,+!8#$% :dd Aes(lt 1' 1arry '(t

VHDL

Following is the VHDL code for an (nsigned 8-bit adder with carry o(t.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arit .all; use ieee.std_logic_unsigned.all; entity adder is port(5,6 : in std_logic_vector(7 downto 0); 178 : out std_logic_vector(7 downto 0); :4 : out std_logic); end adder; arc itecture arc i o! adder is signal t*p: std_logic_vector(; downto 0); begin t*p "# conv_std_logic_vector( (conv_integer(5) 9 conv_integer(6)),<); 178 "# t*p(7 downto 0); :4 "# t*p(;); end arc i;

.n the )receding e3a/)le2 two arith/etic )ac7ages are (sed#

stdBlogicBarith. 0his )ac7age contains the integer to stdBlogic con4ersion f(nction2 that is2 con4BstdBlogicB4ector. stdBlogicB(nsigned. 0his )ac7age contains the (nsigned 6C6 o)eration.

Unsigned 0-.it dder 1it) C"rry In "nd C"rry O&t

0his section contains VHDL and Verilog code for an (nsigned 8-bit adder with 1arry .n and 1arry '(t. 0he following table shows )in descri)tions for an (nsigned 8-bit adder with carry.
IO pins Description

:!8#$%2 @!8#$% 1. &,+!8#$% 1'

:dd ')erands 1arry .n :dd Aes(lt 1arry '(t

VHDL
Following is the VHDL code for an (nsigned 8-bit adder with carry in and carry o(t.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arit .all; use ieee.std_logic_unsigned.all; entity adder is port(5,6 : in std_logic_vector(7 downto 0); :0 : in std_logic; 178 : out std_logic_vector(7 downto 0); :4 : out std_logic);

end adder; arc itecture arc i o! adder is signal t*p: std_logic_vector(; downto 0); begin t*p "# conv_std_logic_vector( (conv_integer(5) 9 conv_integer(6) 9 conv_integer(:0)),<); 178 "# t*p(7 downto 0); :4 "# t*p(;); end arc i;

!i#ple !igned 0-.it dder

0he following table shows )in descri)tions for a si/)le signed 8-bit adder.
IO pins Description

:!8#$%2 @!8#$% :dd ')erands &,+!8#$% :dd Aes(lt

VHDL
Following is the VHDL code for a si/)le signed 8-bit adder.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity adder is port(5,6 : in std_logic_vector(7 downto 0); 178 : out std_logic_vector(7 downto 0)); end adder; arc itecture arc i o! adder is begin 178 "# 5 9 6; end arc i;

Unsigned 0-.it !&.tr"ctor

0he following table shows )in descri)tions for an (nsigned 8-bit s(btractor.
IO pins Description

:!8#$%2 @!8#$% &(b ')erands AE&!8#$% &(b Aes(lt

VHDL
Following is the VHDL code for an (nsigned 8-bit s(btractor.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity subtr is port(5,6 : in std_logic_vector(7 downto 0); =21 : out std_logic_vector(7 downto 0)); end subtr;

arc itecture arc i o! subtr is begin =21 "# 5 ( 6; end arc i;

Unsigned 0-.it dder/!&.tr"ctor

0he following table shows )in descri)tions for an (nsigned 8-bit adder;s(btractor.
IO pins Description

:!8#$%2 @!8#$% :dd;&(b ')erands 'PEA :dd;&(b &elect &,+!8#$% :dd;&(b Aes(lt

VHDL
Following is the VHDL code for an (nsigned 8-bit adder;s(btractor.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addsub is port(5,6 : in std_logic_vector(7 downto 0); 4>2=: in std_logic; =21 : out std_logic_vector(7 downto 0)); end addsub; arc itecture arc i o! addsub is begin =21 "# 5 9 6 w en 4>2=#%0% else 5 ( 6; end arc i; end*odule

Co#p"r"tors (2- /2-3- 32- 4- 42)

0his section contains a VHDL and Verilog descri)tion for an (nsigned 8-bit greater or e9(al co/)arator.

Unsigned 0-.it 5re"ter or E6&"l Co#p"r"tor

0he following table shows )in descri)tions for a co/)arator.
IO pins Description

:!8#$%2 @!8#$% :dd;&(b ')erands 1+P 1o/)arison Aes(lt

VHDL
Following is the VHDL code for an (nsigned 8-bit greater or e9(al co/)arator.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity co*par is

port(5,6 : in std_logic_vector(7 downto 0); :8> : out std_logic); end co*par; arc itecture arc i o! co*par is begin :8> "# %1% w en 5 -# 6 else %0%; end arc i;

M&ltipliers
Dhen i/)le/enting a /(lti)lier2 the siEe of the res(lting signal is e9(al to the s(/ of " o)erand lengths. .f yo( /(lti)ly : <8-bit signal? by @ <*-bit signal?2 then the siEe of the res(lt /(st be declared as a 1"-bit signal.

Unsigned 0*4-.it M&ltiplier

0his section contains VHDL and Verilog descri)tions of an (nsigned 83*-bit /(lti)lier. 0he following table shows )in descri)tions for an (nsigned 83*-bit /(lti)lier.
IO pins Description

:!8#$%2 @!3#$% +,L0 ')erands AE&!8#$% +,L0 Aes(lt

VHDL
Following is the VHDL code for an (nsigned 83*-bit /(lti)lier.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity *ult is port(5 : in std_logic_vector(7 downto 0); 6 : in std_logic_vector(& downto 0); =21 : out std_logic_vector(11 downto 0)); end *ult; arc itecture arc i o! *ult is begin =21 "# 5 ? 6; end arc i;

Di7iders
Di4isions are only s())orted2 when the di4isor is a constant and is a )ower of ". .n that case2 the o)erator is i/)le/ented as a shifter otherwise2 an error /essage will be iss(ed by -&0.

Di7ision %y Const"nt +
0his section contains VHDL and Verilog descri)tions of a Di4ision @y 1onstant " di4ider. 0he following table shows )in descri)tions for a Di4ision @y 1onstant " di4ider.

IO pins

Description

D.!8#$% D.V ')erands D'!8#$% D.V Aes(lt

VHDL
Following is the VHDL code for a Di4ision @y 1onstant " di4ider.
library ieee; use ieee.std_logic_1164.all; use ieee.nu*eric_std.all; entity divider is port(/0 : in unsigned(7 downto 0); /4 : out unsigned(7 downto 0)); end divider; arc itecture arc i o! divider is begin /4 "# /0 @ 2; end arc i;

8eso&rce !)"ring
0he goal of reso(rce sharing <also 7nown as folding? is to /ini/iEe the n(/ber of o)erators and the s(bse9(ent logic in the synthesiEed design. 0his o)ti/iEation is based on the )rinci)le that two si/ilar arith/etic reso(rces /ay be i/)le/ented as one single arith/etic o)erator if they are ne4er (sed at the sa/e ti/e. -&0 )erfor/s both reso(rce sharing and2 if re9(ired2 red(ces of the n(/ber of /(lti)le3ers that are created in the )rocess. -&0 s())orts reso(rce sharing for adders2 s(btractors2 adders;s(btractors and /(lti)liers.

8el"ted Constr"int
0he related constraint is reso&rce9s)"ring.

E*"#ple
For the following VHDL;Verilog e3a/)le2 -&0 will gi4e the following sol(tion#

0he following table shows )in descri)tions for the e3a/)le.

IO pins Description

:!8#$%2 @!8#$%2 @!8#$% D.V ')erands 'PEA ')eration &elector AE&!8#$% Data '(t)(t

VHDL
Following is the VHDL e3a/)le for reso(rce sharing.
library ieee; use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all; entity adds(b is port(5,6,: : in std_logic_vector(7 downto 0); 4>2= : in std_logic; =21 : out std_logic_vector(7 downto 0)); end addsub; arc itecture arc i o! addsub is begin =21 "# 5 9 6 w en 4>2=#%0% else 5 ( :; end arc i;

"dder
306=5=A ieee ; 712 ieee.std_logic_1164.all ; 712 ieee.std_logic_arit .all ; 2BC0CA adder 01 >4=C(in1: in2: c_out: su*: ) ; 2B/ adder ; 0B 0B 47C 47C std_logic_vector(1' /4DBC4 0) ; std_logic_vector(1' /4DBC4 0) ; std_logic ; std_logic_vector(1' /4DBC4 0)

5=:E0C2:C7=2 synt esiFable 4G adder 01 62H0B >=4:211(in1, in2) I5=05632 t*p_in1: signed(16 /4DBC4 0) ; I5=05632 t*p_in2: signed(16 /4DBC4 0) ; I5=05632 output: signed(16 /4DBC4 0) ; I5=05632 c: std_logic ; 62H0B t*p_in1 :# signed(%0% J in1) ; t*p_in2 :# signed(%0% J in2) ; output :# t*p_in1 9 t*p_in2 ; 0G (output(16) # %1%) CE2B c :# %1% ; 2312 c :# %0% ; 2B/ 0G ; su* "# std_logic_vector(output(1' /4DBC4 0)) ; c_out "# c ; 2B/ >=4:211 ; 2B/ synt esiFable ; ((

counter

306=5=A ieee ; 712 ieee.std_logic_1164.all ; 712 ieee.std_logic_arit .all ;

2BC0CA counter 01 >4=C(clK: input: output: ld: inc: clr: ) ; 2B/ counter ;

0B 0B 47C 0B 0B 0B

std_logic ; std_logic_vector(11 /4DBC4 0) ; std_logic_vector(11 /4DBC4 0) ; std_logic ; std_logic ; std_logic

5=:E0C2:C7=2 be avioral 4G counter 01 62H0B generic_counter: >=4:211(clK, input, ld, inc, clr) I5=05632 t*pvar: unsigned(11 /4DBC4 0) ; 62H0B 0G (rising_edge(clK)) CE2B 0G (clr # %1%) CE2B t*pvar :# (4CE2=1 #- %0%) ; 2310G (ld # %1%) CE2B t*pvar :# unsigned(input) ; 2310G (inc # %1%) CE2B t*pvar :# t*pvar 9 $000000000001$ ; 2B/ 0G ; output "# std_logic_vector(t*pvar) ; 2B/ 0G ; 2B/ >=4:211 ; 2B/ be avioral ;

(( (( /esign a 2(bit count(down counter (( 306=5=A ieee ; 712 ieee.std_logic_1164.all ; 712 ieee.std_logic_arit .all ; 712 ieee.std_logic_signed.all ; 712 ieee.std_logic_unsigned.all ; 2BC0CA down_counter 01 >4=C(10HB53 +: 0B std_logic ; 10HB53 count : 47C std_logic_vector(1 /4DBC4 0) ; 10HB53 reset: 0B std_logic ; 10HB53 clK: 0B std_logic ) ; 2B/ down_counter ; 5=:E0C2:C7=2 arc 1 4G down_counter 01 62H0B >=4:211(clK, +, reset) I5=05632 t*p_cnt: unsigned(1 /4DBC4 0) ; 62H0B 0G (reset # %1%) CE2B t*p_cnt :# $00$ ; 2310G rising_edge(clK) CE2B

0G (+ # %1%) CE2B t*p_cnt :# t*p_cnt ( $01$ ; 2B/ 0G ; 2B/ 0G ; count "# std_logic_vector(t*p_cnt) ; 2B/ >=4:211 ; 2B/ arc 1 ;

(( (( ; to & priority encoder (( 306=5=A 712 ieee ; ieee.std_logic_1164.all ; 0B 47C std_logic_vector(7 /4DBC4 0) ; std_logic_vector(2 /4DBC4 0)

2BC0CA enc;to& 01 >4=C(10HB53 input: 10HB53 output: ) ; 2B/ enc;to& ; (( (( Eere is a (( 0 don%t t (( we want a (( 5=:E0C2:C7=2 62H0B output "#

case w ere we really need t e DE2B ( 2312 inK t e D0CE select will worK because priority encoder arc 1 4G enc;to& 01 $111$ $110$ $101$ $100$ $011$ $010$ $001$ $000$ DE2B DE2B DE2B DE2B DE2B DE2B DE2B ; (input(7) (input(6) (input(') (input(4) (input(&) (input(2) (input(1) # # # # # # # %1%) %1%) %1%) %1%) %1%) %1%) %1%) 2312 2312 2312 2312 2312 2312 2312

2B/ arc 1 ;

(( !a.v d (( (( 5 1(bit !ull(adder (( (( Heorge 3. 2ngel, 1072 (( 306=5=A ieee ; 712 ieee.std_logic_1164.all ; 2BC0CA !a 01 >4=C( a, b : in std_logic ; cin : in std_logic ; cout : out std_logic ;

) ; 2B/ !a ;

su*

: out std_logic

5=:E0C2:C7=2 arc 1 4G !a 01 62H0B su* "# (a )4= b) )4= cin ; cout "# (a 5B/ b) 4= ((a 4= b) 5B/ cin) ; 2B/ arc 1 ;

((

REGISTER

306=5=A ieee ; 712 ieee.std_logic_1164.all ; 2BC0CA reg 01 >4=C(clK: input: output: ld: ) ; 2B/ reg ; 0B 0B 47C 0B std_logic ; std_logic_vector(1' /4DBC4 0) ; std_logic_vector(1' /4DBC4 0) ; std_logic

5=:E0C2:C7=2 be avioral 4G reg 01 62H0B generic_register: >=4:211(clK, input, ld) 62H0B 0G (rising_edge(clK)) CE2B 0G (ld # %1%) CE2B output "# input ; 2B/ 0G ; 2B/ 0G ; 2B/ >=4:211 ; 2B/ be avioral ;

((((((((((((((((((((((((((((((((((((((((((((( (( / Glip(Glop (21/ booK : apter 2.&.1) (( by DeiLun . ang, 04@2001 (( (( Glip(!lop is t e basic co*ponent in (( seMuential logic design (( we assign input signal to t e output (( at t e clocK rising edge ((((((((((((((((((((((((((((((((((((((((((((( library ieee ;

use ieee.std_logic_1164.all; use worK.all; ((((((((((((((((((((((((((((((((((((((((((((( entity d!! is port( data_in: clocK: data_out: ); end d!!; in std_logic; in std_logic; out std_logic

(((((((((((((((((((((((((((((((((((((((((((((( arc itecture be v o! d!! is begin process(data_in, clocK) begin (( clocK rising edge i! (clocK#%1% and clocK%event) t en data_out "# data_in; end i!; end process; end be v; (((((((((((((((((((((((((((((((((((((((((((((( (((((((((((((((((((((((((((((((((((((((((((((( (( NO Glip(Glop wit reset (( (21/ booK : apter 2.&.1) (( by DeiLun . ang, 04@2001 (( (( t e description o! NO Glip(Glop is based (( on !unctional trut table (( concurrent state*ent and signal assign*ent (( are using in t is e+a*ple (((((((((((((((((((((((((((((((((((((((((((((( library ieee; use ieee.std_logic_1164.all; (((((((((((((((((((((((((((((((((((((((((((((( entity NO_GG is port ( clocK: in std_logic; N, O: in std_logic; reset: in std_logic; P, Pbar: out std_logic ); end NO_GG;

((((((((((((((((((((((((((((((((((((((((((((((( arc itecture be v o! NO_GG is (( de!ine t e use!ul signals ere

signal state: std_logic; signal input: std_logic_vector(1 downto 0); begin (( co*bine inputs into vector input "# N J O; p: process(clocK, reset) is begin i! (reset#%1%) t en state "# %0%; elsi! (rising_edge(clocK)) t en (( co*pare to t e trut table case (input) is w en $11$ #state "# not state; w en $10$ #state "# %1%; w en $01$ #state "# %0%; w en ot ers #null; end case; end i!; end process; (( concurrent state*ents P "# state; Pbar "# not state; end be v; ((((((((((((((((((((((((((((((((((((((((((((((((( ((((((((((((((((((((((((((((((((((((((((((((((((((( (( n(bit =egister (21/ booK !igure 2.6) (( by DeiLun . ang, 04@2001 (( (( O2A D4=/: concurrent, generic and range ((((((((((((((((((((((((((((((((((((((((((((((((((( library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; (((((((((((((((((((((((((((((((((((((((((((((((((((

entity reg is generic(n: natural :#2); port( 0: in std_logic_vector(n(1 downto 0); clocK: in std_logic; load: in std_logic; clear: in std_logic; P: out std_logic_vector(n(1 downto 0) ); end reg; (((((((((((((((((((((((((((((((((((((((((((((((((((( arc itecture be v o! reg is signal P_t*p: std_logic_vector(n(1 downto 0); begin process(0, clocK, load, clear) begin i! clear # %0% t en (( use %range in signal assig*ent P_t*p "# (P_t*p%range #- %0%); elsi! (clocK#%1% and clocK%event) t en i! load # %1% t en P_t*p "# 0; end i!; end i!; end process; (( concurrent state*ent P "# P_t*p; end be v; (((((((((((((((((((((((((((((((((((((((((((((((((((

((((((((((((((((((((((((((((((((((((((((((((((((((( (( &(bit 1 i!t(=egister@1 i!ter (( (21/ booK !igure 2.6) (( by DeiLun . ang, 04@2001 (( (( reset is ignored according to t e !igure ((((((((((((((((((((((((((((((((((((((((((((((((((( library ieee ; use ieee.std_logic_1164.all; ((((((((((((((((((((((((((((((((((((((((((((((((((( entity s i!t_reg is port( 0: in std_logic;

); end s i!t_reg;

clocK: s i!t: P:

in std_logic; in std_logic; out std_logic

((((((((((((((((((((((((((((((((((((((((((((((((((( arc itecture be v o! s i!t_reg is (( initialiFe t e declared signal signal 1: std_logic_vector(2 downto 0):#$111$; begin process(0, clocK, s i!t, 1) begin (( everyt ing i! clocK%event i! s i!t # 1 "# 0 J end i!; end i!; end process; (( concurrent assign*ent P "# 1(0); end be v; (((((((((((((((((((((((((((((((((((((((((((((((((((( appens upon t e clocK c anging and clocK#%1% t en %1% t en 1(2 downto 1);

(((((((((((((((((((((((((((((((((((((((((((((((((((( (( IE/3 code !or n(bit counter (21/ !igure 2.6) (( by DeiLun . ang, 04@2001 (( (( t is is t e be avior description o! n(bit counter (( anot er way can be used is G18 *odel. (((((((((((((((((((((((((((((((((((((((((((((((((((( library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; (((((((((((((((((((((((((((((((((((((((((((((((((((( entity counter is generic(n: natural :#2); port( clocK: in std_logic; clear: in std_logic; count: in std_logic; P: out std_logic_vector(n(1 downto 0)

); end counter; (((((((((((((((((((((((((((((((((((((((((((((((((((( arc itecture be v o! counter is signal >re_P: std_logic_vector(n(1 downto 0); begin (( be avior describe t e counter process(clocK, count, clear) begin i! clear # %1% t en >re_P "# >re_P ( >re_P; elsi! (clocK#%1% and clocK%event) t en i! count # %1% t en >re_P "# >re_P 9 1; end i!; end i!; end process; (( concurrent assign*ent state*ent P "# >re_P; end be v; (((((((((((((((((((((((((((((((((((((((((((((((((((((

VHDL Code for Shift registers

0-.it !)i't-Le't 8egister 1it) Positi7e-Edge Cloc:- !eri"l In- "nd !eri"l O&t
Fote For this e3a/)le2 -&0 will infer &AL1G. 0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4eedge cloc72 serial in2 and serial o(t.
IO Pins Description

1 &. &'

Positi4e-Edge 1loc7 &erial .n &erial '(t)(t

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all; entity s i!t is port(:, 10 : in std_logic; 14 : out std_logic); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:) begin i! (:%event and :#%1%) t en !or i in 0 to 6 loop t*p(i91) "# t*p(i); end loop; t*p(0) "# 10; end i!; end process; 14 "# t*p(7); end arc i;

0-.it !)i't-Le't 8egister 1it) (eg"ti7e-Edge Cloc:- Cloc: En".le!eri"l In- "nd !eri"l O&t
Fote For this e3a/)le2 -&0 will infer &AL1GEB1. 0he following table shows )in definitions for an 8-bit shift-left register with a negati4eedge cloc72 cloc7 enable2 serial in2 and serial o(t.
IO Pins Description

1 &. 1E &'

Fegati4e-Edge 1loc7 &erial .n 1loc7 Enable <acti4e High? &erial '(t)(t

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a negati4e-edge cloc72 cloc7 enable2 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all; entity shift is port(:, 10, :2 : in std_logic; 14 : out std_logic); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:) begin i! (:%event and :#%0%) t en i! (:2#%1%) t en !or i in 0 to 6 loop t*p(i91) "# t*p(i); end loop; t*p(0) "# 10; end i!; end i!; end process; 14 "# t*p(7); end arc i;

0-.it !)i't-Le't 8egister 1it) Positi7e-Edge Cloc:- sync)rono&s Cle"r- !eri"l In- "nd !eri"l O&t
Fote @eca(se this e3a/)le incl(des an asynchrono(s clear2 -&0 will not infer &AL1G.

0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4eedge cloc72 asynchrono(s clear2 serial in2 and serial o(t.
IO Pins Description

1 &. 1LA &'

Positi4e-Edge 1loc7 &erial .n :synchrono(s 1lear <acti4e High? &erial '(t)(t

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72 asynchrono(s clear2 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all; entity s i!t is port(:, 10, :3= : in std_logic; 14 : out std_logic); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:, :3=) begin i! (:3=#%1%) t en t*p "# (ot ers #- %0%); elsi! (:%event and :#%1%) t en t*p "# t*p(6 downto 0) J 10; end i!; end process; 14 "# t*p(7); end arc i;

0-.it !)i't-Le't 8egister 1it) Positi7e-Edge Cloc:- !ync)rono&s !et!eri"l In- "nd !eri"l O&t
Fote @eca(se this e3a/)le incl(des an asynchrono(s clear -&0 will not infer &AL1G. 0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4eedge cloc72 synchrono(s set2 serial in2 and serial o(t.
IO Pins Description

1 &. & &'

Positi4e-Edge 1loc7 &erial .n synchrono(s &et <acti4e High? &erial '(t)(t

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72 synchrono(s set2 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all;

entity s i!t is port(:, 10, 1 : in std_logic; 14 : out std_logic); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:, 1) begin i! (:%event and :#%1%) t en i! (1#%1%) t en t*p "# (ot ers #- %1%); else t*p "# t*p(6 downto 0) J 10; end i!; end i!; end process; 14 "# t*p(7); end arc i;

0-.it !)i't-Le't 8egister 1it) Positi7e-Edge Cloc:- !eri"l In- "nd P"r"llel O&t
Fote For this e3a/)le -&0 will infer &AL1G.

0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4eedge cloc72 serial in2 and serial o(t.
IO Pins Description

1 Positi4e-Edge 1loc7 &. &erial .n P'!8#$% Parallel '(t)(t

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all; entity s i!t is port(:, 10 : in std_logic; >4 : out std_logic_vector(7 downto 0)); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:) begin i! (:%event and :#%1%) t en t*p "# t*p(6 downto 0)J 10; end i!;

end process; >4 "# t*p; end arc i;

0-.it !)i't-Le't 8egister 1it) Positi7e-Edge Cloc:- sync)rono&s P"r"llel Lo"d- !eri"l In- "nd !eri"l O&t
Fote For this e3a/)le -&0 will infer &AL1G.

0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4eedge cloc72 asynchrono(s )arallel load2 serial in2 and serial o(t.
IO Pins Description

1 &. :L':D D!8#$% &'

Positi4e-Edge 1loc7 &erial .n :synchrono(s Parallel Load <acti4e High? Data .n)(t &erial '(t)(t

VHDL Code
Following is VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72 asynchrono(s )arallel load2 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all; entity s i!t is port(:, 10, 5345/ : in std_logic; / : in std_logic_vector(7 downto 0); 14 : out std_logic); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:, 5345/, /) begin i! (5345/#%1%) t en t*p "# /; elsi! (:%event and :#%1%) t en t*p "# t*p(6 downto 0) J 10; end i!; end process; 14 "# t*p(7); end arc i;

0-.it !)i't-Le't 8egister 1it) Positi7e-Edge Cloc:- !ync)rono&s P"r"llel Lo"d- !eri"l In- "nd !eri"l O&t
Fote For this e3a/)le -&0 will not infer &AL1G.

0he following table shows )in definitions for an 8-bit shift-left register with a )ositi4eedge cloc72 synchrono(s )arallel load2 serial in2 and serial o(t.
IO Pins Description

1 &. &L':D D!8#$% &'

Positi4e-Edge 1loc7 &erial .n &ynchrono(s Parallel Load <acti4e High? Data .n)(t &erial '(t)(t

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a )ositi4e-edge cloc72 synchrono(s )arallel load2 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all; entity s i!t is port(:, 10, 1345/ : in std_logic; / : in std_logic_vector(7 downto 0); 14 : out std_logic); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:) begin i! (:%event and :#%1%) t en i! (1345/#%1%) t en t*p "# /; else t*p "# t*p(6 downto 0) J 10; end i!; end i!; end process; 14 "# t*p(7); end arc i;

0-.it !)i't-Le't/!)i't-8ig)t 8egister 1it) Positi7e-Edge Cloc:- !eri"l In- "nd P"r"llel O&t
Fote For this e3a/)le -&0 will not infer &AL1G.

0he following table shows )in definitions for an 8-bit shift-left;shift-right register with a )ositi4e-edge cloc72 serial in2 and serial o(t.
IO Pins Description

1 &. LEF0BA.HH0 P'!8#$%

Positi4e-Edge 1loc7 &erial .n Left;right shift /ode selector Parallel '(t)(t

VHDL Code

Following is the VHDL code for an 8-bit shift-left;shift-right register with a )ositi4e-edge cloc72 serial in2 and serial o(t.
library ieee; use ieee.std_logic_1164.all; entity s i!t is port(:, 10, 32GC_=0HEC : in std_logic; >4 : out std_logic_vector(7 downto 0)); end s i!t; arc itecture arc i o! s i!t is signal t*p: std_logic_vector(7 downto 0); begin process (:) begin i! (:%event and :#%1%) t en i! (32GC_=0HEC#%0%) t en t*p "# t*p(6 downto 0) J 10; else t*p "# 10 J t*p(7 downto 1); end i!; end i!; end process; >4 "# t*p; end arc i;

Co&nters
4-.it Unsigned Up Co&nter 1it) sync)rono&s Cle"r

0he following table shows )in definitions for a *-bit (nsigned () co(nter with asynchrono(s clear.
IO Pins Description

1 Positi4e-Edge 1loc7 1LA :synchrono(s 1lear <acti4e High? I!3#$% Data '(t)(t

VHDL Code
Following is VHDL code for a *-bit (nsigned () co(nter with asynchrono(s clear.
library ieee use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(:, :3= : in std_logic; P : out std_logic_vector(& downto 0)); end counter; arc itecture arc i o! counter is signal t*p: std_logic_vector(& downto 0); begin process (:, :3=) begin i! (:3=#%1%) t en t*p "# $0000$; elsi! (:%event and :#%1%) t en t*p "# t*p 9 1; end i!; end process; P "# t*p; end arc i;

4-.it Unsigned Do1n Co&nter 1it) !ync)rono&s !et

0he following table shows )in definitions for a *-bit (nsigned down co(nter with synchrono(s set.
IO Pins Description

1 Positi4e-Edge 1loc7 & &ynchrono(s &et <acti4e High? I!3#$% Data '(t)(t

VHDL Code
Following is the VHDL code for a *-bit (nsigned down co(nter with synchrono(s set.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is

port(:, 1 : in std_logic; P : out std_logic_vector(& downto 0)); end counter; arc itecture arc i o! counter is signal t*p: std_logic_vector(& downto 0); begin process (:) begin i! (:%event and :#%1%) t en i! (1#%1%) t en t*p "# $1111$; else t*p "# t*p ( 1; end i!; end i!; end process; P "# t*p; end arc i;

4-.it Unsigned Up Co&nter 1it) sync)rono&s Lo"d 'ro# Pri#"ry Inp&t

0he following table shows )in definitions for a *-bit (nsigned () co(nter with asynchrono(s load fro/ )ri/ary in)(t.
IO Pins Description

1 :L':D D!3#$% I!3#$%

Positi4e-Edge 1loc7 :synchrono(s Load <acti4e High? Data .n)(t Data '(t)(t

VHDL Code
Following is the VHDL code for a *-bit (nsigned () co(nter with asynchrono(s load fro/ )ri/ary in)(t.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(:, 5345/ : in std_logic; / : in std_logic_vector(& downto 0); P : out std_logic_vector(& downto 0)); end counter; arc itecture arc i o! counter is signal t*p: std_logic_vector(& downto 0); begin process (:, 5345/, /) begin i! (5345/#%1%) t en t*p "# /;

elsi! (:%event and :#%1%) t en t*p "# t*p 9 1; end i!; end process; P "# t*p; end arc i;

4-.it Unsigned Up Co&nter 1it) !ync)rono&s Lo"d 1it) " Const"nt

0he following table shows )in definitions for a *-bit (nsigned () co(nter with synchrono(s load with a constant.
IO Pins Description

1 Positi4e-Edge 1loc7 &L':D &ynchrono(s Load <acti4e High? I!3#$% Data '(t)(t

VHDL Code
Following is the VHDL code for a *-bit (nsigned () co(nter with synchrono(s load with a constant.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(:, 1345/ : in std_logic; P : out std_logic_vector(& downto 0)); end counter; arc itecture arc i o! counter is signal t*p: std_logic_vector(& downto 0); begin process (:) begin i! (:%event and :#%1%) t en i! (1345/#%1%) t en t*p "# $1010$; else t*p "# t*p 9 1; end i!; end i!; end process; P "# t*p; end arc i;

4-.it Unsigned Up Co&nter 1it) sync)rono&s Cle"r "nd Cloc: En".le

0he following table shows )in definitions for a *-bit (nsigned () co(nter with asynchrono(s clear and cloc7 enable.
IO Pins Description

1 1LA 1E I!3#$%

Positi4e-Edge 1loc7 :synchrono(s 1lear <acti4e High? 1loc7 Enable Data '(t)(t

VHDL Code
Following is the VHDL code for a *-bit (nsigned () co(nter with asynchrono(s clear and cloc7 enable.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(:, :3=, :2 : in std_logic; P : out std_logic_vector(& downto 0)); end counter; arc itecture arc i o! counter is signal t*p: std_logic_vector(& downto 0); begin process (:, :3=) begin i! (:3=#%1%) t en t*p "# $0000$; elsi! (:%event and :#%1%) t en i! (:2#%1%) t en t*p "# t*p 9 1; end i!; end i!; end process; P "# t*p; end arc i;

4-.it Unsigned Up/Do1n co&nter 1it) sync)rono&s Cle"r

0he following table shows )in definitions for a *-bit (nsigned ();down co(nter with asynchrono(s clear.
IO Pins Description

1 Positi4e-Edge 1loc7 1LA :synchrono(s 1lear <acti4e High? ,PBD'DF ();down co(nt /ode selector

I!3#$%

Data '(t)(t

VHDL Code
Following is the VHDL code for a *-bit (nsigned ();down co(nter with asynchrono(s clear.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(:, :3=, 7>_/4DB : in std_logic; P : out std_logic_vector(& downto 0)); end counter; arc itecture arc i o! counter is signal t*p: std_logic_vector(& downto 0); begin process (:, :3=) begin i! (:3=#%1%) t en t*p "# $0000$; elsi! (:%event and :#%1%) t en i! (7>_/4DB#%1%) t en t*p "# t*p 9 1; else t*p "# t*p ( 1; end i!; end i!; end process; P "# t*p; end arc i;

4-.it !igned Up Co&nter 1it) sync)rono&s 8eset

0he following table shows )in definitions for a *-bit signed () co(nter with asynchrono(s reset.
IO Pins Description

1 Positi4e-Edge 1loc7 1LA :synchrono(s 1lear <acti4e High? I!3#$% Data '(t)(t

VHDL Code
Following is the VHDL code for a *-bit signed () co(nter with asynchrono(s reset.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity counter is port(:, :3= : in std_logic; P : out std_logic_vector(& downto 0));

end counter; arc itecture arc i o! counter is signal t*p: std_logic_vector(& downto 0); begin process (:, :3=) begin i! (:3=#%1%) t en t*p "# $0000$; elsi! (:%event and :#%1%) t en t*p "# t*p 9 1; end i!; end process; P "# t*p; end arc i;

8egisters
;lip-'lop 1it) Positi7e-Edge Cloc:

0he following fig(re shows a fli)-flo) with )ositi4e-edge cloc7.

0he following table shows )in definitions for a fli)-flo) with )ositi4e edge cloc7.
IO Pins Description

D 1 I

Data .n)(t Positi4e Edge 1loc7 Data '(t)(t

VHDL Code
Following is the e9(i4alent VHDL code sa/)le for the fli)-flo) with a )ositi4e-edge cloc7.
library ieee; use ieee.std_logic_1164.all; entity !lop is port(:, / : in std_logic; P : out std_logic); end !lop; arc itecture arc i o! !lop is begin process (:) begin i! (:%event and :#%1%) t en P "# /; end i!; end process; end arc i; Bote D en using IE/3, !or a positive(edge clocK instead o! using i! (:%event and :#%1%) t en

yo( can also (se

i! (rising_edge(:)) t en

and for a negati4e-edge cloc7 yo( can (se

i! (!alling_edge(:)) t en

;lip-'lop 1it) (eg"ti7e-Edge Cloc: "nd sync)rono&s Cle"r

0he following fig(re shows a fli)-flo) with negati4e-edge cloc7 and asynchrono(s clear.

0he following table shows )in definitions for a fli)-flo) with negati4e edge cloc7 and asynchrono(s clear.

IO Pins Description

D 1 1LA I

Data .n)(t Fegati4e-Edge 1loc7 :synchrono(s 1lear <acti4e High? Data '(t)(t

VHDL Code
Following is the e9(i4alent VHDL code for a fli)-flo) with a negati4e-edge cloc7 and asynchrono(s clear.
library ieee; use ieee.std_logic_1164.all; entity !lop is port(:, /, :3= : in std_logic; P : out std_logic); end !lop; arc itecture arc i o! !lop is begin process (:, :3=) begin i! (:3= # %1%)t en P "# %0%; elsi! (:%event and :#%0%)t en P "# /; end i!; end process; end arc i;

;lip-'lop 1it) Positi7e-Edge Cloc: "nd !ync)rono&s !et

0he following fig(re shows a fli)-flo) with )ositi4e-edge cloc7 and synchrono(s set.

0he following table shows )in definitions for a fli)-flo) with )ositi4e edge cloc7 and synchrono(s set.
IO Pins Description

D 1 & I

Data .n)(t Positi4e-Edge 1loc7 &ynchrono(s &et <acti4e High? Data '(t)(t

VHDL Code
Following is the e9(i4alent VHDL code for the fli)-flo) with a )ositi4e-edge cloc7 and synchrono(s set.
library ieee;

use ieee.std_logic_1164.all; entity !lop is port(:, /, 1 : in std_logic; P : out std_logic); end !lop; arc itecture arc i o! !lop is begin process (:) begin i! (:%event and :#%1%) t en i! (1#%1%) t en P "# %1%; else P "# /; end i!; end i!; end process; end arc i;

;lip-'lop 1it) Positi7e-Edge Cloc: "nd Cloc: En".le

0he following fig(re shows a fli)-flo) with )ositi4e-edge cloc7 and cloc7 enable.

0he following table shows )in definitions for a fli)-flo) with )ositi4e edge cloc7 and cloc7 enable.
IO Pins Description

D 1 1E I

Data .n)(t Positi4e-Edge 1loc7 1loc7 Enable <acti4e High? Data '(t)(t

VHDL Code
Following is the e9(i4alent VHDL code for the fli)-flo) with a )ositi4e-edge cloc7 and cloc7 Enable.
library ieee; use ieee.std_logic_1164.all; entity !lop is port(:, /, :2 : in std_logic; P : out std_logic); end !lop; arc itecture arc i o! !lop is begin process (:) begin i! (:%event and :#%1%) t en i! (:2#%1%) t en

P "# /; end i!; end i!; end process; end arc i;

4-.it 8egister 1it) Positi7e-Edge Cloc:- sync)rono&s !et "nd Cloc: En".le
0he following fig(re shows a *-bit register with )ositi4e-edge cloc72 asynchrono(s set and cloc7 enable.

0he following table shows )in definitions for a *-bit register with )ositi4e-edge cloc72 asynchrono(s set and cloc7 enable.
IO Pins Description

D!3#$% 1 PAE 1E I!3#$%

Data .n)(t Positi4e-Edge 1loc7 :synchrono(s &et <acti4e High? 1loc7 Enable <acti4e High? Data '(t)(t

VHDL Code
Following is the e9(i4alent VHDL code for a *-bit register with a )ositi4e-edge cloc72 asynchrono(s set and cloc7 enable.
library ieee; use ieee.std_logic_1164.all; entity !lop is port(:, :2, >=2 : in std_logic; / : in std_logic_vector (& downto 0); P : out std_logic_vector (& downto 0)); end !lop; arc itecture arc i o! !lop is begin process (:, >=2) begin i! (>=2#%1%) t en P "# $1111$; elsi! (:%event and :#%1%)t en i! (:2#%1%) t en P "# /; end i!; end i!; end process; end arc i;

L"tc) 1it) Positi7e 5"te

0he following fig(re shows a latch with )ositi4e gate.

0he following table shows )in definitions for a latch with )ositi4e gate.
IO Pins Description

D H I

Data .n)(t Positi4e Hate Data '(t)(t

VHDL Code
Following is the e9(i4alent VHDL code for a latch with a )ositi4e gate.
library ieee; use ieee.std_logic_1164.all; entity latc is port(H, / : in std_logic; P : out std_logic); end latc ; arc itecture arc i o! latc is begin process (H, /) begin i! (H#%1%) t en P "# /; end i!; end process; end arc i;

,-%it 1-o'-< Priority Encoder

Fote For this e3a/)le -&0 /ay infer a )riority encoder. Jo( /(st (se the priority9e*tr"ct constraint with a 4al(e 'orce to force its inference.

8el"ted Constr"int
: related constraint is priority9e*tr"ct.

VHDL
Following is the VHDL code for a 3-bit 1-of-9 Priority Encoder.
library ieee; use ieee.std_logic_1164.all; entity priority is port ( sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0)); end priority; arc itecture arc i o! priority is begin code "# $000$ w en sel(0) # %1% else $001$ w en sel(1) # %1% else $010$ w en sel(2) # %1% else $011$ w en sel(&) # %1% else $100$ w en sel(4) # %1% else $101$ w en sel(') # %1% else $110$ w en sel(6) # %1% else $111$ w en sel(7) # %1% else $((($; end arc i;

Unsigned 0-.it 5re"ter or E6&"l Co#p"r"tor

0he following table shows )in descri)tions for a co/)arator.
IO pins Description

:!8#$%2 @!8#$% :dd;&(b ')erands 1+P 1o/)arison Aes(lt

VHDL
Following is the VHDL code for an (nsigned 8-bit greater or e9(al co/)arator.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity co*par is port(5,6 : in std_logic_vector(7 downto 0); :8> : out std_logic);

end co*par; arc itecture arc i o! co*par is begin :8> "# %1% w en 5 -# 6 else %0%; end arc i;