ESD Design PDF

ELE863/EE8501 VLSI Systems
Electrostatic Discharge Protection
GATE
BOND PAD
SOURCE
Fei Yuan, Ph.D, P.Eng. Department of Electrical & Computer Engineering Ryerson University Copyright c 2006
Copyright (c) F. Yuan 2006
(1)
OUTLINE
Introduction to ESD Principle Sources of ESD in ICs ESD Models ESD Protection Mechanisms ESD Protection Devices ESD Protection Circuits Layout of ESD Protection Circuits
(2)
Introduction to ESD
What is ESD ?
ESD - Electro-Static Discharge. ESD is a transient discharge of static charge that arises from either human handling or a machine contact. Although ESD is the result of a static potential in a charged object, the energy dissipated and damage made are mainly due to the current in ICs during discharge. Most ESD damage is thermally initiated in the form of device / interconnect burn-out or oxide break-down. The basic phenomenon is for sucient heat to be generated in a localized volume signicantly faster than it can be removed, leading to a temperature in excess of the materials safe operating limits. pn-junction may melt. Gate oxide may have void formation. Metal interconnects & Vias may melt or vaporization, leading to shorts or opens. Gate-oxide breakdown is another form of ESD damage.
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Introduction to ESD (contd)

Why is ESD Critical ?
ESD accounts for more than 10% total failure of integrated circuits. The aggressive decrease in physical dimensions and increase in doping in modern CMOS technology result in a signicant decrease in gate-oxide thickness and pn-junction width Require less energy and lower voltages to destroy MOS devices.
0.8 0.7
Junction depth [m]
0.6 0.5 0.4 0.3 0.2 0.1 0
0.5
1.5 Lmin [m]
2.5
Figure 1: Scaling of gate oxide thickness of MOS transistors.
(4)
Introduction to ESD (contd)

0.8
0.7
0.6
Junction depth [m]
0.5
0.4
0.3
0.2
0.1 0
0.5
1 L
min
1.5 [m]
2.5
Figure 2: Scaling of junction depth of MOS transistors.
20 V
t1
Student Version of MATLAB
Vox
15
Vt1, Vox [V]

10 5 20
40 60 Gate oxide thickness, t
ox
80 [A]
100
Figure 3: Scaling of the breakdown voltage of gate oxide and the avalanche breakdown voltage.
The level of ESD stress, however, does not scale down with the technology.
(5)
Principle Sources of ESD in ICs

Human Handling
A person walking on a synthetic oor can accumulated up to 20 kV. This voltage is discharged when the person touches an object that is suciently at ground. Charge exchange occurs between the person and the object in a very short time duration (10 ns - 100 ns). The charging current is approximately 1A - 10A, depending upon the time constant.
Test and Handling Systems

Equipment can accumulate static charge due to improper grounding. The charge is transmitted through ICs when it is picked up for placement in test sockets.
IC Itself is Charged During Transport / Contact With Charged Objects

ICs remain charged until they come into contact with a grounded surface (large metal plates /test sockets). Charge is discharged through the pins of ICs. Large currents in the internal interconnects can result in high voltage inside the devices which can cause damage to thin dielectrics and insulators.
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ESD Models
Human Body Model (HBM)
HBM models the ESD of a human body. Peak current 1.3A, rise time 10-30ns.
Human body model R=1.5kW
VC (0 - )
C=100pF
DUT
Figure 4: Equivalent circuit for the human body model of ESD. The switch closes upon an ESD event.
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ESD Models (contd)

Machine Model (MM)
MM models the ESD of manufacturing / testing equipment. Peak current 3.7A, rise time 15-30ns, bandwidth 12 MHz.
Machine model
VC (0 - ) C=200pF
DUT
Figure 5: Equivalent circuit for the machine model of ESD. The switch closes upon an ESD event.
ESD stress caused by charged machines is sever because of zero body resistance.
(8)
ESD Models (contd)

Charge Device Model (CDM)
CDM models the ESD of charged integrated circuits. Peak current 10A, rise time 1ns. Gate oxide breakdown is the signature failure of CDM stress, in contrast to the thermal failure signature of HBM and MM stress. CDM stress has the fastest transient and has the max. peak current. CDM stress is the most dicult ESD stress to protect against.
Charged device model R<10 W L<10 nH
DUT
Figure 6: Equivalent circuit of charged device model of ESD. The switch closes upon an ESD event.
(9)
ESD Protection Mechanisms (contd)

Current Limiting Characteristics of n-well Resistors Impact Ionization Avalanche Multiplication of pn-junctions First Breakdown (Avalanche Breakdown) of nMOS Second Breakdown (Thermal Breakdown) of nMOS
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Current Limiting Characteristics of n-well Resistors Conductivity
Majority charge carriers are free electrons. At low voltages, the velocity of free electrons (majority charge carriers) and that of holes (minority charge carriers) in a n-well resistor are linearly proportional to the eld intensity of the applied electric eld a linear resistor with a constant resistance.
vn = n E,
vp = p E,
(1)
where vn and vp are the velocity of free electrons and that of holes, respectively, n and p are the bulk mobility of free electrons and holes, respectively. The total charge crossing a cross-section of area A per second is given by
Q = (vnn + vp p)Aq, where n and p are the concentration of free electrons and holes, respectively, and q is the charge of an electron. The current density is obtained from Q = (nn + pp )qE = E, A
Copyright (c) F. Yuan 2006 (11)
(2)
J=
(3)
where
= (nn + pp )q is the conductivity.
(4)
Current Density
For n-type, the concentration of free electronics is approximately the doping of the donors, i.e. nnn , where nn is the doping of donors, we have vnn E . Consequently
J Jn = (nnn E )q = nn vn q = E
(5)
J is linearly proportional to E or equivalently the voltage across the semiconductors.
(12)

Velocity Saturation
At high voltages, the velocity of free electrons saturates due to the increasing collision with silicon lattices. As a result, the current through n-well resistors remains nearly constant regardless of voltage increase
Jsat = nn vn,satq vn,sat 107cm/s, nn = 1017/cm3 Jsat = 1.6105A/cm2.

vn Ohmic region v sat (10 7 cm/s) Saturation region
(6)
4 10 V/cm
Figure 7: Velocity saturation
n-well resistors exhibit a large resistance in the saturation region show above. n-well resistors in the saturation region can be used as current-limiting devices for ESD protection by limiting the amount of ESD discharging current.
(13)

Avalanche Multiplication in pn-junctions
When a pn-junction is reverse biased, the reverse current (leakage current) is solely due to (i) the movement of thermally generated charge carriers in the depletion region and (ii) the diusion of charge carriers in the neutral regions. When the reverse biasing voltage exceeds Vsat = 105V/cm, the carriers in the depletion region can impart enough energy in the collision with the silicon lattices to generate electron-hole pairs, which become free charge carriers. These charge carriers are then accelerated, collide with the silicon lattices, and create more free charge carriers Avalanche Multiplication.
Strike the covalent bond and destroy it Si Si Free electron Hole Si Si Si Si Holes Si
Covalent bonds
Si
Si
Si
Si
Si
Si
Si
Covalent bond destroyed
Si
Figure 8: Avalanche multiplication
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Avalanche Breakdown of nMOS Parasitic Lateral Bipolar Transistor in nMOS
PAD D
p+
G S
n+ n+
Isub
Rsub
VB
p-substrate
Figure 9: Parasitic lateral BJT in nMOS transistors.
nMOS is used as ESD protection devices. Gate is grounded to ensure nMOS is o under normal operation conditions. Drain-substrate/source-substrate pn-junctions are reverse biased. A parasitic lateral BJT as shown exists in the substrate. Under normal operation conditions, this parasitic BJT is o because both the pn-junctions of the nMOS transistor are reverse biased.

Avalanche Breakdown of Drain pn-junction of nMOS
When VD increases, the electric eld across the drain-substrate depletion region becomes high enough such that avalanche multiplication occurs at the drain-substrate junction electron-hole pairs are generated. The generated free electrons go to the drain due to its high potential, whereas the generated holes go to substrate due to its low potential It gives rise to Isub The base potential VB = Rsub Isub is increased subsequently. When VB is suciently high, the source-substrate pn-junction becomes forward biased electrons in the source (emitter) are emitted to the substrate (base) the parasitic lateral BJT is ON Avalanche Breakdown. The turn-on time of the parasitic BJT is determined by the base transit time (b = 250ps for 1 m channel length). Note the fundamental dierences between the parasitic BJT and normal BJTs. The base width of the parasitic BJT equals to the channel length of the nMOS transistor (in the range of m), whereas that of a normal BJT is very small (in the range of A).
(16)

Snapback
ID Thermal breakdown region
(Vt2 , I t2 ) Thermal breakdown Snapback region (ESD protection operation region) Avalanche breakdown Vsh (Vt1 , I t1 )
Slope=1/R sh
VD
Figure 10: Avalanche breakdown, snap back, and thermal breakdown of nMOS transistors.
When the BJT is ON, more electrons ows from the source to the drain ID and VD decreases sharply until the snapback holding voltage Vsp is reached. The snapback holding voltage is mainly across the drain-substrate pc-junction. The marginal increase of the drain voltage is due to voltage drop across the drain diusion, source diusion, and contact resistance. During snapback, the resistance has positive temperature coecients. This implies that if the current in any region increases, the temperature of the region will increase, thereby increasing the resistance, which encourages the current to ow elsewhere current is conducted uniformly by all gures of nMOS transistors.
(17)

Thermal Breakdown of nMOS
During snapback, the current of nMOS increases with the external voltage VDS . If VDS continues to increase, the device enters the thermal breakdown with the onset of the thermal breakdown, the resistance of the current path has negative temperature coecients, encourages current to concentrates in certain localized ngers of nMOS and eventually destroys the ngers. The concentration of ESD current into a few ngers indicates that no matter how many ngers are used, only a few will be activated in case of an ESD strike ESD current capability of the device does not scale with its size. To enhance the self-protection of ESD protection devices, the current must ow UNIFORMLY among all ngers of ESD protection devices.
(18)

Avalanche Breakdown versus Thermal Breakdown
If the avalanche breakdown voltage of ESD protection devices is LESS THAN their thermal breakdown voltage, then the avalanche breakdown occurs before the thermal breakdown ESD stress will be released by the avalanche breakdown and the devices will not enter the thermal breakdown. If the avalanche breakdown voltage of ESD protection devices is GREATER THAN their thermal breakdown voltage, the avalanche breakdown will occur at a voltage higher than the thermal breakdown voltage. After the avalanche breakdown occurs, VDS will still higher than the thermal breakdown voltage the devices will enter thermal breakdown and concentrate currents in a localized area due to negative temperature coecients device will be destroyed.
ID ID
Thermal breakdown Thermal breakdown Avalanche breakdown Avalanche breakdown
Vsp
Vt1 < Vt2
VD
Vsp
Vt2 < Vt1
VD
(A) Avalanche breakdown voltage is less than thermal breakdown voltage
(B) Avalanche breakdown voltage is greater then thermal breakdown voltage
Figure 11: Avalanche breakdown/thermal breakdown voltages
(19)
ESD Protection Devices

n-well Resistors Gated-Grounded nMOS Transistors (GGNMOS) Gated-Coupled nMOS Transistors (GCNMOS) Silicon Controlled Rectiers (SCR) Medium Voltage Triggered SCR
(20)
ESD Protection Devices (contd)

n-well Resistors
M1 SiO2 SiO2 N-well P-substrate P-substrate n+ M1 M1 Poly SiO2 M1
Poly-resistor
N-well resistor
Figure 12: Poly and n-well resistors
Poly-resistors should not be used as ESD protection devices due to their poor heat dissipation capability (Poly resistors are isolated from the substrate by the SiO2 layer). Note that the heat generated by ICs are taken away via two paths (i) PADs/traces/pins and (ii) substrate/ground plate. n-well resistors have good contact with the substrate. They are used as primary current-limiting devices. When a n-well resistor is used as the current-limiting device, together with a nMOS (primary ESD protection device), it is essential to make sure that the n-well resistor will not enter its thermal breakdown when the nMOS is in its avalanche breakdown.
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Diodes
n-well p+ Rn-well p-substrate (a) p+/n-well diodes PAD n+ R p-well p-substrate (b) n+/p-well diodes p+ p-well p+/n-well diode Internal circuits n+/p-well diode n+ pn-junction
Figure 13: Diodes in CMOS. (a) p+ /n-well diodes; (b) n+ /p-well diodes; (c) ESD protection using diodes.
Two main types of diodes : n+ /p-well diodes and p+ /n-well diodes. p+ /n-well diodes have a pn-junction between the n-well and p-substrate whereas there is no isolation between the diode and the p-substrate in n+ /p-well diodes. When forward-biased, diodes can sustain a large current with a small device dimension.
(22)

Gate-Grounded nMOS Transistors
PAD D DS
n+ RD R sub RS
G SS
p-substrate
Figure 14: Drain contact-gate spacing (DS) and source contact-gate spacing (SS) of ESD protection nMOS transistors.
During a ESD strike, the pn-junction at the drain undergoes an avalanche breakdown. Holes ow to the substrate, resulting in an increase in VB parasitic BJT will be turned on ESD current ows from the collector the (drain of nMOS) to the emitter (the source of nMOS that is connected to the ground) ESD stress at the drain of the nMOS transistor (PAD) is released. The dimensions of ESD nMOS should be large enough to handle large ESD currents multiple ngers structure is used to implement ESD nMOS. The main design parameters of nMOS are (i) channel length, (ii) drain contact-to-gate spacing, and (iii) device width. The source contact-to-gate spacing is not critical and is kept at its minimum design value.
i) The minimum channel length is good for ecient turn-on but the punch-through limit will be reduced. ii) Drain contact-to-gate spacing aects the resistance of ballast resistors. For silicided processes, the minimum drain contact-to-gate spacing is used. iii) Device width determines the maximum current that the device can conduct.
(24)

Gated-Grounded nMOS Transistors (contd)
D n-well ballasting resistor Contact/via n+
G S Metal-2 Metal-1
Figure 15: Lumped ballast resistors are added at the drains to ensure a uniform ESD current distribution among the ngers of ESD protection transistors.
During an avalanche breakdown, the current owing through the drain increases. However, the positive temperature coecient of the resistance of n+ -diusion (called Ballast Resistors) at the drain prevents current from concentrating in a localized region it forces the ESD current to ow into other ngers uniform current distribution is achieved. The eect of n+ -diusion resistance is virtually eliminated in silicided CMOS processes because in these processes n+ is silicided and the resistance of silicided n+ is small (a few ohms). To preserve the current-limiting ability of ballast resistors, explicit n-well ballast resistors at the drain are added. Note that the sheet resistance of n-well is much higher than that of n+ -diusion.
(25)

Gate-Coupled nMOS Transistors
In most applications, the gate of ESD nMOS is grounded to ensure that the ESD nMOS will not cause any extra leakage at the pin during normal operation (Without ESD). The avalanche breakdown voltage is reduced if the gate of nMOS is properly biased during a ESD strike. The gate voltage helps reduce the width of the pn-junction at the drain increase the electric eld in the junction and lower the avalanche breakdown voltage of the junction. The value of C and R must be such that (i) they have no eect on the operation of the circuit when there is no ESD stress, (ii) they must couple a sucient voltage to the gate during a ESD strike such that the avalanche breakdown voltage of nMOS is eectively reduced.
(26)

Gate-Coupled nMOS Transistors (contd)
DS (Avalanche breakdown voltage) V Internal circuits PAD C
R
VG
ID
Thermal breakdown
Reduced avalanche breakdown Avalanche breakdown
Vsp
VD
Figure 16: Gate-coupled nMOS
(27)

Drawbacks of nMOS-based ESD Protection
Eective for non-silicided processes. Less eective for silicided processes. Need additional ballast n-well resistors to increase ESD protection. Need gate-coupling circuitry to improve ESD protection.
(28)

Silicon-Controlled Rectiers (SCR)
Internal circuits
p+ n+ n+ p+
PAD pn-junction
Rnwell T1 Rsub p-substrate T2 n-well Ic2
Figure 17: Silicon-controlled rectiers (SCRs).
Under normal operation, the pn-junction between n-well and p-substrate is reverse biased and SCR has no eect on the operation of the protected circuits. During a ESD strike, the pn-junction undergoes an avalanche breakdown currents ow from n+ through Rnwell to the substrate a sucient voltage drop across Rnwell turns on T2 a large current ows from p+-diusion through Rsub to the ground T1 turns on T1 and T2 latch up to release ESD stress. SCR has a high ESD breakdown voltage (40V with the latch-up time 1ns) as compared with that of nMOS because the breakdown voltage of n+/p-sub is lower than that of n-well/p-sub (large pn-junction width) internal circuits might have already been destroyed even before ESD protection circuits are activated. SCR is not aected by silicidation attractive for modern CMOS processes where silicidation is common.

Medium-Voltage Triggered SCR
An additional n+ is added at the edge of the n-well to reduce the junction width.
n+-diffusion is added
Internal circuits
n+ n+ p+
PAD
p+
n+
Rnwell T1 Rsub p-substrate T2 n-well Ic2
Figure 18: Modied silicon-controlled rectiers (MSCRs).
During an ESD strike, pn-junction in this region undergoes an avalanche breakdown at a LOWER voltage. Breakdown voltage : 25V for 0.35 CMOS (40V for conventional SCR).
(30)

Low-Voltage Triggered SCR
An additional n+ is added at the edge of the n-well to reduce the junction width.
Internal circuits
Grouded-gate is added
PAD
p+
n+
n+
n+
p+
R nwell T1 Rsub p-substrate T2 n-well Ic2
Figure 19: Low-voltage silicon-controlled rectiers (LVTSCRs).
The added gate-grounded nMOS enters avalanche breakdown rst. Avalanche voltage is similar to gate-grounded nMOS (10V approximately).
(31)
ESD Protection Circuits

Requirements of ESD Protection Circuits :
Provide a low-impedance path from input pads to the ground during an ESD strike to release the static charge accumulated on the pads. Clamp the voltage of the pads at a level that is below the dielectric breakdown voltage of thin transistors during an ESD strike. Provide a very high impedance and a low capacitance during normal operation such that it has a little eect on the operation of the protected circuits.
(32)
ESD Protection Circuits

Basic Conguration
PAD
Primary ESD Elements Current limiting resistor Secondary ESD Elements
Internal circuits
Figure 20: Conguration of ESD protection circuits
Primary ESD protection elements shunt most of ESD currents. Primary ESD protection elements have large width and need more time to turn on. Secondary ESD protection elements serve to limit the voltage at the circuit being protected until the primary ESD protection devices are fully operational. Secondary ESD protection devices have smaller width. The eectiveness of the primary ESD protection devices is determined by the secondary protection stage. Note that due to the small dimensions, the secondary protection devices enter avalanche breakdown before the primary protection devices are activated. It is critical to ensure that the avalanche breakdown of the primary protection devices is activated before the secondary protection devices enter their thermal breakdown so that the secondary ESD protection devices will not be destroyed by ESD stress. Current-limiting resistor has two functions (i) limit the current owing into the internal circuits. (ii) withstand some ESD voltage so that the secondary protection circuit will not be damaged in an ESD strike.
(33)
ESD Protection Circuits (contd)

Basic Circuits
PAD
Current-limiting resistor
Internal circuits
Primary ESD elements
Secondary ESD elements
Figure 21: Basic ESD protection circuits
Both nMOS and pMOS are used for positive and negative ESD strikes. Under normal operation conditions, ESD devices are o minimize the leakage current of these devices.
(34)
ESD of 0.35 CMOS Processes

In sub-micron CMOS, the onset of damage has been observed at between 1 kV and 2kV. Design rules are set for 2 kV HBM and 200V MM. Min. resistance of the isolation n-well resistor : 200 . Soft-pull is used to balance the breakdown voltage and the speed of I/O ngers under ESD zapping.
(35)

Distributed ESD Protection Circuits
De-centralize a large capacitance into a set of small capacitances separated by inductors - a transmission line is constructed capable of transmitting high-frequency signals.
zo PAD
zo
zo
zo Internal circuits
z in
zo PAD C
zo C
zo C
zo C
Internal circuits
Figure 22: Top - Distributed ESD protection with equal sections; Bottom - small-signal equivalent circuit.
(36)

Multi-Finger Turn-On (MFT)
Thermal breakdown voltage of each nger of a large ESD protection transistor is made higher than the avalanche breakdown voltage of the nger. Lumped resistors are added at source and drain. The one at drain functions as ballast resistors while the one at source sense the ESD current and generates a voltage that is applied to the gate of the adjacent nger behave as a gate-coupled nMOS transistor.
Internal circuits
PAD
Rd
Rd
Rd
Rd
Rs
Rs
Rs
Rs
Figure 23: Equivalent circuit of poly back-end ballast with segmentation.
(37)

Soft-Ground-Gate nMOS MFT
Based on substrate pick-up technique when an ESD strike occurs, the potential of substrate increases. The gate potential increases as well behaves as gate-coupled nMOS transistor that have a low avalanche breakdown voltage (better ESD protection).
Internal circuits
PAD
Rd
Rd
Rd
Rd
Rs
Rs
Rs
Rs
Figure 24: Equivalent circuit of a soft-grounded-gate nMOS MFT.
(38)

Domino nMOS MFT
Lumped resistors are added at source and drain. The one at drain functions as ballast resistors while the one at source sense the ESD current and generates a voltage that is applied to the gate of the adjacent nger behave as a gate-coupled nMOS transistor.
Internal circuits
PAD
Rd
Rd
Rd
Rd
Rs1 Rs2
Rs1 Rs2
Rs1 Rs2
Rs1 Rs2 Macro-ballasting resistors
Figure 25: Equivalent circuit of domino nMOS MFT.
(39)

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ELE863/EE8501 VLSI Systems

Electrostatic Discharge Protection

Copyright (c) F. Yuan 2006

Copyright (c) F. Yuan 2006

Copyright (c) F. Yuan 2006

Introduction to ESD (contd)

Junction depth [m]

0.6 0.5 0.4 0.3 0.2 0.1 0

1.5 Lmin [m]

Figure 1: Scaling of gate oxide thickness of MOS transistors.

Copyright (c) F. Yuan 2006

Introduction to ESD (contd)

Junction depth [m]

Figure 2: Scaling of junction depth of MOS transistors.

Vt1, Vox [V]

40 60 Gate oxide thickness, t

Copyright (c) F. Yuan 2006

Principle Sources of ESD in ICs

Test and Handling Systems

IC Itself is Charged During Transport / Contact With Charged Objects

Copyright (c) F. Yuan 2006

Copyright (c) F. Yuan 2006

ESD Models (contd)

Copyright (c) F. Yuan 2006

ESD Models (contd)

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

= (nn + pp )q is the conductivity.

J is linearly proportional to E or equivalently the voltage across the semiconductors.

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

Jsat = nn vn,satq vn,sat 107cm/s, nn = 1017/cm3 Jsat = 1.6105A/cm2.

Figure 7: Velocity saturation

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

Covalent bond destroyed

Figure 8: Avalanche multiplication

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

ESD Protection Mechanisms (contd)

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

Copyright (c) F. Yuan 2006

ESD Protection Mechanisms (contd)

Thermal breakdown Thermal breakdown Avalanche breakdown Avalanche breakdown

Vt1 < Vt2

Vt2 < Vt1

(A) Avalanche breakdown voltage is less than thermal breakdown voltage

(B) Avalanche breakdown voltage is greater then thermal breakdown voltage

Figure 11: Avalanche breakdown/thermal breakdown voltages

Copyright (c) F. Yuan 2006

ESD Protection Devices

Copyright (c) F. Yuan 2006

ESD Protection Devices (contd)

Figure 12: Poly and n-well resistors

Copyright (c) F. Yuan 2006

ESD Protection Devices (contd)

Copyright (c) F. Yuan 2006

ESD Protection Devices (contd)