A Practical Report On

VLSI DESIGN LAB

Submitted in partial fulfillment of the requirements of the degree of MASTERS OF TECHNOLOGY To the

MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY

Submitted by

Submitted to

Radhika Kalawat

Miss Ko al Swa i
(ECE M !T"

DE!ARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY

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E$PER!ME T

PA%E O#

REMAR&S

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E"!ERIMENT# $
OB%ECT# (esign and simulate basic A ( %ATE# RE&UIREMENT# Modelsim PE Student Edition# THEORY# The A ( gate is a basic digital logic gate that implements logical con)unction# !t beha*es according to the truth table to the right# A +!%+ output (," results only if both the inputs to the A ( gate are +!%+ (,"# !f neither or only one input to the A ( gate is +!%+- a .O/ output results# !n another sense- the function of A ( effecti*ely finds the minimum bet0een t0o binary digits- )ust as the OR function finds the maximum# Therefore- the output is al0ays 1 e2cept 0hen all the inputs are ,s# S3M4O. 35 A#4 TRUTH TABLE# A 1 1 , , 4 1 , 1 , 3 1 1 1 ,

VHDL !ROGRAM# library ieee6 use ieee#std7logic7,,89#all6 entity and' is port(a-b :in bit6 c :out bit"6 end and'6 architecture and7' of and' is begin c ;5 a and b6 end and7'6

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RESULT# /e ha*e design A ( %ATE using Modelsim PE Student Edition#

E"!ERIMENT# '
OB%ECT# (esign and simulate basic OR %ATE# RE&UIREMENT# Modelsim PE Student Edition# THEORY# The OR gate is a digital logic gate that implements logical dis)unction ? it beha*es according to the truth table to the right# A +!%+ output (," results if one or both the inputs to the gate are +!%+ (,"# !f neither input is +!%+- a .O/ output (1" results# !n another sense- the function of OR effecti*ely finds the ma2imum bet0een t0o binary digits- )ust as the complementary A ( function finds the minimum# S3M4O. @5 AA4 TRUTH TABLE# A 1 1 , , 4 1 , 1 , @ 1 , , ,

VHDL !ROGRAM# library ieee6 use ieee#std7logic7,,89#all6 entity or7' is port(a-b:in bit6 c:out bit"6 end or7'6 architecture or' of or7' is begin c ;5 a or b6 end or'6

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RESULT# /e ha*e design OR %ATE using Modelsim PE Student Edition#

E"!ERIMENT# (
OB%ECT# (esign and simulate basic A ( %ATE# RE&UIREMENT# Modelsim PE Student Edition# THEORY#The egated A (- OT A ( or A ( gate is the opposite of the digital A ( gate- and beha*es in a manner that corresponds to the opposite of A ( gate- as sho0n in the truth table on the right# A .O/ (1" output results only if both the inputs to the gate are +!%+ (,"6 if one or both inputs are .O/ (1"- a +!%+ (," output results# The A ( gate is significant because any boolean function can be implemented by using a combination of A ( gates# This property is called functional completeness# S3M4O. &) *A+B,TRUTH TABLE# A 1 1 , , 4 1 , 1 , @ , , , 1

VHDL !ROGRAM# library ieee6 use ieee#std7logic7,,89#all6 entity nand' is port(a-b :in bit6 c :out bit"6 end nand'6 architecture nand7' of nand' is begin c ;5 a nand b6 end nand7'6

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RESULT# /e ha*e design A ( %ATE using Modelsim PE Student Edition#

E"!ERIMENT# .
OB%ECT# (esign and simulate basic OR %ATE# RE&UIREMENT# Modelsim PE Student Edition# THEORY# The OR gate is a digital logic gate that implements logical OR ? it beha*es according to the truth table to the right# A +!%+ output (," results if both the inputs to the gate are .O/ (1"6 if one or both input is +!%+ (,"- a .O/ output (1" results# OR is the result of the negation of the OR operator# OR is a functionally complete operation combinations of OR gates can be combined to generate any other logical function# S3M4O. @5 (AA4"E TRUTH TABLE# A 1 1 , , 4 1 , 1 , @ , 1 1 1

VHDL !ROGRAM# library ieee6 use ieee#std7logic7,,89#all6 entity nor' is port(a-b :in bit6 c :out bit"6 end nor'6 architecture nor7' of nor' is begin c ;5 a nor b6 end nor7'6

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RESULT# /e ha*e design OR %ATE using Modelsim PE Student Edition#

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E"!ERIMENT# /
OB%ECT# (esign and simulate basic OT %ATE# RE&UIREMENT# Modelsim PE Student Edition# THEORY# The OT gate is a digital logic gate that implements in*erts? it beha*es according to the truth table to the right# A +!%+ output (," results if the input to the gate is .O/ (1"6 if the input is +!%+ (,"- a .O/ output (1" results# OT is the result of the negation of the input# The OT gate is an electronic circuit that produces an in*erted *ersion of the input at its output# !t is also Gno0n as an inverter# !f the input *ariable is A- the in*erted output is Gno0n as OT A# This is also sho0n as AH- or A 0ith a bar o*er the top# S3M4O.

@5AE TRUTH TABLE# A 1 , @ , 1

VHDL !ROGRAM# library ieee6 use ieee#std7logic7,,89#all6 entity not7, is port(a:in bit6 b:out bit"6 end not7,6 architecture not, of not7, is begin b ;5 not a6 end not,6

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RESULT# /e ha*e design OT %ATE using Modelsim PE Student Edition

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E"!ERIMENT# 0
OB%ECT# (esign and simulate basic E$C.IS!=E JOR %ATE# RE&UIREMENT# Modelsim PE Student Edition# THEORY# The $OR gate (sometimes EOR gate- or E$OR gate" is a digital logic gate that implements an e2clusi*e or6 that is- a true output (," results if one- and only one- of the inputs to the gate is true (,"# !f both inputs are false (1" or both are true (,"- a false output (1" results# !ts beha*ior is summariKed in the truth table sho0n on the right# A 0ay to remember $OR is Lone or the other but not bothL# !t represents the inequality functioni#e#- the output is +!%+ (," if the inputs are not aliGe other0ise the output is .O/ (1"# This function is addition modulo '# As a result- $OR gates are used to implement binary addition in computers S3M4O.

@5 AE4AA4E TRUTH TABLE# A 1 1 , , 4 1 , 1 , @ 1 , , 1

VHDL !ROGRAM# ibrary ieee6 use ieee#std7logic7,,89#all6 entity e2or' is port(a-b :in bit6 c :out bit"6 end e2or'6 architecture e2or7' of e2or' is begin c ;5 a 2or b6 end e2or7'6

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RESULT# /e ha*e design $OR %ATE using Modelsim PE Student Edition#

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