Proc. IEEE 2005 Int. Conference on Microelectronic Test Structures, Vol.

18, April 2005

9. I
Capacitance Characterization in Integrated Circuit Development: The Intimate Relationship of Test Structure Design, Equivalent Circuit and Measurement Methodology George A. Brown

SEMATECH, Inc. 2407 MontopoIis Drive, Austin, TX 78741, USA

MSTRACT

This paper traces the historical and continuing relationship between integrated circuit device and material properties, capacitance test structure design, and measurement methodology. Design concepts for test structures useful for C-V characterization of EOT in ultra-thin leaky dielectrics are reviewed, and measurements on new and conventional devices are compared. The key premise is that test structure design should provide a structure with an equivalent circuit matching that used for measurement and data analysis.

usually negligible, even with the higher substrate resistivity used. With the relatively thick gate oxide and electrode films, test capacitors were sufficiently rugged that they could be probed directly on the device without need for probe pads. Under all these conditions, the Q of the capacitors was sufficiently high that it was inconsequential whether a series or parallel equivalent circuit was used for the capacitance measurement. In general, the capacitance reading one measured could be immediately associated with the gate capacitance.
Intermediate in this scaling process were situations in which, for example, it was realized that for MOS capacitance measurements, the shrinking gate oxide thickness was lowering the capacitive impedance of the gate dielectric to a point where use of a series RC equivalent circuit for capacitance measurement mode and data interpretation would desensitize the measurement result to the relatively high series resistance left over firom earlser test structure designs, where it didn't matter. This is illwtrated in Figure I. The flexibility of capacitancemeasuring tools to express their results as either equivalent series or parallel RC networks was most useful as long as our samples could be represented as one or the other of these options.

INTRODUCTION
From the earliest days of semiconductor device and circuit a half-centmy ago, capacitance development measurements have played a central role in material and In early bipolar devices, device characterization. capacitance data was used as a tool to evaluate and model minority carrier lifetime and device switching speed. With the advent of MOS device technology, capacitance-voltage (C-V) characterization of the gate elecbode-gate dielecaicchannel structure of the MOS transistor became an indispensable part of the development and control of the properties of all three elements of the devices. In this paper, we will trace the intimate relationship between device and material characteristics, test structures, and capacitance measurement and analysis equivalent circuits as they have evolved with the scaling of device dimensions.
EFFECT OF SCALING ON CAPACITANCE MEASUREMENT AND TEST STRUCTURE DESIGN

I:
I ,
I

In the process of device scaling over the years, materials and test structures have evolved f r o m a situation in which little attention needed to be given to capacitance test structures and measurements to today's and the future's need to tailor test structure design with extended capacitance measurement conditions in mind. This must be done to achieve an overall measurement methodology in which capacitance, or more properly, impedance measurements may be interpreted in terms of the values of the component equivalent circuit parameters of interest.

Figure 1. Impedance plane representation of series equivalent RC circuit with varying &,
Difficulties arose when further scaling of MOS transistors led to the thinning of gate oxides to the point that significant tunneling currents were present at operating n Figure 2, showing the voltages. This is illustrated i variation in apparent accumulation capacitance of the sample depending upon measurement mode. It is clear that both values cannot represent the true accumulation capacitance of the gate oxide. It was shown that an

In early MOS transistors, the gate dielectric was invariably SiOl, with thicknesses of about 100 nm. Here, the conductance of the oxide was very low and its impedance high, so that series resistance of the tcst s t r u m was 0-7803-8855-0105/$20.00 02005 IEEE

0~~1-137622

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equivalent circuit with three elements at least, like that shown i n ' Figure 3, would be required to describe the behavior of these capacitors'.

which included several other relevant This work essentially extended the dual fiequency approach of Yang and Hu to the use of frequency spectra. Following this concept, the dissipation factor-frequency characteristic of the three-eIement circuit of Figure 3 is given by

c!

a5

1.5

25

V-M

Figure 2. MOS capacitor with a conductive oxide measured in series and parallel mode.

This function has a mini" value, with branches above and below the minimum that vary inversely and linearly with frequency. In the low frequency regime, the relationship is

while at the high kequency limit, the expression becomes

D = wR,C,

(3)

Figure 3. Three-element equivalent circuit.

h ' A L Y S I S OF MORE

R=

If experimental data matches these predictions of the model, we can with some confidence extract the values of the equivalent ckcuit of Figure 3 for that sample. In order for this to be possible, the quality of the design of the test structure must be adequate to assure that its electrical behavior well approximates that of the linear circuit elements. Figure 4 is a plot of the relationship in equation 1, illustrating the nature of the dependence and the branches described by equations 2 and 3.

COMPLEX STRUCTURES

Analysis of this structure led to an understanding of two key guidelines that will be needed for present and future test structure design and measurement of capacitors with these conductive dielectrics. Higher measurement frequencies will be needed to emphasize the capacitive portion of the parallel equivalent circuit of the dielectric film. Much lower series resistance wiil be needed for the overall test structure, as the higher frequency lowers the overall impedance o f the equivalent i l m , and the series circuit of the dielectric f resistance must not dominate that of the dielectric we are trying to measure. With three elements in the equivalent circuit of our device, we have seen that we can no longer directly relate the capacitance value we measure with that of the dielectric f i l m . Since a capacitance measurement yields only two output parameters and there are three unknowns in ow equivalent circuit, a completely new approach to capacitance measurements in this regime will be required. Use of dual or multiple frequencies was suggested by Yang and Hu2to overcome this problem. Schmitz et aL3 gave a methodology for high frequency capacitance measurements at this conference in 2003,

+Telement

dreutl

Rs=SOohm
0.1
1

1.E+05

!.EMS 1. E 4 7 Frequency @]

1.E+O8

Figure 4. Dissipation factor- frequency plot for Ideal

tbree-element equivalent eircuiL

ADVANCED TEST S~~ucrrrtle DESIGNS

Implications of the two guidelines bulleted i n the previous section have been treated in recent capacitance test structure designs. One design that we have been fortunate a s supplied by Philips research laboratories5, and to use w features wafer level top surface ground-signal-ground probe connections to permit use of higher frequencies, and a large number of small capacitor elements imbedded in a sea of highly doped material to lower series resistance. The layout of this structure is shown in Figure 5 . The capacitor array shown in this figure consists of 720

214

elements, each of dimensions 2 . 6 ~ ,O 1 microns, for a total drawn area of 1 . 8 7 ~ 1 0 cm2. -~ An element of this array is shown in Figure 6. This array is similar to that used by Scbmitz et al. in reference 3.

HEiO gate dielectric with an EOT of 1.72 nm. Here, the series resistance Rs, primarily a finction of the test structure, is 18.4 ohms, while the dielectric effective O4 ohms. resistance, Ro, is reduced to 1 . 41~
10

1---

-"-I

'

.: .I. . . . . . . . . . . . . . . " .......................

!._....................

. " ........ . " ......... " . ...... ..... ...>'

~

0.01

l.OE+OS

1.OE+06

1.0+07
5"a~'

l.OE+OE

Figure 5. Layout of Philips UHF capacitor test structure, showing ground-signal-ground pads.

Fmquency plz]

Figure 8. Dissipation factor-frequency plot for an HfSiO dielectric in the UHF capacitor structure,

To evaluate the effectiveness of this approach to capacitor test structure design independent of the measurement technoIogy, the results obtained above are compared to those obtained on a more conventionally laid out MOS device that because of its location in its module can also be probed with a topside ground-signal-ground fixture. Its layout is shown in Figure 9.
Figure 6. Capacitor element of Philips UHF capacitance test structure.

A set of multiple-frequency C-V curves for one of these structures is given in Figure 7, measured with an Agilent 4294A Precision Parameter Analyzer using their I-V Probe connection technology.

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E
Figure 9. Conventional 30x30 pm transistor with pseudo-C-S-G connections.

Figure 7. Multi-frequency MOS C-V plots o f the PhiIips UHF capacitor with 2 nm SO, gate oxide, TiN gate.

In the frequency range from 100 kHz to 100 MHz, essentially frequency-independent C-V curves are obtained on this device, having a 2 nm SiOz gate dielectric with a polysilicon electrode. Plotting the dissipation factor for this data set in strong accumulation (-2V) versus frequency as in Figure 4 yields the same frequency dependence, permitting extraction of parameter values Rs = 15.2 ohm and Ro = 2 . 0 ~ 1 0 ohm ~ for this condition. This procedure is illustrated in Figure 8 for a similar device having a

The device is a 30pm x 30pm transistor (area = 9 . 0 ~ 1 0 - ~ cm*) with its gate pad surrounded by two topside p-well contacts. The source and drain connections are not used in these measurements, so that inversion layer response is not seen in the C-V curves. The dissipation factor-frequency plot for the device in strong accumulation (-2V) is shown in Figure 10. Considerable distortion of the dependence is . This observed, compared to the ideal model of Figure 4 distortion, which is also seen in the C-V data, is taken as evidence of the failure of this device structure to approximate the ideal three-element equivalent circuit with linear, frequency-independent parameters. A value of effective series resistance Rs of 358 ohms is extracted from the high frequency branch of the data in Figure 10. Estimates of this parameter from other data sets with different processing range from about 125 to 400 o h s ,

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compared to values of 15-25 ohms for the Philips UHF capacitor of Figure 5

RI-318

ohm.

Significant distortion of the test structure is seen, resulting in at least 30% reduction in active area relative to the drawn value. The difficulty in estimating the active area of such a capacitor element can better be judged from the top-view micrograph of a series of three of the capacitor elements, shown in Figure 12, which includes a comparison with a similar set of four elements built using a shallow trench isolation (STI) flow. It is clear that this latter structure has much better control of the active area, and it has been useful for this work

DO1 1 E105

1 E+DS 1 Er07 F w w wN I

1 E+O8
mta2 16

Figure IO. Dissipsfion-frequency plot for 30 x 30 pn conventional MOSCAP.

DESIGN CONSTRAINTS FOR

ADVANCED MOSCAP TEST STRUCTURES

One caveat must be expressed in terms of design constraints on such MOS capacitor test structures. It must never be forgotten that accurate calculation of MOS capacitor parameters depends critically upon precise knowledge of the active area of the capacitor. This of course depends upon having properly designed open circuit, short circuit and load calibration structures for use in the measurements, but one must also keep in mind the physical limitations of device geometry associated with the process technology used in the fabrication of the test structures. An example of this was found in the early use of this test structure, in which devices were fabricated using an older poly buffered LOCOS (PBL) process flow. A well-known feature of this process is that there is a limitation in the control of smaller device geometries, because of the encroachment of the isolation oxide into the active device areas. This is illustrated in Figure 1 1, which is a cross-section SEM taken vertically across one end of the capacitor element shown in Figure 6 .

PBL

STI

Figure 12. Comparison of capacitor element geometries of the test structure of Figure 4, built with different isolation technologies.

Still, neither isolation technology provides devices with active areas equivalent to the drawn area., which is 1 .S7xlO- cm2 Therefore effective area calibration must be done using wafers with known or accurately measurable EOT using conventional capacitors of known area for comparison with C-V data on the UHFCAP device. For the PEL shuctures, this has given a broad range of Effective areas, ranging &om 8 . 7 ~ 1 cm2 0 ~ to I . Z X I O - ~cm2 depending on the degree of geometry distortion. This range is so great that calibrations must be done on nearly
all wafers, making the UHF devices virtudy useless for

EOT evaluation, As suggested by the micrographs of Figure 12, the situation is much better for the STl isolated devices. Here we have found effective areas of about 1 . 4 ~ 1 0cm2. - ~ In some cases, this value is obtained both by area estimation from micrographs as well as from capacitance calibration as described above. However, in some cases, process deviations have yielded effective areas as high as 1.7x10- cm2, leading to the need to check area calibration on at least some wafers from any process lot to be used for EOT evaluation.
These findings lead to an additional constraint on UHFCAP design for EOT evaluation, added to the two that were bulleted above. This is that the area of the capacitor elements used to build the capacitor a m y much each be large enough that effective area variation due to resist sizing and etch undercuUfoot effects will be within tolerable limits for EOT determination. With gate stack EOTs going beneath 1 nm, EOT variation of only a fraction of an angstrom can be tolerated, calling for very high precision in C-V parameter extraction. This precision

Figure 11. Isolation encroachment in the test structure of Figure 6 .

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is directly related to the precision with which the capacitor effective area is known.
CONCLUSION

We have seen that if test capacitor structures for ultra-thin, leaky dielectrics are designed with an eye to measurement requirements, i.e. the use of high measurement frequencies arid the need for very low series resistance, good quality C-V characteristics can be obtained. An additional requirement has been identified if the structures are to be used for EOT evaluation; the need for highly precise and accurate control of the effective active area o f the capacitor, through design of the structure etements and provision of accurate zeroing and load calibration devices.
The design concept suggested here is to attempt to realize a test structure that matches the simplest possible equivalent circuit that will be used for measurement and data analysis rather than to attempt to generate more complex equivalent circuits to match the characteristics of the designed device.
ACKNOWLEDGEMENT

I t is a pleasure to acknowledge the support of my colleagues at SEMATECH in this work, especially Jeff Peterson and Paul Kirsch for the use of their lots and their processing support, and Kenneth Matthews for the electrical characterization.
REFERENCES

Henson, W. K., et al., Estimating Oxide Thickness of Tunnel Oxides Down to 1.4 nm Using Conventional Capacitance Measurements on MOS Capacitors, IEEE Elect. Dev. Lett., 20, #4 (1999), pp.179-181. Yang, K. and Hu, C., MOS Capacitance for High-Leakage Thin Measurements Dielectrics, IEEE Trans. on Elect. Dev. 46, #7 (1999),pp. 1500-1501. 1. Schmitz et al., Test Structure Design Considerations for RF-CV Measurements on Leaky DieIectrics, Proc. 2003 IEEE ICMTS (2003), pp. 181-185. Rideau, D. et al., Series Resistance Estimation and C(V) Measurements on Ultra Thin Oxide MOS Capacitors, ibid. PP. 191-1 96. Okama, Y. et al., The Negative Capacitance Effect on the C-V Measurement of Ultra Thin Gate Dielectrics Induced by the Stray Capacitance of the Measurement System, ibid., pp.197-202. We are indebted to IMEC and Philips Research Laboratories for access to this set of test structures.

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