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Digital design Combinatorial circuits: it!out status Sequential circuits: it! status FSMD design: !ard ired "rocessors Language based H# design: VHDL
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#!at is VHDL2
& "rogramming language 'or describing t!e be!a*ior o' digital s)stems Design entr) language+ used 'or 3nambiguous s"eci'ication at be!a*ioral and 45L le*el Simulation 6e.ecutable s"eci'ication78 S)nt!esis Documentation
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)ou s"eci') @addA instead o' Botting do n a s"eci'ic t)"e o' adder: t!e s)nt!esis tool ill instantiate t!e best t)"e o' adder under timing+ area C "o er constraints eas) to "arametrise 6e,g, ord lengt!+ queue de"t!8 eas) to s"eci') arra)s o' com"onents
Dortable across man) tools 'or simulation+ s)nt!esis+ anal)sis+ *eri'ication+ 7 o' di''erent *endors 6e,g, S)no"s)s+ Mentor Era"!ics+ 78
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%999 standard 1:;<,1-1=== is a su"er-set o' t!e 'ull %999 VHDL 1:;<-1==/ standard 'or digital design
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%nterconnected 'unctions Inl) in'o on 'unctions or algorit!ms 6 !at8 Inl) timing needed to let t!e 'unction or( correctl) IK 'or VHDL Je!a*ioral s)nt!esisers immatureG used 'or !ig! le*el e.ecutable s"eci'ication in to"-do n design and manual s)nt!esis into 45L
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Eate le*el
%nterconnected gates and 'li"-'lo"s %n'o on 'unction and arc!itecture %n'o on tec!nolog) de"endent timing 6gate dela)s8
La)out
%n'o on la)out on silicon Continuous timing &nalog e''ects
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More ides"read in 3S& t!an in 9uro"e I'ten required 'or gate le*el or 45L le*el &S%C sign-o'' ?e*er ending discussion !ic! is better
DLD languages li(e &J9L+ D&L&SM+ 7
5!ese are more at t!e gate le*el+ ca"turing also tec!nolog) de"endent 'eatures 6e,g, detailed timing8
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arc!itecture Je!a*1 o' Com"are is begin @&rc!itectureA describes 9M Q1 @1A !en 6&1J8 else @:AG t!e be!a*ior and structure end arc!itecture Je!a*1G o' t!e entit)+ t!e internals o' t!e bo. ?otes: - Multi"le arc!itectures "er entit) are "ossible: di''erent a)s o' im"lementing same be!a*ior - 5!is arc!itecture s"eci'ies be!a*ior at 45L le*el and not t!e actual structure o' gatesG s)nt!esis tool ill automaticall) translate t!is 45L be!a*ioral descri"tion into gate le*el - Dorts !a*e an e."licit direction and are 6*ectors o'8 bits
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S"eci'ication o' t!e ne.t !ig!er le*el in t!e circuit !ierarc!): @5estA
arc!itecture Struct1 o' 5est is com"onent Com"arator is 5 o instantiations "ort6 -+F: in bitP*ector6: to ;8G o' t!e same com"onent R: out bit8G @Com"aratorA it! its end com"onent Com"aratorG signal binding begin Com"are1: com"onent Com"arator "ort ma" 6%n1+%n$+Iut18G Com"are$: com"onent Com"arator "ort ma" 6%n1+%n/+Iut$8G end arc!itecture Struct1G ?otes: - 5!e t o @com"aratorA com"onents or( concurrentl)HHH - 5!is arc!itecture describes structure+ i,e, !o t!is entit) consists o' an interconnection o' lo er le*el com"onents
Virtual de*ice: allo s 'or concurrent de*elo"ment o' bot! !ierarc!ical le*els+ b) di''erent "ersons, @Com"aratorA ill be bound to @Com"areA later
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?otes: - Inl) one be!a*ior "er 'unction "ossible - Je!a*ior is s"eci'ied at rat!er !ig! le*el and ill be automaticall) translated b) t!e com"iler into &SM instructions - Function arguments do not !a*e a direction and are o' t)"e int
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?otes: - 5!e t o @com"areA 'unction calls are e.ecuted sequentiall) - 5!is main "rogram is e.ecuted once and sto"s, %n VHDL+ all com"onents describe relations t!at are *alid continuousl) and 'ore*er
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-- Con'iguration in'ormation: arc!itecture selection -- and com"onent-entit) binding Jot! @use entit)As could be combined in one: con'iguration Juild1 o' 5est is 'or &ll: Com"arator ,,, 'or Struct1 'or Com"are1: Com"arator use entit) Com"are6Je!a*18 "ort ma" 6& 1V -+ J 1V F+ 9M 1V R8G end 'orG 'or ot!ers: Com"arator use entit) Com"are6Je!a*18 "ort ma" 6& 1V -+ J 1V F+ 9M 1V R8G end 'orG end 'orG end con'iguration Juild1G ?ote: @con'igurationA corres"onds in S# to @lin(ingA
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&4CH%59C5349: arc!itecture &rc!itecturePname o' 9ntit)Pname is localPsignalPdeclarationsG com"onentPdeclarationsG begin statementsG end arc!itecture &rc!itecturePnameG
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-- /-in"ut &?D gate entit) &?D/ is "ort 6 &+J+C: in bitG F: out bit8G end entit) &?D/G arc!itecture 45L o' &?D/ is begin F Q1 @1A !en 66&1@1A8 and 6J1@1A8 and 6C1@1A88 else @:AG end arc!itecture 45LG
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-- /-in"ut I4 gate entit) I4/ is "ort 6 &+J+C: in bitG F: out bit8G end entit) I4/G arc!itecture 45L o' I4/ is begin F Q1 @:A !en 66&1@:A8 and 6J1@:A8 and 6C1@:A88 else @1AG end arc!itecture 45LG
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arc!itecture Je!a* o' M3-$1 is begin F Q1 & !en 6S1@1A8 else JG end arc!itecture Je!a*G
Je!a*ioral descri"tion
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Com"onents R F R
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& VHDL @test benc!A can be considered to be t!e to" le*el o' a design
%t instantiates t!e Design 3nder 5est 6D358 a""lies stimuli to it c!ec(s !et!er t!e stimuli are correct or ca"tures t!e out"uts 'or *isualisation in a a*e'orm *ie er
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Ho
to use a "ac(age2
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& JitP*ector is a collection o' bitsG a *alue is s"eci'ied bet een double quotes: constant State1: bitP*ector60 do nto :8 :1 X::1::YG MSJ+ bit 0 & String is a collection o' c!aractersG a *alue is s"eci'ied bet een double quotes: constant 9rrorPmessage: string :1 X3n(no n error: as( )our "oor s)so" 'or !el"YG LSJ
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?ot all s)nt!esis tools su""ort enumerated t)"es #!en t!e) do su""ort t!em+ t!e de'ault encoding is o'ten straig!t'or ard encoding using t!e minimum number o' bits I'ten+ t!e de'ault encoding ma) be o*er- ritten b) some !ere s"eci')ing somet!ing li(e XencodingPst)le is gra)PcodeY or b) e."licitl) s"eci')ing t!e encoding 'or eac! "ossible *alue: constant reset: bitP*ector :1 X1::::YG constant ait: bitP*ector :1 X:1:::YG constant in"ut: bitP*ector :1 X::1::YG constant calculate: bitP*ector :1 X:::1:YG constant out"ut: bitP*ector :1 X::::1YG
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4esol*er circuit 4
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Corres"ondence b) "ositionH
Jus6/ do nto :8 Q1 &G Jus65 do nto 08 Q1 &6: to 18G Jus65 do nto 08 Q1 &6: to 18G Jus60 do nto /8 Q1 &6$ to /8G
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entit) EeneralPmu. is generic 6 idt! : integer8G "ort 6 %n"ut : in stdPlogicP*ector 6 idt! - 1 do nto :8G Select : in integer range : to idt! - 1G Iut"ut : out stdPlogic8G end entit) EeneralPmu.G 5!is is not *alid VHDL: inde. is not (no n at arc!itecture Je!a* o' EeneralPmu. is design timeH #e ill begin re"lace t!is b) *alid Iut"ut Q1 %n"ut6Select8G code laterH end arc!itecture Je!a*G entit) 5estbenc! is end entit) 5estbenc!G arc!itecture Juild1 o' 5estbenc! is constant %n"utPsiLe : integer :1 >G signal & : stdPlogicP*ector 6%n"utPsiLe-1 do nto :8G signal S : integer range : to %n"utPsiLe - 1G signal J : stdPlogicG begin D35: entit) EeneralPmu.6Je!a*8 generic ma" 6 idt! 1V %n"utPsiLe8 "ort ma" 6%n"ut 1V &+ Select 1V S+ Iut"ut 1V J8G ,,, end arc!itecture Juild1G
Eeneric constants
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Logical I"erators
List o' logical o"erators: not+ and+ or+ .or+ nand+ nor Drecedence:
@notA !as !ig!est "recedence all ot!ers !a*e equal "recedence+ lo er t!an @notA
Logical o"erators are "rede'ined 'or 'ollo ing data t)"es: bit+ bitP*ector+ boolean+ stdPlogic+ stdPlogicP*ector+ stdPulogic+ stdPulogicP*ector & logical o"erator ma) or( on an arra):
arra)s s!ould !a*e same siLe elements are matc!ed b) "osition
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Logical I"erators
librar) %999G use %999,StdPLogicP11<0,&llG entit) Eate is "ort6 &+J+C: in stdPlogicG R: out stdPlogic8G end entit) EateG arc!itecture Logical o' Eate is begin R Q1 & and not6J or C8G end arc!itecture LogicalG
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Logical I"erators
librar) %999G use %999,StdPLogicP11<0,&llG entit) Eate is generic6 idt! : integer range : to /18G "ort6 &+J+C: in stdPlogicP*ector6 idt!-1 do nto :8G R: out stdPlogicP*ector6 idt!-1 do nto :88G end entit) EateG arc!itecture Logical o' Eate is begin R Q1 & and not6J or C8G end arc!itecture LogicalG
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4elational I"erators
List o' relational o"erators: Q+ Q1+ 1V+ V+ 1+ /1 4elational o"erators return a boolean Jot! o"erands need to be o' t!e same t)"e & relational o"erator ma) or( on an arra):
arra)s ma) !a*e di''erent siLeHH 5!e) are le't alligned and t!e number o' bits equal to t!e smallest arra) are com"aredG t!e com"arison is done bit b) bit+ 'rom le't to rig!t 4emember: *ectors o' bits do not !a*e a numerical meaningHH Ho e*er+ t!is com"arison or(s on *ectors o' bits it! t!e meaning o' an unsigned integer !en bot! *ectors !a*e equal lengt!
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4elational I"erators
librar) %999 use %999,StdPLogicP11<0,&llG entit) Com"are is "ort6 &: in stdPlogicP*ector6/ do nto :8G J: in stdPlogicP*ector6: to 08G R: out boolean8G end entit) Com"areG arc!itecture 4elational o' Com"are is begin R Q1 5439 !en &QJ else F&LS9G end arc!itecture 4elationalG entit) 5estbenc! end entit) 5estbenc!G arc!itecture Juild1 o' 5estbenc! is signal &: stdPlogicP*ector6/ do nto :8 :1 X111:YG signal J: stdPlogicP*ector6: to 08 :1 X1:111YG signal R: booleanG begin D35: entit) Com"are64elational8 "ort ma" 6& 1V &+ J 1V J+ R 1V R8G end arc!itecture Juild1G #!at is t!e *alue o' R2 54392 F&LS92 111: is com"ared to 1:11 b) bit "osition 'rom le't to rig!tG in t!e $nd "osition &6$8 V J618 !ence 6&QJ8 is F&LS9
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&rit!metic I"erators
List o' arit!metic o"erators: Z+ -+ S+ /+ SS 6e."onential8+ abs 6absolute *alue8+ mod 6modulus8+ rem 6remainder8 5!e) are de'ined on t)"es integer and real 6e.ce"t mod and rem8 and not on *ectors o' bitsG use o*erloading "ac(age 'or t!e latter 6*endor de"endent8 Jot! o"erands !a*e to be o' same t)"eG di''erent ranges are allo ed & *ariable o' "!)sical t)"e 6e,g, time8 ma) be multi"lied b) an integer or real and ill still return a *ariable o' t!e "!)sical t)"e
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&rit!metic I"erators
entit) &dd is "ort 6 &+J: in integer range : to ;G R: out integer range : to 108G end entit) &ddG arc!itecture Je!a* o' &dd is begin R Q1 & Z JG end arc!itecture Je!a*G
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Concurrent Statements
&ll statements are concurrent and are continuousl) *alid: t!is mimics t!e be!a*ior o' !ard are+ !ere all gates o"erate concurrentl)
entit) Concurrent is "ort 6 &+J+C+D: in stdPlogicG F+R: out stdPlogic8G end entit) ConcurrentG arc!itecture Struct o' Concurrent is begin ?&?D1: entit) ?&?D$ "ort ma" 6&+J+F8G ?&?D$: entit) ?&?D$ "ort ma" 6C+D+R8G end arc!itecture StructG #!at is t!e di''erence in be!a*ior a'ter ?&?D$2
Sc!ematic: & J C D
F R
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Concurrent Statements
&ll statements are concurrent and are continuousl) *alid: t!is mimics t!e be!a*ior o' !ard are+ !ere all gates o"erate concurrentl)
entit) Concurrent is "ort 6 &+J+C+D: in stdPlogicG F+R: out stdPlogic8G end entit) ConcurrentG arc!itecture Struct o' Concurrent is begin ?&?D$: entit) ?&?D$ "ort ma" 6C+D+R8G ?&?D1: entit) ?&?D$ "ort ma" 6&+J+F8G end arc!itecture StructG
Sc!ematic: & J C D
F R
Concurrent Statements
Does t!is sc!ematic s"eci') sequential Je!a*ior2 Fes ?o entit) Concurrent is "ort 6 &+J+ D: in stdPlogicG R: out stdPlogic8G end entit) ConcurrentG arc!itecture Struct o' Concurrent is signal 51: stdPlogicG begin ?&?D$: entit) ?&?D$ "ort ma" 651+D+R8G ?&?D1: entit) ?&?D$ "ort ma" 6&+J+518G end arc!itecture StructG & J D 51 R Sc!ematic:
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Simulation
5!is continuousl) u"dating o' out"uts "oses "roblems to t!e simulator: e*en i' not!ing in t!e circuit c!anges+ t!e simulator !as to com"ute continuousl) t!e @ne A out"uts o' all gates Solution: e*ent-dri*en simulation
a statement is onl) re-e*aluated !en one or more o' its in"ut signals c!anges 6i,e, !en an e*ent occurs at one o' its in"uts8 e sa) t!at a statement is sensiti*e to all its in"ut signals+ because an e*ent at an) in"ut signals triggers a re-e*aluation (ee" in mind t!at t!is mec!anism is onl) 'or ma(ing simulation 'ast !ile maintaining t!e same be!a*ior as in realit)+ !ere all gates or( continuousl)HH
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Simulation
Ho is an e*ent-dri*en simulator "racticall) im"lemented2
1, Dut all statements it! at least one c!anged in"ut in t!e @"rocess e.ecution queueA $, 9.ecute all statements in t!e "rocess e.ecution queue one b) one 6or concurrentl) i' t!e simulator is e.ecuted on a "arallel com"uter8 it!out u"dating t!e out"ut signals /, &'ter all statements in t!e "rocess e.ecution queue are "rocessed+ u"date t!e out"ut signals 0, &dd all statements to t!e "rocess e.ecution queue t!at !a*e an e*ent because o' t!e u"dated out"ut signals 5, 4e"eat until t!e "rocess e.ecution queue is em"t) <, &d*ance s)stem time to t!e ne.t time !ere a timed e*ent is "lanned 6e,g, testbenc!: ait'or $: ns8 Delta c)cle con*ergence Delta c)cle
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 ?&?D1 & MA M
& J M MA 51 5$
it! in"ut
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 ?&?D$ & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 ?&?D$ & MA M
& J M MA 51 5$
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it! e*ent
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 : Drocess 9.ecution Mueue 51 ?&?D$ & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 : Drocess 9.ecution Mueue 51 ?&?D$ & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 ?&?D1 & MA M
& J M MA 51 5$
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it! e*ent
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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Ste" 0: &dd statements it! e*ent to D9M 9nd Delta c)cle / o' 51: con*ergence
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 M Q1 1 Drocess 9.ecution Mueue 51 & MA M
& J M MA 51
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Ste" $: 9.ecute statements in D9M and remember out"ut ?&?D$ com"uted using t!is MA+ not t!e remembered 5$
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 M Q1 1 Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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it! e*ent
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 : Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 : Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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it! e*ent
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 1 Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
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Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 1 Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
5/>0
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
5/>5
Ste" 0: &dd statements it! e*ent to D9M 9nd Delta c)cle / o' 5$: con*ergence
Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M
& J M MA 51 5$
5/><
Drocess
Sometimes+ t!e combinatorial equation in a single statement becomes *er) com"licated:
& J C D entit) Com"le. is "ort6 &+J+C+D+9+F+E+H+%+[: in stdPlogicG F+R: out stdPlogic8G end entit) Com"le.G arc!itecture Struct o' Com"le. is begin F Q1 66& nand J8 nand 6C nand D88 !en 6S 1 @1A8 else 669 nand F8 nand 6E nand H88G R Q1 % nand [G end arc!itecture StructG 9 F E H % [ S F
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Drocess
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Drocess
S)nta. o' "rocess: DrocessPname: "rocess 6sensiti*it)Plist8 is -- *ariable declarationsG begin -- sequential commands end "rocess DrocessPnameG
S)nta. o' *ariable assignment: VariablePname :1 e."ressionG #!en assigning to *ariable :1 #!en assigning to signal Q1
5/>=
Drocess
4e rite t!e e.am"le using a "rocess:
entit) Com"le. is "ort6 &+J+C+D+9+F+E+H+%+[: in stdPlogicG F+R: out stdPlogic8G end entit) Com"le.G 51 and 5$ !a*e no "!)sical meaning since eac! re'ers to $ di''erent "!)sical ires 51 5$
5/=:
arc!itecture Struct o' Com"le. is Sensiti*it) list begin FP"rocess: "rocess 6&+J+C+D+9+F+E+H+S8 is *ariable 51+5$: stdPlogicG & begin i' 6S1@1A8 t!en J 51 :1 & nand JG C 5$ :1 C nand DG D else 9 51 :1 9 nand FG 5$ :1 E nand HG F end i'G E F Q1 51 nand 5$G H end "rocess FP"rocessG % R Q1 % nand [G end arc!itecture StructG [
F S
Drocess
Drocesses and delta c)cle con*ergence, #!at is t!e be!a*ior o' 'ollo ing "rocess:
9.am"le: "rocess 6&+J+M8 is begin Ild MHHH M gets F Q1 &G onl) ne *alue M Q1 JG at end o' "rocess R Q1 MG end "rocess 9.am"leG 1, &ssume e*ent at J it! ne *alue JA $, Drocess 9.am"le is e.ecuted once sequentiall), Follo ing out"uts are remembered: FA Q1 &G MA Q1 JAG RA Q1 MG
/, Drocess 9.am"le sus"ends 6i,e, is e.ecuted once com"letel)8, F+ M and R get t!eir ne *alues FA+ MA+ RA, 0, Since M is in t!e sensiti*it) list+ t!e 9.am"le "rocess is "laced again in t!e Drocess 9.ecution Mueue, 5, Drocess 9.am"le is e.ecuted: FY Q1 &G MY Q1 JAG RY Q1 MAG <, Iut"uts F+ M and R get t!eir ne
5/=1
Drocess
Drocesses and delta c)cle con*ergence, #!at is t!e be!a*ior o' 'ollo ing "rocess:
9.am"le: "rocess 6&+J+C+D8 is begin R Q1 & Z JG R Q1 C Z DG end "rocess 9.am"leG 1, &ssume e*ent at J it! ne *alue JA $, 5!e commands o' Drocess 9.am"le are e.ecuted sequentiall), First 'ollo ing out"ut is remembered: RA Q1 & Z JAG /, ?e.t+ t!e second command is e.ecuted and 'ollo ing out"ut is remembered: RA Q1 C Z D, 5!is o*er rites t!e "re*iousl) remembered RA 0, Drocess 9.am"le sus"ends and !ence signal R is u"dated it! its ne *alue C Z D #!en t!e same t o statements ould !a*e occurred outside a "rocess+ bot! ould dri*e signal R and a resol*er ould be necessar)
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5/=/
%F statement: i' condition t!en -- sequential statements else -- sequential statements end i'G
multi"le %F statements: i' condition1 t!en -- sequential statements elsei' condition$ t!en -- sequential statements elsei' condition/ t!en -- sequential statements else -- sequential statements end i'G
5!e 'irst condition !ic! turns out to be 5439 determines !ic! sequential statements are e.ecuted: built-in "riorit)
5/=0
4equirements: 1, &ll "ossible *alues s!ould be s"eci'ied $, 5!e *alues s!ould be constant and (no n at design time /, 5!e *alues s!ould !a*e t!e same t)"e as t!e e."ression
9.am"le: "rocess 6&+J+C+-8 is begin case - is !en : to 0 1V R Q1 JG !en 5 1V R Q1 CG !en ; \ = 1V R Q1 &G !en ot!ers 1V R Q1 @:AG end "rocess 9.am"leG
5/=5
5/=<
#e indicated t!at t!is is not *alid VHDL: inde. is not (no n at design timeH #e ill re"lace t!is no b) *alid code using t!e loo" construct,
5/=;
5/=>
Variables
& *ariable can onl) be used it!in a "rocess & *ariable is u"dated immediatel)G a signal is stored in t!e signal u"date queue till t!e "rocess sus"ends Variables ma) be assigned to signals and *ice *ersa Variables are used as intermediate *alues to 'acilitate t!e s"eci'ication o' t!e "rocessG !en t!e *alue o' a *ariable needs to be accessible outside t!e "rocess+ it s!ould be assigned to a signal
5/==
Variables
#it! !ic! !ard are sc!ematic does 'ollo ing code corres"ond2 entit) Darit) is generic 6 idt! : integer8G "ort 6&: in stdPlogicP*ector 6: to idt!-18G Idd: out stdPlogic8G 5!is is t!e H# structure end entit) Darit)G as it is gi*en to t!e s)nt!esis tool, 5!e s)nt!esis tool arc!itecture Struct o' Darit) is ill o"timiLe a a) t!e .or begin it! constant @:A in"ut Darit): "rocess6&8 is and ill trans'orm it to *ariable 5em": stdPlogicG a binar) tree o' less de"t! begin 5em" :1 @:AG 'or % in &Alo to &A!ig! loo" : 5em" :1 5em" .or &6%8G 5em" end loo"G &6:8 Idd Q1 5em"G end "rocess Darit)G 5em" end arc!itecture StructG &618 Idd &6$8
5/1::
Since t!ere is no 9LS9 "art t!e "re*ious M *alue !as to be remembered 'or t!e case !ere Cl(1@:A, 5!e s)nt!esis tool ill !ence in'er a latc! instead o' Bust combinatorial logicHHH Je are o' unintended latc!es !en 9LS9 "arts are omitted
it! a D-'li"-'lo"HH
#!en a Cl(-e*ent occurs and Cl( is lo + not!ing !a""ens #!en a Cl(-e*ent occurs and Cl( is !ig!+ t!e D in"ut is co"ied to t!e M out"ut
5/1:1
#!en a D-e*ent occurs and Cl( is !ig!+ t!e D in"ut is co"ied to t!e M out"ut 1V !ence a latc!: !en Cl( is !ig!+ M 'ollo s D
5/1:$
5/1:/
@#ait untilA !as to be 'irst line o' "rocess+ 'ollo ed b) t!e descri"tion o' t!e combinatorial circuit
5/1:0
arc!itecture 45L o' 4egisteredCircuit is begin "rocess 6&+J+C+D+Cl(8 is begin i' 6Cl(Ae*ent and Cl(1@1A8 t!en -- combinatorial circuit R Q1 6& and J8 or 6C and D8G end i'G end "rocessG end arc!itecture 45LG
@i' Cl(Ae*entA !as to be 'irst line o' "rocess+ it! t!e descri"tion o' t!e combinatorial circuit in t!e 5H9? "art and it! no 9LS9 "art
5/1:5
5/1:<
entit) DFli"Flo" is "ort 6D+Cl(+ 4eset: in stdPlogicG M: out stdPlogic8G end entit) DFli"Flo"G arc!itecture 45L o' DFli"Flo" is begin "rocess 6D+ Cl(+ 4eset8 is begin i' 64eset 1 @1A8 t!en M Q1 @:AG elsei' 6Cl(Ae*ent and Cl(1@1A8 t!en M Q1 DG end i'G end "rocessG end arc!itecture 45LG
5/1:;
5/1:>
Start11 3"1: Do n/ 11
State 4eg
3"$ 1:
Do n$ 1:
Start
5/1:=
3"
3"/ 11
Do n1 :1
Start11 3"1: Do n/ 11
3"$ 1:
Do n$ 1:
3"/ 11
Do n1 :1
5/11:
Iut"utLogic: "rocess6CurrentState8 is begin case CurrentState is !en #ait 1V Iut"ut Q1 X::YG !en 3"1\Do n1 1V Iut"ut Q1 X:1YG !en 3"$\Do n$ 1V Iut"ut Q1 X1:YG !en 3"/\Do n/ 1V Iut"ut Q1 X11YG end caseG end "rocess Iut"utLogicG
Start11 3"1: Do n/ 11
3"$ 1:
Do n$ 1:
3"/ 11
Do n1 :1
5/111
Start11 3"1: Do n/ 11
3"$ 1:
Do n$ 1:
3"/ 11
Do n1 :1
5/11$
Start11 3"11 State4egister: "rocess6?e.tState+Cl(+4eset8 is begin i' 4eset1@1A t!en CurrentState Q1 #aitG elsei' 6Cl(Ae*ent and Cl(1@1A8 t!en CurrentState Q1 ?e.tStateG end i'G end "rocess State4egisterG 3"1 :1
Start11 3"1: Do n/ 11
3"$ 1:
Do n$ 1:
3"/ 11
Do n1 :1
5/11/
5/110
4esource s!aring
#!at is t!e circuit corres"onding to: i' Sel 1 @1A t!en R Q1 & Z JG else R Q1 & Z CG end i'G Sel 5!is is (ind o' stu"id+ since bot! additions are mutuall) e.clusi*e: it is !ence not necessar) to im"lement $ adders, J Some s)nt!esis tools are ca"able to recogniLe t!is 6o'ten onl) it!in t!e sco"e o' a "rocess8 and trans'orm t!is into t!e s!ared use o' one adder 'or bot! additions, -ilin. Foundation Series "er'orms t!is o"timiLation it!in a !ierarc!ical le*el, Sel & J & C
M3R C M3&
Z R
5/115
4esource s!aring
%' t!e s)nt!esis tool does not do t!is o"timiLation automaticall)+ )ou s!ould re- rite )our code: i' Sel 1 @1A t!en - :1 JG else - :1 CG end i'G R Q1 & Z -G J Sel C M3&
Z R
5!e VHDL coding st)le toget!er it! t!e ca"abilities o' t!e s)nt!esis tool determine t!e circuit t!at is e*entuall) s)nt!esiLed,
5/11<
5/11;
3sing LogiJLI- ma(es )our VHDL im"lementation more e''icient on -ilin. FDE& but less "ortable to ot!er de*icesHH
5/11>
?e.tStateLogic: "rocess6CurrentState8 is begin case CurrentState is !en %dle 1V ?e.tState Q1 S1G !en S1 1V ?e.tState Q1 S$G !en S$ 1V ?e.tState Q1 %dleG !en ot!ers 1V ?e.tState Q1 %dleG end caseG end "rocess ?e.tStateLogicG
5/11=
5/1$:
5/1$1
5/1$$
Ho
JusPin Q1 JidiP"adG "rocess 69nable+ JusPout8 is begin i' 69nable 1 @1A8 t!en JidiP"ad Q1 JusPoutG else JidiP"ad Q1 @RAG end i'G end "rocessG
JusPin
5/1$/
9nable JidiP"ad
JusPin
5/1$0
Ho
Digital design Combinatorial circuits Sequential circuits FSMD design VHDL
entit) Dullu"Pin is "ort 6 %nP"ad: in stdPlogicG CorePin: out stdPlogic8G end entit) Dullu"PinG arc!itecture 45L o' Dullu"Pin is com"onent D3LL3D "ort 6I: out stdPlogic8G end com"onent D3LL3DG
CorePin
com"onent %J3F "ort 6%: in stdPlogicG I: out stdPlogic8G end com"onent %J3FG signal Dumm): stdPlogicG begin Dumm) Q1 %nP"adG D3: com"onent D3LL3D "ort ma" 6Dumm)8G Ju': com"onent %J3F "ort ma" 6Dumm)+CorePin8G end arc!itecture 45LG
5/1$5
5/1$<
5/1$;