ARTICLE IN PRESS

INTEGRATION, the VLSI journal 42 (2009) 457467

Contents lists available at ScienceDirect

INTEGRATION, the VLSI journal

journal homepage: www.elsevier.com/locate/vlsi

A novel low-power full-adder cell for low voltage

Keivan Navi a,, Mehrdad Maeen b, Vahid Foroutan b, Somayeh Timarchi a, Omid Kavehei c
a b c

Faculty of Electrical and Computer Engineering, Shahid Beheshti University GC, Tehran, Iran Microelectronic LAB of Shahid Beheshti University and IAU, Tehran, Iran School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, SA 5005, Australia

a r t i c l e in fo
Article history: Received 14 April 2008 Received in revised form 20 January 2009 Accepted 2 February 2009 Keywords: Full adder Majority function Low power Very large-scale integrated (VLSI) circuit Performance analysis Static CMOS inverter MOSCAP

abstract
This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efciency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efciency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster. & 2009 Elsevier B.V. All rights reserved.

1. Introduction With the explosive growth in laptops, portable personal communication systems and the evolution of the shrinking technology, the research effort in low-power microelectronics has been intensied and low-power VLSI systems have emerged as highly in demand. Today, there is an increasing number of portable applications requiring small-area low-power highthroughput circuitry. Therefore, circuits with low power consumption become the major candidates [13] for design of microprocessors and system-components. The battery technology does not advance at the same rate as the microelectronics technology and there is a limited amount of power available for the mobile systems. The goal of extending the battery life span of portable electronics is to reduce the energy consumed per arithmetic operation, but low power consumption does not necessarily imply low energy. To execute an arithmetic operation, a circuit can consume very low power by clocking at extremely low frequency but it may take a very long time to complete the operation. Therefore, designers are faced with more constraints such as high speed, high throughput, small silicon area and at the

Corresponding author.

E-mail addresses: navi@sbu.ac.ir (K. Navi), mrc-ecef@sbu.ac.ir (M. Maeen), s_timarchi@sbu.ac.ir (S. Timarchi), kavehei@eleceng.adelaide.edu.au (O. Kavehei). 0167-9260/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2009.02.001

same time low power consumption. This is why building lowpower, high-performance adder cells is of great interest. Addition is one of the fundamental arithmetic operations and is used extensively in many VLSI systems. In addition to its main task, which is adding two binary numbers, it is the nucleus of many other useful operations such as subtraction, multiplication, division, address calculation, etc. [1,49]. In most of these systems, the adder is part of the critical path that determines the overall performance of the system and the full adder is the core element of complex arithmetic circuits. That is why enhancing the performance of the 1-bit full-adder cell (the building block of the binary adder) is considered a signicant goal. Lowering the supply voltage appears to be the most wellknown means to reduce power consumption. However, lowering supply voltage also increases circuit delay and degrades the drivability of cells designed with certain logic styles. Recently, clustered voltage scaling and dual voltage supply schemes have been proposed to maintain the chip throughput by selectively lowering the supply voltage for noncritical sub-circuits [10,11]. One of the objectives of this work is to design a circuit based on 0.18-mm CMOS process technology that can operate at ultralowpower supply voltage. One of the most important obstacles in decreasing supply voltage is the large transistor count and Vth loss problem. In nano-scaling, the biggest power consumption is static power dissipation. The proposed adder has very low short-circuit current

ARTICLE IN PRESS
458 K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467

and reduced transition activity compared with previously proposed low-power adders [12]. The energy consumption is measured by the product of average power and worst-case delay. The power-delay product (PDP) represents a tradeoff to be optimized between two conicting criteria of power dissipation and circuit latency. The rest of this paper is organized as follows. Section 2 explores a review of the full adder design in different logic styles. Creating a full adder by using Majority Function is proposed in Section 3. In Section 4, a new adder is presented and in Section 5 the circuits are simulated and the simulation results of power consumption, delay, power-delay product, area efciency and immunity to noise are analyzed and compared. Finally, Section 6 concludes the paper.

2. Review of full-adder designs There are standard implementations with various logic styles that have been used in the past to design full-adder cells and these are used for comparison in this paper. Although they all have similar function, the way of producing the intermediate nodes and the outputs, the loads on the inputs and intermediate nodes and

the transistor count are varied. Different logic styles tend to favor one performance aspect at the expense of the others. Some of them use one logic style for the whole full adder and others use more than one logic style for their implementation. We call them hybrid logic design style. The complementary CMOS full adder (C-CMOS) [1,1316] as shown in Fig. 1(a) is based on a regular CMOS structure with conventional pull-up and pull-down transistors and has 28 transistors. C-CMOS generates Cout throughout a single static CMOS gate. The input capacitance of a static CMOS gate is large because each input is connected to the gate of at least a PMOS and an NMOS device. Additional buffers at the last stage are needed to provide the required driving power because the series transistors in the output stage form a weak driver. The advantage of complementary CMOS style is its robustness against voltage scaling and transistor sizing. Another adder, shown in Fig. 2(b) is the complementary passtransistor logic (CPL) [1,13,14,16,17] with swing restoration, which uses 32 transistors. CPL produces many intermediate nodes and their complement to make the outputs. The basic difference between the pass-transistor logic style and the complementary CMOS logic style is that the source side of the pass logic transistor network is connected to some input signals instead of the power

Fig. 1. Full adder cells of different logic styles: (a) C-CMOS, (b) CPL, (c) TFA, (d) TGA, (e) 14T, (f) 10T and (g) Hybrid full adder.

ARTICLE IN PRESS
K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467 459

Fig. 1. (Continued)

Fig. 2. Majority Function.

lines [16,18]. One pass-transistor network is enough to implement the logic function; therefore results are generated by a smaller number of transistors and a smaller input load. When the transistor gates are oversized the inputs are overloaded and this creates high capacitance values. This problem occurs in CPL and CMOS. Pass-transistor logic has an intrinsic problem, which is threshold voltage drop, and output inverters are necessary to guarantee the drivability. CPL is not an appropriate choice for low power due to its high switching activity of intermediate nodes, high transistor count, static inverters and overloading of its inputs. Both circuits will be considered for comparison in this paper.

The other two full-adder designs contain transmission function full adder (TFA) [13,14,19] (Fig. 1(c)) and transmission gate full adder (TGA) [13,14,20] (Fig. 1(d)). These designs are based on transmission function theory and transmission gates and have 16 and 20 transistors, respectively. Transmission gate [18,20] consists of a PMOS transistor and an NMOS transistor that are connected in parallel way, which is a particular type of pass-transistor logic circuit. There is no voltage drop problem but it requires double the number of transistors to design a similar function. TFA and TGA are inherently low power consuming and they are good for designing XOR or XNOR gates [1315,21]. The main disadvantage of these logic styles is that they lack driving capability. When TGA or TFA are cascaded, their performance degrades signicantly. 14T in Fig. 1(e) [13,14,22] and 10T in Fig. 1(f) [13,23] use more than one logic style for their implementation and as already mentioned they are called Hybrid logic design style. They generate AB and use it and its complement as a select signal to generate the outputs. They benet from small transistor count and exploit the nonfull swing pass transistors with swing restored transmission gate techniques. The problem that produces high capacitance values for the inputs is less clear in these designs. 14T is low power implementation and it is worth mentioning that TGA, TFA, 10T and 14T have lower loading of the inputs and intermediate nodes, lower-transistor count and balanced generation of SUM and Cout signals. These full adders lack driving capabilities in fan-out situation and the their performance degrades drastically when they are cascaded. The last full-adder cell as shown in Fig. 1(g) is a Hybrid full adder [13]. In this design, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved. This full-adder cell can work at low supply voltage. It uses 26

ARTICLE IN PRESS
460 K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467

transistors but has the full swing logic, balanced output and good output drivability.

4. New majority function-based full adder The three-input majority not function is shown in Fig. 5. In order to create this function, it uses three-input capacitors that prepare an input voltage for driving the CMOS inverter. There are two ways to make the circuit shown in Fig. 5 working as a Majority Not Function. The rst method is the transistor sizing that shifts VTC into the left and right through changing the ratio of (W/L)n to (W/L)p. Rising this ratio moves VTC into the left therefore this circuit will operate as an NOR function. In reverse, decreasing that ratio makes NAND function. Appropriate values for these parameters should be found in order to create the Majority Not Function using this circuit. Fig. 6 shows the output waveforms of the circuit by changing the size of transistors. However, different functions are implemented with unique circuit and all of them can be designed by selecting correct values but in the presented full adder this circuit is only used as the Majority Not Function. This method suffers from an excessive power dissipation caused by the short-circuit current in a steady state and also during transient from high to low and vice versa when both transistors are on. The second method is based on high threshold voltages transistors [1,2431]. For implementing the Majority Not Function by the circuit shown in Fig. 5, high-Vt transistors have been used. The NMOS transistor must be turned on (Vgs4Vthn) and the output has to be low when at least two out of the three inputs are high and vice versa while two or three of inputs are low. The threshold voltage of the PMOS and NMOS transistors are 0.48 and 0.47 V, respectively. This method has the benet of a very low Pdirect path (Eq. (3)) and the short-circuit current. The circuit also is a ratio less one and in addition the energy consumed per switching activity is better: Ptot P dyn Pdp P state C L V DD2 f V DD Ileak   tr tf f V DD Ileak 2 (3)

3. Implementing full adder by means of Majority Function The Majority Function is a logic circuit that performs as a Majority vote to determine the output of the circuit. This function has only odd numbers of input and its output is equal to 1 when the number of inputs 1 is more than 0. Three-input and ve-input Majority Functions have been used in the proposed adder. Majority Functions with three and ve inputs are illustrated in Fig. 2(a) and (b), respectively. The full-adder operation can be stated as follows: given the three inputs A, B and C, it is desired to calculate two 1-bit outputs, SUM and Cout. Table 1 shows the truth table of Cout, SUM and three-input Majority Function. As the above table shows, Cout can be implemented with a three-input Majority Function. This fact is also proposed in Eq. (1) Cout AB AC BC (1)

If we invert the output of the circuit, Cout is produced with Majority Not Function circuit which is shown in Fig. 3. As Table 1 exhibits, SUM is different in merely two places with Majority Not Function; when inputs are 000 or 111. Therefore, SUM can be calculated with Cout as shown in Eq. (2): SUM Cout A B C ABC Majority A; B; C ; Cout ; Cout (2)

Consequently, according to this fact, SUM is generated by means of two Majority Not Functions as illustrated in Fig. 4. The rst one is a three-input Majority Not Function that makes Cout and the second one is a ve-input Majority Not Function which creates SUM .
Table 1 Truth table. A B C Cout SUM Majority Function Majority Not Function 1 1 1 0 1 0 0 0

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

0 1 1 0 1 0 0 1

0 0 0 1 0 1 1 1

Fig. 5. Three-input Majority Not Function.

Fig. 3. Majority Not Function.

Fig. 4. Majority Function-Based Full Adder.

Fig. 6. Output waveforms of the circuit by changing size of transistors.

ARTICLE IN PRESS
K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467 461

The reason which   results in low power dissipation is that the sum of Vtn and V tp  is larger than VDD (Eq. (4)) [1,16]; therefore to calculate the power consumption of this circuit Pdp can be ignored:   V DD oV tp  V tn (4)    Although lowering supply voltage and increasing Vtn and V tp  results in decreasing the power consumption, modifying threshold voltages and reducing supply voltage have direct impact on latency of the circuit and as shown in Eqs. (5) and (6) any increase in Vth or decrease in supply voltage causes reduction in the speed of the circuit: T P H !L C l V DD K n V dd V tn 2 C l V dd   K P V dd V tp 2 (5)

T PL!H

(6)
Fig. 8. Buffer circuit.

As shown in previous equations reducing the supply voltage will results in linear increase of latency and quadratic reduction of power consumption (Eq. (3)) resulting in improved PDP. In our rst attempt for designing full-adder cell, the Majority Not Function that has been shown in Fig. 5 is used for implementing Cout and then in the next level of the full-adder design as shown in Fig. 7 the SUM is implemented with a veinput Majority Not Function. Two capacitors that have been connected to Cout are parallel; hence, the capacitances of them can be added up. Each successive couple Inverter gates on top of Fig. 7 that provide A, B and C inputs for the ve-input Majority Not Function can be substituted with a new design of Buffer circuit that is shown in Fig. 8. Fig. 9 offers a new sketch that uses buffer circuit. In practice, there is no need for any kind of buffer and it can be eliminated. As shown in Fig. 10, the circuit uses only two Inverter gates. In Fig. 11, the static CMOS inverter has been used as an inverter gate. Cadence simulation shows 2.67 femto Farad is the minimum capacitance that is made at 0.18-mm technology. The proposed adder can work better with smaller capacitance values which can be made at higher technology such as 0.13 mm or nano-scaling and it exhibits that the new full-adder cell will achieve more performance in the future with these small sizes. The best values of capacitance at 0.18-mm CMOS technology obtained from Cadence simulation have been shown in Fig. 11. Since the outputs of this adder are Cout and SUM, in Fig. 12 two Inverters are attached to the circuit to make it comparable with the seven conventional full-adder cells. The addition of the inverters is just for comparison. Indeed there are not any general differences in practical environment among the adder cells which produce SUM and Cout or their inverts [32,33]. The presented

Fig. 9. Full adder cell.

Fig. 10. Proposed full-adder.

adder can work reliably without additional inverters but extra inverters enhance the driving capability of the adder cell.

5. Simulation results and analysis The investigation which includes the seven circuits C-CMOS, CPL, TFA, TGA, 14T, 10T, Hybrid full adder of Fig. 1 and the proposed adder, has been based on simulation runs on Cadence environment by using a 0.18-mm technology [1]. In this paper, post-layout simulations have been performed. For the seven circuits that have been shown in Fig. 1, the threshold voltages of

Fig. 7. Full adder cell.

ARTICLE IN PRESS
462 K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467

5.1. Area comparison Capacitors are implemented in two ways. metal-insulatormetal capacitance technology consumes an enormous chip area but, the new adders capacitors have been implemented using the MOS capacitors (MOSCAP) available in the 0.18-mm CMOS process technology. Tying the drain and source of a MOSFET together makes a MOSCAP. It can be seen from Fig. 14 that the length of the gate of the MOSCAP determines the capacitance value. The overlap, sidewall and fringe capacitances are between the gate and the drain or source. These capacitances are only dependent on the width of the MOSCAP. Gate to channel capacitance is dependent upon the area of the channel, or the MOSCAPs width and length. So the capacitance of the MOSCAP is directly dependent on the length and increasing the length of the MOSCAP increases this value. The smallest capacitance value of capacitor that could be implemented in 0.18-mm technology is 2.67 femto Farad, which require having a PMOS transistor with a width and length equal to the minimum value of this technology. Since this MOSCAP capacitance is dependent only upon the length of the channel, a linear increasing of the capacitance occurred by increasing the length of the MOSCAP in a linear manner. The layouts of these three MOSCAPs and a PMOS transistor are demonstrated in Fig. 15(a)(d). As shown in these gures, the area of 8.4 femto Farad MOSCAP is equal to 1.18 transistors with minimum length and also for 5.76 femto Farad the area is equal to 1.13 transistors with minimum length. The area of the new adder is approximately equal to a circuit with 15 transistors. By a perfect layout design even more reduction in the area is applicable and more compact design will be implemented. Fig. 15(e) shows an exact layout of the proposed full adder. On the left-hand side of this gure, there are three 8.4 femto Farad MOSCAPs and next to the three 8.4 femto Farad, there are three 2.88 femto Farad MOSCAPs followed by two PMOSs at the top and the bottom and in between a 5.76 femto Farad MOSCAP is placed. As shown in this gure, PMOSs and 2.88 femto Farad MOSCAPs occupy the equal area. This translates to have a minimum penalty from the area aspect, but as will be shown later, improvement in many parameters such as Delay, Power y are remarkable. The values of the length, width and overall area of the adder cells are listed in Table 2. The layouts of CPL and TGA full adders occupy the most silicon area. The presented full adder uses only two metal lines and CPL needs the most metal lines to connect the complementary inputs. TGA adder is composed of transmission gates, which has more area due to the inefcient usage of the ntype wells. The layout of the new cell occupies the smallest silicon area among all simulated full adder cells that are operable below 1 V. It is only slightly larger than 14T and 10T adders because of their number of transistors but, the overall performances of 10T and 14T are inferior at low supply voltage. In addition to all previous discussion which results in having an acceptable penalty in area due to improvement in manufacturing and implementation of capacitors more compatible capacitors with high capacitance value have been made. These new capacitors got their high capacitance value by reduction in the thickness of their oxide [3436] so capacitors with compact size are implemented with a little increase in length of the channel.

Fig. 11. Proposed full-adder with Static CMOS Inverter.

Fig. 12. Proposed full-adder with two extra Inverters.

the NMOS and PMOS transistors are around 0.39 and 0.42 V but the new full adder uses the high-Vt transistors with 0.47 and 0.48 V for NMOS and PMOS, respectively [1,2431]. The supply voltage is 0.8 V and since the smallest voltage that 10T can work at it is 1.8 V [1] furthermore, 14T cannot function under 1.0 V, will results in the supply voltage for them is 1.8 and 1 V, respectively. By optimizing the transistor sizes of full adders considered, it is possible to reduce the delay of all adders without signicantly increasing the power consumption, and transistor sizes can be set to achieve minimum PDP. All adders were designed with minimum transistor sizes initially and then simulated. Buffers are attached to the TFA, TGA, 14T and 10T circuits to enhance their driving capability. The inputs are fed from the buffers (two cascaded inverters) to give more realistic input signals. The output waveforms of each full adder are shown in Fig. 13. In this gure, two Inverters are attached to the new circuit to make it comparable with the seven conventional full-adder cells also delay, power and PDP comparisons are performed with these two extra inverters. Input test patterns do not cover every possible transition for a 1-bit full adder but, they contain transition with maximum delay for each adder cell in delay comparison. It is clear that input waveform affects delay and short-circuit power consumption. Hence, to avoid underestimating delay and power dissipation, realistic waveforms have been fed to A and B by inserting two symmetrical inverters between the ideal voltage sources and the input nodes, while carry input C has been obtained by inserting an equal full adder [1]. Since the proposed cell uses capacitors in its structure, implementing capacitor is explained in Section 5.1. Comparison of full adders is discussed below in ve subsections referred to AREA, DELAY, POWER, PDP and IMMUNITY to NOISE.

5.2. Delay comparison The values of power, delay and power-delay product of C-CMOS, CPL, TFA, TGA, 14T, 10T, hybrid and the new adder (with

ARTICLE IN PRESS
K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467 463

500m 0 800m 600m 400m 200m 0 500m 0 500m 0 500m 0 800m 600m 400m 200m 0 800m 600m 400m 200m 0 500m 0

Cout C-CMOS

SUM C-CMOS

Cout CPL

SUM CPL

Cout TFA

SUM TFA

Cout TGA

SUM TGA

500m 0

Cout 14T

500m 0 1.5 1 500m 0 1.5 1 500m 0 800m 600m 400m 200m 0 500m 0 800m 600m 400m 200m 0 500m 0 0 10n 20n 30n 40n Time (lin) (TIME) 50n 60n 70n

SUM 14T

Cout 10T

Sum 10T

Cout Hybrid

SUM Hybrid

Cout Proposed Adder SUM Proposed Adder 80n

Fig. 13. Comparison of output waveforms of the adder cells.

2 extra inverters) are presented in Table 3 for comparison. For each transition, the delay is measured from 50% of the input voltage swing to 50% of the output voltage swing. The maximum delay is taken as the cell delay. It is apparent that among the existing full adders, the 10T full adder has the smallest delay because of its supply voltage. As already mentioned the smallest

voltage that 10T can work at it is 1.8 V but the supply voltage for C-CMOS, CPL, TFA, TGA, hybrid and the proposed circuit is 0.8 V and for 14T is 1 V. The complementary pass-transistor logic full adder is 1.25 times faster than the new full adder, but this degradation is compensated with its improvement in power dissipation, and as we will see this design has better power-delay product.

ARTICLE IN PRESS
464 K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467

Fringe Fringe

Table 3 Simulation results for the proposed full adders in 0.18-mm technology and 0.8 V Vdd (supply voltage for 10T and 14T is 1.8 and 1 V). DESIGN Power (mW) 0.6126 0.8005 0.779 0.7604 1.1844 2.4498 0.5978 0.5451 Delay (ns) 0.681 0.51 0.776 0.685 0.5 0.395 0.672 0.687 PDP (fJ) 0.4172 0.4083 0.6045 0.5209 0.5922 0.9677 0.4017 0.3745

Gate Overlap Diffusion Channel

Sidewall Sidewall Diffusion

C-CMOS CPL TFA TGA 14T 10T Hybrid Proposed

Fig. 14. Illustration of the capacitances in a MOSCAP.

Table 4 Leakage power consumption at 0.8 V Vdd. Leakage power ( 109 W) P C-CMOS CPL TFA TGA Hybrid Proposed inputs 0 P inputs 1 P inputs 2 P inputs 3

3.82 1.594 1.89 2.05 2.06 1.91

5.27 1.677 2.47 2.7 2.21 2.56

5.72 1.702 2.88 3.02 3.33 2.18

6.48 1.667 2.11 2.35 2.58 2.34

0.43 C-CMOS 0.42 CPL 0.41 PDP (fj) 0.4 0.39 0.38 0.37 0.36 0.7 0.8 0.9 Vdd(V)
Fig. 15. Layout of all individual components and the compact layout of the new full adder: (a) PMOS transistor, (b) 2.8 femto Farad MOSCAP, (c) 5.76 femto Farad MOSCAP, (d) 8.4 femto Farad MOSCAP and (e) complete layout. Fig. 16. Power-delay-product comparison of full adders.

Hybrid FA-4T

1.1

Table 2 Area comparison of the full adders. C-CMOS CPL Length (mm) 17.45 7.11 Width (mm) 124.07 Area (mm2) TFA TGA 14T 10T Hybrid Proposed 11.43 8.51 97.26

11.20 9.58 14.07 12.10 11.2 9.85 12.20 10.08 9.59 6.11 6.30 10.97 136.36 96.57 134.88 73.93 70.56 108.05

proposed adder can function reliably at a supply voltage as low as 0.8 V. Among them CPL adder dissipation is always the highest; hence, the CPL topology not be used when the primary target is low consumption also its performance quickly degrades for low VDD [1]. Leakage power consumption of the proposed adder and some of the conventional adder cells that can work properly at 0.8 V Vdd also have been listed in Table 4 for comparison.

5.4. Power-delay product comparison 5.3. Power comparison The average power dissipation has been evaluated by applying casual pattern. Simulation results show that the new design consumes 11%, 31%, 30%, 28% and 8% less power than the C-CMOS, CPL, TFA, TGA and Hybrid. This is quite clear as the new design has much lower transistor count and has no Vth drop. The simulation results also exhibit that C-CMOS, TFA, TGA, CPL, Hybrid and the The PDP is a quantitative measure of the efciency and a compromise between power dissipation and speed. PDP is particularly important when low power operation is needed. As Table 3 shows, the PDP of Hybrid, C-CMOS, CPL and the presented full adders are small at very low voltage of 0.8 V and this new design has the best PDP in comparison with others. The PDP improvement of the new full adder is 10%, 8% and 7% in comparison with C-CMOS, CPL and Hybrid. As it can be seen the

ARTICLE IN PRESS
K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467 465

delay degradation in this design is compensated with the improvement in its power dissipation, leading to a better PDP. 5.5. Immunity to noise As mentioned in area comparison section, capacitors in the presented adder structure are implemented by means of MOS transistors. So this new design only consists of MOS transistor hence, it has not any extraordinary differences as compared with conventional adder circuits and it makes this circuit strong from the noise point of view. Simulations for delay, power and PDP comparison have been performed at 0.8Vdd supply voltage. The values of PDP evaluated
Table 5 Values of Delay and Power consumption in different temperatures. Design Temp 0 1C Delay (ns) C-CMOS CPL Hybrid Proposed 0.689 0.523 0.684 0.701 Power (mW) 0.609 0.791 0.588 0.52 Temp 70 1C Delay (ns) 0.68 0.547 0.666 0.663 Power (mW) 0.635 8.41 0.628 0.563

Table 6 Delay and power consumption of proposed adder in different capacitance values and threshold voltages. Delay (ns) C1 2.88 femto Farad, C2 8.4 femto Farad C1 4 femto Farad, C2 11 femto Farad C1 5 femto Farad, C2 15 femto Farad C1 6 femto Farad, C2 18 femto Farad C1 7 femto Farad, C2 21 femto Farad C1 8 femto Farad, C2 24 femto Farad C1 9 femto Farad, C2 26 femto Farad Vtn 0.41 V, Vtp 0.42 V Vtn 0.52 V, Vtp 0.53 V 0.687 0.692 0.69 0.688 0.711 0.705 0.718 0.647 0.708 Power (mW) 0.5451 0.5447 0.5459 0.5491 0.5476 0.5502 0.5513 0.5707 0.5018

by Cadence under different supply voltages (0.7, 0.8, 0.9, 1 and 1.1 V) are shown in Fig. 16. The comparison has been done among four circuits with better PDP in this range of VDD. This chart exhibits that the proposed adder is robust against voltage variation and the best value of PDP attains at 0.8 V. Operating at low VOLTAGE is an advantage of the circuits which is used for low power design. So the lowest supply voltage that circuits can work reliably with is considered in previous sections. Working with different supply voltage and having the best PDP between 0.7 and 0.9 V demonstrate that supply voltage variation noise does not affect the functionality of the circuit. For considering another aspect of noise immunity, the values of delay and power consumption for the proposed and some of conventional adder cells including C-CMOS, CPL and Hybrid in different temperatures are shown in Table 5. Simulation results in Table 3 measured in room temperature around 27 1C but, values of Table 5 attained in 0 and 70 1C with similar supply voltage to Table 3. As Table 5 shows lowering temperature decreases the power consumption and speed of circuits but any increase in temperature enlarges these parameters. It is also obvious from Table 5 that the new design can perform reliable in these temperatures and increasing or decreasing of delay and power consumption in 0 and 70 1C toward 27 1C is acceptable. In Table 6, the values of power and delay of the proposed adder are also calculated under different capacitance values and threshold voltages to evaluate susceptibility to these variations. Fig. 17 illustrates the output waveforms of the new circuit under different threshold voltages presented in Table 6. The output voltage values can also be obtained from this gure. Having correct operation and suitable voltage level for the SUM and Cout, prove that the proposed design is immune to these variations and has a large noise margin. In fact the most signicant noise is noisy input. This new design works at low supply voltage and input voltage of CMOS inverters is 2 0, 1 3V DD ; 3V DD or VDD when 0, 1, 2 or 3 of inputs are high. The main drawback of multiple value logic has always been the tolerance issue [9]. It is certain that the noise margin is reduced which make the circuit more susceptible to noise. Using more than eight levels face the circuits with serious sensibility to noise.

Fig. 17. Output waveforms of the proposed adder under different threshold voltages: (a) Vtn 0.52 V, Vtp 0.53 V, (b) Vtn 0.41 V and Vtp 0.42 V.

ARTICLE IN PRESS
466 K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467

The new design does not use higher voltage levels which results in having a small penalty from noise point of view. 6. Conclusion In this paper, a novel low-power Majority Function-based 1-bit full adder has been proposed. The proposed circuit uses only CMOS inverter and capacitance in its structure resulting in a signicant reduction in power consumption. In addition, some techniques to improve the speed of the circuit resulted in this new adder beneting from the best PDP and high performance. Simulation have been performed on Cadence environment and HSPICE by using a 0.18-mm technology to evaluate the new design and seven other adders, including 28-transistor complementary CMOS, CPL, TFA, TGA, 14T, 10T and Hybrid. Simulation results show the presented adder has the best PDP in comparison with the others. This adder consumes 11%, 31% and 8% less power compared with C-CMOS, CPL and Hybrid. The immunity to noise has been also evaluated in this paper. Consequently, this new design is appropriate to be applied for construction of large lowpower high-performance VLSI systems and it can work better in the future at higher technology such as 0.13 mm or nano-scaling.

Acknowledgement The authors would like to thank Dr. Belmond Yoberd for his literature contribution. References
[1] M. Alioto, G. Palumbo, Analysis and comparison of the full adder block, IEEE Trans. VLSI 10 (6) (December 2002) 806823. [2] R. Shalem, E. John, L.K. John, A novel low-power energy recovery full adder cell, in: Proceedings of the Great Lakes Symposium on VLSI, February 1999, pp. 380383. [3] R. Pedram, M. Pedram, Low Power Design Methodologies, Kluwer, Norwell, MA, 1996. [4] U. Ko, P. Balsara, W. Lee, Low-power design techniques for high performance CMOS adders, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 3 (2) (June 1995) 327333. [5] P.J. Song, G. De Micheli, Circuit and architecture trade-offs for high speed multiplication, IEEE J. Solid-Sate Circuits 26 (9) (September 1991) 11191184. [6] K. Navi, O. Kavehei, M. Rouholamini, A. Saha, S. Mehrabi, N. Dadkhani, Lowpower and high-performance L bit CMOS full adder cell, J. Comput. 3 (2) (February 2008). [7] M. Rahimi Azghadi, O. Kavehei, K. Navi, A novel design for quantum-dot cellular automat cell and full adders, J. Appl. Sci. 7 (22) (2007) 34603468. [8] M. Rouholamini, O. Kavehei, A. Mirbaha, S. Jasbi, K. Navi, A new design for 7:2 compressors, in: ACS/IEEE International Conference on Computer Systems and Applications, AICCSA, 2007. [9] D. Etiemble, K. Navi, Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system, in: Eleventh IEEE Symposium on Computer Arithmetic, 29 June2 July 1993. [10] T. Kuroda, M. Hamada, Low-power CMOS digital design with dual embedded adaptive power supplies, IEEE J. Solid-State Circuits 35 (4) (April 2000) 652655. [11] K. Usami, M. Horowitz, Clustered voltage scaling technique for low-power design, in: Proceedings of the International Symposium on Low Power Design, April 1995, pp. 38. [12] M. Haghparast, K. Navi, A novel reversible BCD adder for nanotechnology based systems, Am. J. Appl. Sci. 5(3) (2008) 282288, ISSN 1546-9239. [13] C.H. Chang, J. Gu, M. Zhang, A review of 0.18 um full adder performances for tree structure arithmetic circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13 (6) (June 2005). [14] A.M. Shams, T.K. Darwish, M.A. Bayoumi, Performance analysis of low-power 1-bit CMOS full adder cells, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10 (1) (February 2002) 2029. [15] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha, J. Chung, A novel multiplexerbased low-power full adder, IEEE Trans. Circuits Syst. II: Express Briefs 51 (7) (July 2004). [16] R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS versus passtransistor logic, IEEE J. Solid-State Circuits 32 (July 1997) 10791090. [17] S. Issam, A. Khater, A. Bellaouar, M.I. Elmasry, Circuit techniques for CMOS low-power high performance multipliers, IEEE J. Solid-State Circuits 31 (October 1996) 15351544. [18] M.M. Vai, VLSI Design, CRC Press, Boca Raton, FL, 2001.

[19] N. Zhuang, H. Wu, A new design of the CMOS full adder, IEEE J. Solid-State Circuits 27 (May 1992) 840844. [20] N. Weste, K. Eshraghian, Principles of CMOS VLSI Design. A System Perspective, Addison-Wesley, Reading, MA, 1993. [21] D. Radhakrishnan, Low-voltage low-power CMOS full adder, Proc. IEE Circuits Dev. Syst. 148 (1) (February 2001) 1924. [22] M. Vesterbacka, A 14-transistor CMOS full adder with full voltage swing nodes, Proc. IEEE Workshop Signal Process. Syst. (October 1999) 713722. [23] H.T. Bui, Y. Wang, Y. Jiang, Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates, IEEE Trans. Circuits Syst. II. Analog Digit. Signal Process. 49 (1) (January 2002) 2530. , Leakage-biased domino circuits for dynamic ne[24] Seongmoo Heo, K. Asanovic grain leakage reduction, in: VLSI Circuits Symposium, Honolulu, HI, June 2002. [25] T. McPherson, et al., 760 MHz G6 S/390 microprocessor exploiting multiple Vt and copper interconnects, in: ISSCC, 2000, pp. 9697. [26] A. Keshavarzi, et al., Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS Ics, in: ISLPED, August 2001, pp. 207212. [27] M.W. Allam, M.H. Anis, M.I. Elmasry, High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies, ISLPED (2000) 155160. [28] S. Mutoh, et al., IV power supply high-speed digital circuit technology with multithreshold-voltage CMOS, IEEE J. Solid-Sate Circuits 30 (8) (August 1995) 847854. [29] S.V. Kosonocky, et al., Enhanced multi-threshold (MTCMOS) circuits using variable well bias, ISLPED (August 2001) 165169. [30] T. Kuroda, et al., A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme, IEEE J. Solid-Sate Circuits 31 (11) (November 1996) 17701779. [31] J.T. Kao, A.P. Chandrakasan, Dual-threshold voltage techniques for low-power digital circuits, IEEE J. Solid-Sate Circuits 35 (7) (July 2000) 10091018. [32] Douglas A. Pucknell, Kamran Eshraghian, Basic VLSI Design, third ed., Prentice-Hall, Englewood Cliffs, NJ, 1994. [33] N. Weste, D. Harris, CMOS VLSI Design, Pearson/Wesley, 2005. [34] D.J. Webb, J. Fompeyrine, S. Nakagawa, A. Dimoulas, C. Rossel, M. Sousa, R. Germann, S.F. Alvarado, J.P. Locquet, C. Marchiori, H. Siegwart, A. Callegari, E. Kiewra, Y. Sun, J. De Souza, N. Hoffmann, In-situ MBE Si as passivating interlayer on GaAs for HfO2 MOSCAPs: effect of GaAs surface reconstruction, Microelectron. Eng. 84 (910) (September/October 2007) 21422145. [35] R. Das, M.K. Bera, S. Chakraborty, S. Saha, J.F. Woitok, C.K. Maiti, Physicochemical and electrical properties of rapid thermal oxides on Ge-rich SiGe heterolayers, Appl. Surf. Sci. 253 (3) (30 November 2006) 13231329. [36] K. Choi, P. Lysaght, H. Alshareef, C. Huffman, H.C. Wen, R. Harris, H. Luan, P.Y. Hung, C. Sparks, M. Cruz, K. Matthews, P. Majhi, B.H. Lee, Growth mechanism of TiN lm on dielectric lms and the effects on the work function, Thin Solid Films 486 (12) (22 August 2005) 141144. Keivan Navi received his B.Sc. and M.Sc. in Computer Hardware Engineering from Beheshti University in 1987 and Sharif University of Technology in 1990, respectively. He also received his Ph.D. of Computer Architecture from Paris XI University in 1995. He is currently associate professor in faculty of electrical and computer engineering of Beheshti University. His research interests include VLSI Design, Single Electron Transistors (SET), Carbon Nano Tube, Computer Arithmetic, Interconnection Network and Quantum Computing. He has published over 40 ISI and research journal papers and over 70 IEEE, international and national conference paper.

Mehrdad Maeen received his B.Sc. in Computer Architecture Engineering from faculty of electrical and computer engineering of Shahid Beheshti University in 2007. Currently, he is an M.Sc. student at the Tehran Science and Research Branch of Islamic Azad University under supervision of Dr. Keivan Navi. He has research interests in modeling and design of Ultra Low-Power VLSI circuits, Computer Arithmetic and Single Electron Transistors (SET).

Vahid Foroutan received his B.Sc. and M.Sc. in Computer Hardware Engineering from Azad University of Tehran Central Branch and Tehran science and research branch in 2004 and 2008, respectively. He is currently studying Computer Architecture in his Ph.D. degree. His research interests include VLSI Design, Computer Arithmetic and Computer Networks.

ARTICLE IN PRESS
K. Navi et al. / INTEGRATION, the VLSI journal 42 (2009) 457467 Somayeh Timarchi received her B.Sc. and M.Sc. in Computer Hardware Engineering from Shahid Beheshti University in 2002 and Sharif University of Technology in 2004, respectively. Currently, she is a Ph.D. student in Shahid Beheshti University. She is also a visiting researcher in the Engineering Department of the University of Siena, Italy. Her research interests include Computer Arithmetic, Residue and Redundant Number System, VLSI Design, modeling and design of Ultra Low-Power arithmetic circuits. 467

Omid Kavehei received his B.Sc. and M.Sc. in Computer Architecture Engineering from Arak Azad University and Shahid Beheshti University in 2003 and 2005, respectively. He is currently a postgraduate research student at the University of Adelaide, Centre for HighPerformance Integrated Technologies and Systems (CHiPTec). He has been pursuing teaching and research in the mainstreams of Computer-Aided Design (CAD), Numerical Methods, Robust Statistical Methods, Computer Arithmetic and Integrated Circuits in the general area of Integrated VLSI Systems. His research interest has particularly focused on the eld of robust design and optimization methods for Deep Sub-Micron (DSM) VLSI circuits with emphasis on low-power and highperformance circuit design.