Code No: R05410207

R05

Set No. 2

IV B.Tech I Semester Supplementary Examinations,June 2010 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain the following terms (a) Sheet resistance (Rs)

(b) Standard unit of capacitance (Cg)

(c) Discuss the possible choice of layers in VLSI design.

2. (a) What are the advantages of Hardware Description Languages and Software Languages?
(b) What are dierent design verication tools and explain them in brief? [8+8]

3. Design a stick diagram and layout for two input CMOS NAND gate indicating all the regions & layers [16]
4. Describe Ion implantation mechanism in IC fabrication.

5. (a) Explain dierent fault models in detail.

(b) Draw the general view of the TAP data register and explain how a boundary scan register is used for testing. [8+8]
6. (a) Explain the operation of nMOS inverter. Describe latch up condition in CMOS circuits.

(b) Draw the nMOS transistor circuit model and explain various components of the model. [8+8]
7. Develop a model for the read time of a ROM with 2n rows and 2m columns analogous to that of SRAM. Assume the wire capacitance in the ROM array is negligible compared to the gate and diusion capacitance. Assume the ROM cells are laid out such that two cells share a single diusion contact and hence each contributes only C/2 of diusion capacitance. [16] 8. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure?

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[16]

(b) Explain any one chip architecture that uses antifuse. Mention its advantages. tages. [8+8]

Code No: R05410207

R05

Set No. 4

IV B.Tech I Semester Supplementary Examinations,June 2010 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Derive an equation for rds of an n channel enhancement MOSFET in linear region. (b) Plot the transfer characteristic of an nMOS inverter as a function of Vds . [8+8] 2. (a) Write a architecture for a 4- bit Counter in both behavioral and structural styles.
(b) Explain with example how mixed mode simulator are more used for CMOS circuits testing. [8+8] 3. (a) Discuss the recent trends in IC Technology.

(b) What are the advantages of ICs over discrete components? (c) List the limitations of ICs.

4. Draw the stick diagram and mask layout for a CMOS two input NOR gate and stick diagram of two input NAND gate. [16]
5. Draw the structure of PLA and how the clocks are selected in PLA such that the OR plane outputs must be captured before the AND plane pre-charges ? What are the applications of it? [16]

6. Explain the scan-path design technique used to test sequential circuits in detail. [16] 7. (a) Draw the schematic for a multiplexer based shifter and explain the operation of a logical left shift and arithmetic right shift. (b) Design a fast 8-bit adder. The inputs may drive no more than 30 of transistor width each and the output must drive a 20/10 inverter. Determine its delay. [8+8]
8. Describe three sources of wiring capacitances. Explain the eect of wiring capacitance on the performance of a VLSI circuit. [16]

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[8+4+4]

Code No: R05410207

R05

Set No. 1

IV B.Tech I Semester Supplementary Examinations,June 2010 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What are dierent classes of Programmable CMOS devices? Explain them briey. (b) What is the basis for standard-cell? What are basic classes of circuits for Library cells? [8+8] 2. Implement following logic functions using CMOS logic (a) (A + B ) C (b) ((AB + C ) D).

3. (a) Explain the structure of MOS enhancement mode, Depletion mode and PMOS enhancement mode transistors. (b) Explain the working of an enhancement mode transistor with suitable diagrams. [12+4] 4. (a) For a 5m technology,the standard unit of capacitances for metal 1,polysilicon and n-diusion are 0.0075 Cg , 0.1 Cg and 0.25 Cg respectively. Calculate the capacitances for area shown in gure 4. Consider same area for calculation.

i. metal ii. polysilicon iii. n-diusion.

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[8+8]

(b) Impliment a 3-input NOR gate in dynamic logic and explain its operation. [8+8]

Figure 4 5. (a) What is BIST? Explain in detail. (b) Write the advantages of BIST. [10+6]

6. (a) What is Selected Signal Assignment Statement? Write a syntax in VHDL. 3

Code No: R05410207

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Set No. 1

(b) Explain how the timing analyzers are used to verify the functionality of CMOS chip. [8+8] 7. (a) Draw the top level schematic and a oor plan for 16 16 Booth recoded multiplier and explain its operation. (b) Explain the tradeos between open, closed, and twisted bit lines in a dynamic RAM array. [8+8] 8. (a) A CMOS inverter is built in a process where kn=100A/V 2 , Vtn =+0.7V, kp =42 A/V 2 , Vtp =-0.8V, and a power supply of VDD =3.33V is used .Find mid point voltage VM if (W/L)n =10 and (W/L)p = 14.
(b) Discuss the CMOS inverters transfer characteristics.

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[8+8]

Code No: R05410207

R05

Set No. 3

IV B.Tech I Semester Supplementary Examinations,June 2010 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Explain the CMOS system design based on the control structures with suitable example. (b) What are the dierent types of Memory elements? Compare them with respect to CMOS design. [8+8] 2. (a) What are the main categories of testing? Explain these with examples.

(b) Draw the block level implementation of a polarity hold SRL and explain its working. (c) How ROM memories can be tested?

3. Two NMOS inverters are cascaded to drive a capacity load CL = 14Cg as shown in gure 3. Calculate the pair delay Vin to Vout in terms of for the given data inverter-A. [16] Lpu =12, Wpu =4, Lpd =1, Wpd =8 Inverter-B Lpu =4, Wpu =4, Lpd =2, Wpd =8

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[6+6+4]

Figure 3 4. (a) Draw and explain the Vialink Structure for programming the PAL device. (b) What is CLB? Draw and explain the structure of it and also explain how these are used in FPGA. [8+8] 5. Design a stick diagram for nMOS EX-NOR gate. [16]

6. (a) With neat sketches explain how PNP transistor is fabricated in bipolar process. 5

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Set No. 3
[12+4]

(b) What is the dierence between bipolar and biCMOS technologies?

7. (a) Clearly explain the body eect of the MOSFET with necessary equations. (b) Clearly explain about channel length modulation of the MOSFET. [8+8]

8. (a) Compare the Concurrent signal assignments, sequential signal assignments and process statements. (b) Why resettable registers are preferable and what is the dierence between Synchronous and Asynchronous resets? [8+8]

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